Field of the Invention
The present invention relates to a display panel and a display device including the same and in particular, relates to suppression of a wire breakage and the like in a display panel.
Description of the Background Art
Display devices are widely adopted as user interfaces in various fields, and liquid crystal display devices using liquid crystals are mainstream of current display devices. A liquid crystal display device is provided with a thin film transistor (TFT) array substrate, a counter substrate disposed to face the TFT array substrate, and a liquid crystal layer provided therebetween.
In the TFT array substrate, a display region for displaying video and a circuit component mounting region on which circuit components are mounted are defined. The counter substrate of the liquid crystal display device is cut to expose the circuit component mounting region.
In a cutting process for exposing the circuit component mounting region, a sharp foreign matter is generated. Particularly, in a case of using a glass plate as the substrate, a foreign matter that is sharp and firm is generated. If such the foreign matter comes into contact with (adheres to) a surface of the TFT array substrate and an external force is applied to the foreign matter, a protective film (insulating film) and a wiring of the TFT array substrate may be damaged in some cases. Moreover, if an offcut formed in the cutting process comes into contact with the surface of the TFT array substrate, the protective film and consequently the wiring of the TFT array substrate may also be damaged in some cases.
As a result, a wiring is broken and a malfunction such as a line defect of the display occurs. In addition, a product separated in an inspection during a manufacturing process due to a line defect such as a wire breakage is eliminated, so that the wire breakage is one of the factors that reduce yields of products. Moreover, in the case where a product with damage which does not cause a wire breakage during the manufacturing process passes the inspection, there is a possibility that a line defect may occur after shipment.
About this, Japanese Patent Application Laid-Open No. 2010-230885 discloses a technique for suppressing an impact on the TFT array substrate at the time of cutting the counter substrate. Specifically, Japanese Patent Application Laid-Open No. 2010-230885 discloses the technique capable of reducing an impact on the wiring disposed as a lower layer and preventing a wire breakage by forming a pattern in a floating potential state on the wiring connecting the display region and the circuit component mounting region.
In the configuration of Japanese Patent Application Laid-Open No. 2010-230885, the pattern serving as a shock absorbing layer is further formed on a plurality of wirings, respectively, so that the shock absorbing layer reduces the impact on the wirings as the lower layer. Unfortunately, the entire film thickness of a laminated film (such as the shock absorbing layer and insulating layer) on the wirings is significantly thick, and thus there is a higher probability to come into contact with a foreign matter, whereby there is a possibility that the laminated film is destroyed and the wirings are exposed. When the wirings are exposed, they become susceptible to moisture and the like from the outside, and there is a higher possibility that a malfunction such as a wire breakage occurs because electric corrosion is induced as the wirings are energized.
It is an object of the present invention to provide a technique capable of suppressing a malfunction such as a wire breakage between a display region and a circuit component mounting region.
A display panel of the present invention includes a first substrate, in which a display region that displays video and a circuit component mounting region on which circuit components are mounted are defined, and a second substrate disposed to face the display region of the first substrate, an end of the second substrate being cut to expose the circuit component mounting region of the first substrate. The first substrate includes a plurality of first wirings formed from the display region to the circuit component mounting region and a wiring protection pattern formed in a region corresponding to cut the end of the second substrate between any adjacent first wirings. In a cross sectional view, an upper end of the wiring protection pattern is located above an upper end of the first wirings.
An upper end of a wiring protection pattern is formed to be positioned above a first wiring, which prevents the first wiring from coming in contact with a foreign matter. Therefore, a malfunction such as a wire breakage by a cut end of a second substrate can be suppressed.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
A preferred embodiment of the present invention is described below with reference to the drawings.
Dimensions, materials, shapes, and relative positions of respective structural elements shown as examples in the preferred embodiment are changed suitably depending on a structure of an apparatus to which the present invention is applied and various conditions and the present invention is not restricted to the examples. The dimensions of the respective structural elements in the respective drawings may be different from actual dimensions.
The display panel 1 is provided with a first substrate 11 such as the TFT array substrate and the like, a second substrate 21 such as a color filter substrate and the like disposed to face the first substrate 11, flexible printed circuits (FPCs) 31, an aftermentioned seal member 41, and an aftermentioned liquid crystal layer 42. In
The first substrate 11 includes a glass substrate 12 being a transparent substrate, a plurality of source wirings 13, a plurality of gate wirings 14, and a plurality of TFTs (switching elements) which are not shown. In the first substrate 11 configured in this manner, a display region 11a that displays video (image) and a circuit component mounting region 11b on which circuit components are mounted are defined. Next, the display region 11a and the circuit component mounting region 11b will be described.
The plurality of TFTs are formed in a matrix, and the plurality of source wirings 13 (signal wirings) and the plurality of gate wirings 14 (scanning wirings) are provided to cross one another on the glass substrate 12 of the display region 11a. The plurality of source wirings 13 transmit data signals to the plurality of TFTs, respectively. The plurality of gate wirings 14 transmit select signals, which are for selectively transmitting the data signals, to the plurality of TFTs, respectively. Each of the TFTs configures pixels (pixel section) that make a change to an alignment direction and consequently a polarization direction of the liquid crystals of the liquid crystal layer 42 based on the signals from the source wirings 13 and the gate wirings 14 in order to make a change to light transmittance. In this manner, the light transmittance is selectively changed in the pixels to display video in the display region 11a.
The plurality of source wirings 13 are formed on the glass substrate 12 along x direction (here, long-side direction of the display panel 1) from the display region 11a to the circuit component mounting region 11b. Similarly, the plurality of gate wirings 14 are formed on the glass substrate 12 along y direction (here, short-side direction of the display panel 1) from the display region 11a to the circuit component mounting region 11b. In
Next, the circuit component mounting region 11b is described. As shown in
In the following description, the end which is cut in the second substrate 21 is referred to as a “cut end 21a”. Moreover, a line corresponding to a shape of the cut end 21a in the plan view (
Circuit components are mounted on the circuit component mounting region 11b of the first substrate 11. Here, the circuit components are described as the FPCs 31 on which a driver integrated circuit (IC) and a power source for driving the driver IC are mounted.
First, the second substrate 21, the seal member 41, and the liquid crystal layer 42, as mentioned above, provided in the display panel 1 will be described below.
As shown in
The seal member 41 is a member which connects the first substrate 11 and the second substrate 21 and it is formed between the first substrate 11 and the second substrate 21. The seal member 41 is formed on a main surface of the first substrate 11 on the second substrate 21 side and on a main surface of the second substrate 21 on the first substrate 11 side. Here, the seal member 41 is formed in a black matrix region of the outermost peripheral display region 11a, and a part of the seal member 41 is formed in the vicinity of the boundary (the cut end 21a) between the display region 11a and the circuit component mounting region 11b.
The liquid crystal layer 42 is formed such that a space surrounded by the first substrate 11, the second substrate 21, and the seal member 41 is filled up with the liquid crystals. Although it is not shown, an alignment film for regulating the alignment direction of the liquid crystals is formed on the main surface of the first substrate 11 on the liquid crystal layer 42 side and on the main surface of the second substrate 21 on the liquid crystal layer 42 side. Furthermore, in order to make the presence of the liquid crystal layer 42 clear,
Next, a configuration, which has not been described, of the aforementioned first substrate 11 will be described. The first substrate 11 is configured to include the glass substrate 12, the plurality of source wirings 13, and the plurality of gate wirings 14 that are mentioned above. In addition to these, the first substrate 11 is configured to include an interlayer insulating film 15 (
In the first preferred embodiment, as shown in
The first source wiring 13b is formed on the glass substrate 12 (
The interlayer insulating film 15 used as a gate insulating film is formed on the glass substrate 12 so as to cover the first source wiring 13b and the gate wirings 14. For example, a silicon nitride film is used for the interlayer insulating film 15.
An amorphous silicon film, not shown, the second source wiring 13c (
As shown in
The protective insulating film 17 is formed on the second source wiring 13c and the interlayer insulating film 15 (
The transparent electrode 13d is connected to one end of the first source wiring 13b through contact holes of the interlayer insulating film 15 and the protective insulating film 17, and it is connected one end of the second source wiring 13c through a contact hole of the protective insulating film 17. Thus, the first source wiring 13b and the second source wiring 13c are electrically connected to each other.
The transparent electrode 13e is connected to the other end of the first source wiring 13b through contact holes of the interlayer insulating film 15 and the protective insulating film 17 to configure terminals 13a.
Next, a process of manufacturing the first substrate 11 (TFT substrate) will be described with reference to
First, while the gate wirings 14 are formed, a process of forming the first source wiring 13b as shown in
Then, as shown in
Next, as shown in
In the cross sectional view (B-B′ cross sectional view), to easily form the configuration such that the upper end of the wiring protection pattern 16 is located above the upper end of the first source wiring 13b, it is preferable that the metal film of the wiring protection pattern 16 (the second source wiring 13c) has a greater film thickness than that of the first source wiring 13b. However, it is not limited to this as long as the upper end of the wiring protection pattern 16 is located above the upper end of the first source wiring 13b.
As shown in
As shown in
Finally, as shown in
After that, a counter substrate 26 having the substantially same size as the first substrate 11 is provided to face the first substrate 11. This counter substrate 26 is a substrate to be the second substrate 21 and a substrate that is not given a cut to expose the circuit component mounting region 11b.
A manufacturing process before providing the counter substrate 26 to face the first substrate 11 is described below.
First, the laminated film 23 such as the black matrix layer, the color material layer, and the transparent electrode is formed on the glass substrate 22 to form the counter substrate 26. In addition, the black matrix layer is provided in the outermost peripheral black matrix region of the display region 11a. In other words, the black matrix layer (region) is provided outside the display region 11a.
The alignment film is applied to each surface of the first substrate 11 and the counter substrate 26, and the alignment films are processed by a rubbing cloth (application of the alignment film and the rubbing cloth are not shown). Then, the seal member 41 is applied to the black matrix region of the counter substrate 26. The counter substrate 26, to which the seal member 41 is applied, is arranged on top of the first substrate 11, and the seal member 41 connects the counter substrate 26 and the first substrate 11.
Subsequent to the connection, as shown in
The incision 26a is formed at the position to be the cut line mentioned above (the boundary between the display region 11a and the circuit component mounting region 11b of the first substrate 11), in other words, the incision 26a is formed above the wiring protection pattern 16. One example is shown in
After that, the point where the incision 26a is positioned is pressurized and is broken as shown in
After that, the space surrounded by the first substrate 11, the second substrate 21, and the seal member 41 is filled up with the liquid crystals to form the liquid crystal layer 42. Then, the FPCs 31 are mounted on the circuit component mounting region 11b. In this manner, the display panel 1 is manufactured.
To describe the effect of the display panel 1 manufactured in the manner above, a related display panel that relates to the display panel 1 is described next.
In the process shown in
When the contact mentioned above causes a serious damage on the first source wiring 13b, a wire breakage and the like occur in the first source wiring 13b, and thus a malfunction such as a line defect of the display occurs. Perhaps, when the first source wiring 13b is not damaged, however the protective insulating film 17 is seriously damaged such that the first source wiring 13b are exposed, the first source wiring 13b is influenced by moisture from the outside which induces electric corrosion as the wiring is repeatedly energized, whereby there is a possibility that the wire breakage occurs in the first source wiring 13b.
In contrast, in the first preferred embodiment, as shown in
In the first preferred embodiment, the wiring protection pattern 16 is formed of the same metal film as that of the second source wiring 13c, so that they can be formed in the same process to allow the manufacturing process to be simplified.
It is preferable that the wiring protection pattern 16 is formed of a metal film having higher hardness than a metal film of the first source wiring 13b such that, for example, the first source wiring 13b is formed of aluminum film and the wiring protection pattern 16 is formed of copper film.
As shown in
In the descriptions above, it is described that the first wiring is the first wiring 13b, however it is not limited to this. For example, the first wiring may be the gate wirings 14 and the wiring protection pattern similar to the one in the descriptions above may be formed in regard to the gate wirings 14.
In addition, according to the present invention, the preferred embodiment can be appropriately varied or omitted within the scope of the invention.
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
Number | Date | Country | Kind |
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2013-010036 | Jan 2013 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
6480255 | Hoshino et al. | Nov 2002 | B2 |
6977708 | Tanaka | Dec 2005 | B2 |
8013454 | Yamashita | Sep 2011 | B2 |
20020085137 | Fujikawa | Jul 2002 | A1 |
20080007667 | Nakayama | Jan 2008 | A1 |
Number | Date | Country |
---|---|---|
2000-029061 | Jan 2000 | JP |
2000-194013 | Jul 2000 | JP |
2001-305569 | Oct 2001 | JP |
2009-229969 | Oct 2009 | JP |
2010-230885 | Oct 2010 | JP |
Entry |
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An Office Action; “Notification of Reason(s) for Refusal” issued by the Japanese Patent Office on Nov. 1, 2016, which corresponds to Japanese Patent Application No. 2013-010036 and is related to U.S. Appl. No. 14/156,411; with English language translation. |
Number | Date | Country | |
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20140204324 A1 | Jul 2014 | US |