Patent Grant
12087227
The present application claims priority to Chinese Patent Application No. 202310695462.9, filed on Jun. 12, 2023, the content of which is incorporated herein by reference in its entirety.
The present disclosure relates to the technical field of display, and in particular to a display panel, a method for driving a display panel, and a display apparatus.
With the development of display technology, a display panel can display information at different refresh frequencies in different modes. For example, the display panel displays, using a high refresh frequency, dynamic frames (such as sports events or games) so as to ensure the smoothness of the display images, and displays, using a lower refresh frequency, static frames so as to reduce its power consumption.
However, at present, when the display panel is driven at a low refresh frequency, flicker may occur on the display panel.
Embodiments of the present disclosure provide a display panel, a method for driving a display panel, and a display apparatus, having less flicker in a low-frequency display mode.
In an aspect, a display panel is provided. The display panel includes a light-emitting element and a pixel driver circuit electrically connected to the light-emitting element. The pixel driver circuit includes a driver transistor and a first light emission control switch. The driver transistor includes a gate electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node. The first light emission control switch is electrically connected between the third node and the light-emitting element.
A working mode of the display panel includes a first mode. In the first mode, a working cycle of the pixel driver circuit includes a data writing phase and at least one data holding phase after the data writing phase. The data writing phase includes at least one first light-emitting period. The data holding phase includes at least one second light-emitting period. In the first light-emitting period and the second light-emitting period, the first light emission control switch is turned on.
The display panel further includes a control circuit. The control circuit controls a duration of a first one of the at least one first light-emitting period in the data writing phase to be less than a duration of one of the at least one second light-emitting period.
In another aspect, a method for driving a display panel is provided. The display panel includes a light-emitting element and a pixel driver circuit electrically connected to the light-emitting element. The pixel driver circuit includes a driver transistor and a first light emission control switch. The driver transistor includes a gate electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node. The first light emission control switch is electrically connected between the third node and the light-emitting element. A working mode of the display panel includes a first mode. In the first mode, a working cycle of the pixel driver circuit includes a data writing phase and at least one data holding phase after the data writing phase. The data writing phase includes at least one first light-emitting period. The data holding phase includes at least one second light-emitting period. In the first light-emitting period and the second light-emitting period, the first light emission control switch is turned on.
The driving method includes controlling a duration of a first one of the at least one first light-emitting period in the data writing phase to be less than a duration of one of the at least one second light-emitting period.
In yet another aspect, provided is a display apparatus including the above display panel.
Static frames are displayed by the display panel in the first mode, the data refresh frequency of the display panel is reduced, and the power consumption of the display panel when displaying static frames or when in an always on display (AOD) mode is reduced.
In the first mode, the duration of the first one of the at least one first light-emitting period in the data writing phase is less than the duration of one of at least one second light-emitting period. This can reduce the brightness of the light-emitting element in the data writing phase, thereby compensating for the brightness reduction of the light-emitting element in the data holding phase, caused by the change in the potential of the first node due to the leakage current. In this way, the brightness consistency of the light-emitting element in the data writing phase and data holding phase is improved, thereby alleviating the flicker problem.
To describe the technical solutions in the embodiments of the present disclosure more clearly, the following briefly describes the accompanying drawings used in the embodiments. The accompanying drawings in the following description show merely some embodiments of the present disclosure, and a person of ordinary skill in the art may derive other accompanying drawings from these accompanying drawings.
For the sake of a better understanding of the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
It should be noted that the embodiments in the following descriptions are merely some rather than all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art on the basis of the embodiments of the present disclosure shall fall within the protection scope of the present disclosure.
Terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Unless otherwise specified in the context, words, such as “a”, “the”, and “this”, in a singular form in the embodiments of the present disclosure and the appended claims include plural forms.
It should be understood that the term “and/or” in this specification merely describes associations between associated objects, and it indicates three types of relationships. For example, A and/or B may indicate that A exists alone, A and B coexist, or B exists alone. In addition, the character “/” in this specification generally indicates that the associated objects are in an “or” relationship.
It should be understood that although the terms first, second, third, and the like may be used to describe nodes in the embodiments of the present disclosure, these nodes should not be limited to these terms. These terms are merely used to distinguish the nodes from one other. For example, without departing from the scope of the embodiments of the present disclosure, a first node can also be referred to as a second node. Similarly, a second node can also be referred to as a first node.
Embodiments of the present disclosure provide a display panel.
The pixel driver circuit 12 includes a driver transistor M0, a storage capacitor Cst, a first reset switch 21, a data writing switch 22, a threshold compensation switch 23, a first light emission control switch 24, and a second light emission control switch 25. The driver transistor M0 includes a gate electrically connected to a first node N1, a first electrode electrically connected to a second node N2, and a second electrode electrically connected to a third node N3. It should be noted that in the embodiment of the present disclosure, the first node N1, the second node N2, and the third node N3 are only defined for the convenience of describing the structure of the pixel driver circuit 12. Therefore, the first node N1, the second node N2, and the third node N3 are not necessarily actual circuit units. In some embodiments, each of the first reset switch, the data writing switch, the threshold compensation switch, the first light emission control switch, and the second light emission control switch includes one or more transistors.
As shown in
A working mode of the display panel includes a first mode and a second mode. A data refresh frequency in the first mode is lower than a data refresh frequency in the second mode. Exemplarily, the data refresh frequency in the first mode may be less than 60 Hz. For example, the data refresh frequency in the first mode is 10 Hz, 15 Hz or 30 Hz. The data refresh frequency in the second mode may be greater than or equal to 60 Hz. For example, the data refresh frequency in the second mode is 60 Hz, 75 Hz or 120 Hz.
The sub-pixels are arranged in multiple rows. During an image frame, the pixel driver circuits 12 in the sub-pixels are enabled/scanned row by row to input data voltages corresponding to the current frame to the sub-pixels.
As shown in
Exemplarily, referring to
When the display panel is working in the first mode, as shown in
In the data writing period b, the first reset switch 21 is turned off, the data writing switch 22 is turned on by a signal provided by a second scan control signal terminal SP, and the threshold compensation switch 23 is turned on by a signal provided by a third scan control signal terminal S2N. The data signal terminal Vdata inputs a data voltage corresponding to the current working cycle T to the first node N1 through the data writing switch 22. Meanwhile, the threshold compensation switch 23 detects and compensates for a deviation of a threshold voltage Vth of the driver transistor M0 at this phase. When the potential of the first node N1 reaches Vd−|Vth|, the driver transistor M0 is turned off, completing the capture of the threshold voltage Vth of the driver transistor M0. Vd denotes a data voltage provided by the data signal terminal Vdata corresponding to the current working cycle T.
In the first light-emitting period c1, the first reset switch 21, the data writing switch 22, and the threshold compensation switch 23 are turned off. The potential of the first node N1 is maintained by the storage capacitor Cst. The first light emission control switch 24 is turned on by a signal provided by a light emission control signal terminal E. The second light emission control switch 25 is turned on by the signal provided by the light emission control signal terminal E. The driver transistor M0 is turned on by the first node N1. Under the action of a driving current generated by the driver transistor M0, the light-emitting element 11 emits light.
Exemplarily, as shown in
After the data writing phase T1, the pixel driver circuit 12 enters the data holding phase T2. As shown in
In the embodiment of the present disclosure, a duration of the first one of the first light-emitting periods c1 in the data writing phase T1 is denoted as Bi1, and a duration of a j-th one of the second light-emitting periods c2 in the i-th data holding phase T2 is denoted as Bij. Both i and j are integers, 1≤i≤n, and 1≤j≤m.
As shown in
Optionally, as shown in
In the embodiment of the present disclosure, the working mode of the display panel includes the first mode, such that static frames can be driven in the first mode, thereby reducing the data refresh frequency of the display panel, and reducing the power consumption of the display panel in the display of static frames or in an always on display (AOD) mode.
As shown in
As shown in
Exemplarily, referring to
In the embodiment of the present disclosure, the control circuit (not shown in
Exemplarily, the following method is used to make the duration B01 of the first-one first light-emitting period c1 in the data writing phase T1 less than the duration of each of at least one second light-emitting period c2 in the data holding phase T2.
A reference light emission control signal refers to a light emission control signal with the duty cycle of each high-level pulse in the data writing phase T1 the same as the duty cycle of each high-level pulse in the data holding phase T2. For example, compared to the reference light emission control signal, in the embodiment of the present disclosure, a rising edge of a first high-level pulse of the light emission control signal in the data writing phase T1 is moved forward, and/or, a falling edge of the first high-level pulse of the light emission control signal in the data writing phase T1 is moved backward.
Alternatively, in the embodiment of the present disclosure, the rising edge of at least one high-level pulse of the light emission control signal in the data holding phase T2 is moved backward compared to the reference light emission control signal, and/or, the falling edge of at least one high-level pulse of the light emission control signal in the data holding phase T2 is moved forward compared to the reference light emission control signal.
Exemplarily, as shown in
Optionally, as shown in
Optionally, the first reset period a or the data writing period b may be reused as the second reset period. For example, in
Exemplarily, as shown in
Optionally, in the embodiment of the present disclosure, at least one of the first transistor M1 and the third transistor M3 includes an oxide transistor to reduce an off-state leakage current of the first transistor M1 or the third transistor M3, thereby reducing the impact of the leakage current on the potential of the first node N1 and improving the potential stability of the first node N1. The design improves the stability of the driving current flowing through the light-emitting element 11 during different light-emitting periods within a working cycle T, so as to further improve the uniformity of the brightness of the light-emitting element 11 and alleviate the flicker problem.
Exemplarily, as shown in
Exemplarily, in one or more embodiments of the present disclosure, m=2 and k×N=4. In another embodiment of the present disclosure, k=1 and N=4. Alternatively, k=2 and N=2.
In the embodiment of the present disclosure, N≥2. Thus, each light emission control sub-circuit 30 can drive more pixel driver circuit rows 40, thereby reducing the number of light emission control sub-circuits 30. The design can narrow a bezel of the display panel and increase a screen-to-body ratio of the display panel. Compared with the conventional method in which each light emission control sub-circuit drives one pixel driver circuit row, the above arrangement can reduce the frequency of a light emission clock signal for controlling the light emission control sub-circuit 30, thereby reducing the power consumption of the light emission control unit 30.
Exemplarily, if the data holding phase T2 includes at least two second light-emitting periods c2, the durations of the at least two second light-emitting periods c2 in the same data holding phase T2 may be arranged as following. In some embodiments of the present disclosure, Bi1≤Bi2≤ . . . ≤Bim, i being any integer from 1 to n. That is, duty cycles of a plurality of high-level pulses of the light emission control signal in the same data holding phase T2 sequentially decrease. As shown in
Exemplarily, when a working cycle T of the pixel driver circuit 12 includes a plurality of data holding phases T2, in the embodiment of the present disclosure, B1j≤B2j≤ . . . ≤Bnj, j being any integer from 1 to m. The duty cycles of the corresponding high-level pulses of the light emission control signal transmitted by the light emission control signal terminal E in different data holding phases T2 sequentially decrease to compensate for the impact of the leakage current on the brightness, so as to further alleviate the flicker problem in the first mode.
Exemplarily, when the data holding phase T2 includes at least two second light-emitting periods c2, that is, when m≥2, in the embodiment of the present disclosure, the second light-emitting periods c2 in the data holding phase T2 and the corresponding second light-emitting periods c2 in other data holding phase T2 meet the above relationship. In the example embodiment shown in
Referring to
Optionally, when n≥2, the n data holding phases T2 at least include an (i−1)-th data holding phase T2 and an i-th data holding phase T2 that are adjacent. The duration of an m-th second light-emitting period c2 in the (i−1)-th data holding phase T2 is less than or equal to the duration of a first-one second light-emitting period c1 in the i-th data holding phase T2. In some embodiments of the present disclosure, B(i−1)m<Bi1. B(i−1)m denotes the duration of the m-th second light-emitting period c2 in the (i−1)-th data holding phase T2, and Bi1 denotes the duration of the first-one second light-emitting period c2 in the i-th data holding phase T2. Referring to
Exemplarily, as shown in
Exemplarily, among the m first light-emitting periods c1 of the data writing phase T1, m being an integer greater than or equal to 2, there at least exist two adjacent first light-emitting periods c1. The duration of a previous first light-emitting period c1 of the two adjacent first light-emitting periods c1 is less than the duration of a subsequent first light-emitting period c1 of the two adjacent first light-emitting periods c1. Since the duration of the previous first light-emitting period c1 is less than the duration of the subsequent first light-emitting period c1, the change in the potential of the first node N1 due to the leakage current during the data writing phase T1 is compensated for, thereby alleviating the flicker problem during the data writing phase T1. Referring to
Exemplarily, as shown in
Exemplarily, as shown in
Specifically, when the display panel displays a low gray-scale image, the light emission delay effect in the data writing phase T1 with respect to the data holding phase T2 is more significant. If the duration of the first-one first light-emitting period c1 in the data writing phase T1 is the same as the duration of the second light-emitting period c2 in the data holding phase T2, the brightness in the data writing phase T1 is less than the brightness of the data holding phase T2. In some embodiments of the present disclosure, the duration of the first-one first light-emitting period c1 is shortened, and the bias of the driver transistor M0 is adjusted in the data holding phase T2, so as to reduce the brightness of the light-emitting element 11 in the data holding phase T2. The design ensures that the brightness of the light-emitting element 11 in the data writing phase T1 is close to the brightness thereof in the data holding phase T2, thereby alleviating the flicker problem of the display panel in the first mode.
When the display panel displays a high gray-scale image, a bias voltage of the driver transistor M0 in the data writing phase T1 is relatively weak. The light emission delay effect in the data writing phase T1 with respect to the data holding phase T2 is weaker. If the duration of the first-one first light-emitting period c1 in the data writing phase T1 is the same as the duration of the second light-emitting period c2 in the data holding phase T2, the brightness in the data writing phase T1 is greater than the brightness in the data holding phase T2. In embodiments of the present disclosure, based on the above method, the brightness of the light-emitting element 11 in the data writing phase T1 and the data holding phase T2 is reduced, and thus the brightness difference of the light-emitting element 11 in the data writing phase T1 and the data holding phase T2 perceived by human eyes is reduced, avoiding the deterioration of the flicker problem.
Referring to Table 1, Table 1 provides simulation data for flicker values (in dB) of display panels with different timing designs at different gray-scales. A larger absolute value of a flicker value indicates a weaker flicker level. The highest gray-scale 255 corresponds to a brightness of 300 nit. The data refresh frequencies in Comparative Example 1, Comparative Example 2, and Embodiment are all 10 Hz. In Comparative Example 1, the data holding phase T2 does not include the bias adjustment period e, and the duration of the first one of the first light-emitting periods c1 is the same as the duration of the second light-emitting period c2. In Comparative Example 2, the data holding phase T2 includes the bias adjustment period e, and the duration of the first one of the first light-emitting periods c1 is the same as the duration of the second light-emitting period c2. In Embodiment, the data holding phase T2 includes the bias adjustment period e, and the duration of the first one of the first light-emitting periods c1 is less than the duration of the second light-emitting period c2. Compared to Comparative Example 1 and Comparative Example 2, the flicker problem in low gray-scale display in Embodiment is significantly alleviated, and the flicker level in high gray-scale display in Embodiment is reduced, without deterioration.
Exemplarily, as shown in
Optionally, referring to
Exemplarily, as shown in
Exemplarily, as shown in
Embodiments of the present disclosure further provide a method for driving a display panel. As shown in
A working mode of the display panel includes a first mode. In the first mode, as shown in
The driving method according to the embodiment of the present disclosure includes the following steps.
A duration of a first one of the at least one first light-emitting period c1 in the data writing phase T1 is less than a duration of each of the at least one second light-emitting period c2 in the data holding phase T2.
In the embodiments of the present disclosure, the working mode of the display panel includes the first mode, and static frames can be driven in the first mode, thereby reducing the data refresh frequency of the display panel, and reducing the power consumption of the display panel when displaying static frames or when in an always on display (AOD) mode. In the embodiments of the present disclosure, the duration Bi1 of the first one of the at least one first light-emitting period c1 in the data writing phase T1 is less than the duration of one of at least one second light-emitting period c2 in the data holding phase T2. This can reduce the brightness of the light-emitting element 11 in the data writing phase T1, thereby compensating for the brightness reduction of the light-emitting element 11 in the data holding phase T2, caused by the change in the potential of the first node N1 due to the leakage current. In this way, the brightness consistency of the light-emitting element 11 in the data writing phase T1 and data holding phase T2 is improved, thereby alleviating the flicker problem.
Exemplarily, in the embodiments of the present disclosure, the duration of the first one of the at least one first light-emitting period c1 in the data writing phase T1 of the pixel driver circuit 12 is denoted as Bi1. A working cycle T of the pixel driver circuit 12 includes n data holding phases T2, and each data holding phase T2 includes m second light-emitting periods c2. A duration of a j-th one of the second light-emitting periods c2 in an i-th data holding phase T2 is denoted as Bij. Both i and j are integers, 1≤i≤n, and 1≤j≤m.
As shown in
Exemplarily, in the embodiment of the present disclosure, the duration of the first one of the at least one first light-emitting period c1 in the data writing phase T1 is less than a duration of each of at least one second light-emitting period c2 in the data holding phase T2. That is, B01=Bij−kNH, k being an integer greater than or equal to 1, and H being a row scan time of the pixel driver circuit row 40. In this way, the difficulty of timing design for the light emission control signal outputted by the light emission control sub-circuit 30 is reduced, making it simple and easy to operate.
Optionally, the driving method according to embodiments of the present disclosure further includes: the durations are controlled to meet Bi1≤Bi2≤ . . . ≤Bim, i being any integer from 1 to n. That is, the duty cycles of a plurality of high-level pulses of the light emission control signal in the same data holding phase T2 successively decrease. As shown in
Optionally, the driving method according to the embodiments of the present disclosure further includes: the durations are controlled to meet B1j≤B2j≤ . . . ≤Bnj, j being any integer from 1 to m. That is, the duty cycles of the high-level pulses of the light emission control signal transmitted by the light emission control signal terminal E in different data holding phases T2 successively decrease to compensate for the impact of the leakage current on the brightness, so as to further alleviate the flicker problem in the first mode.
Exemplarily, when n≥2, the driving method according to the embodiments of the present disclosure further includes the following step.
The n data holding phases T2 at least include an (i−1)-th data holding phase T2 and an i-th data holding phase T2 that are adjacent. The duration of an m-th one of the second light-emitting periods c2 in the (i−1)-th data holding phase T2 is less than or equal to the duration of the first one of the second light-emitting periods c2 in the i-th data holding phase T2. That is, in the embodiment of the present disclosure, B(i−1)m≤Bi1. B(i−1)m denotes the duration of the m-th second light-emitting period c2 in the (i−1)-th data holding phase T2, and Bi1 denotes the duration of the first-one second light-emitting period c2 in the i-th data holding phase T2. Referring to
Exemplarily, as shown in
Exemplarily, as shown in
The driving method according to the embodiment of the present disclosure further includes the following step.
The adjustment switch 27 is controlled to provide a data signal Vd to the second node N2 in the data writing period b.
The adjustment switch 27 is controlled to provide a bias adjustment signal Vp to the second node N2 in the adjustment period e. The bias adjustment signal Vp can adjust the bias state of the driver transistor M0. The inventor found that in the data writing phase T1 at an initial stage of each working cycle T, due to a hysteresis voltage of the driver transistor M0, the light-emitting element 11 has a light emission delay, resulting in a brightness delay in the first-one first light-emitting period c1. In the embodiments of the present disclosure, the adjustment switch 27 adjusts the bias of the driver transistor M0 to generate a brightness delay when the display enters the second light-emitting period c2. The design can reduce the brightness of the light-emitting element 11 in the data holding phase T2, thereby reducing a brightness difference between the data holding phase T1 and the data writing phase T2, so as to alleviate the flicker problem in the first mode.
Moreover, in the embodiment of the present disclosure, the adjustment switch 27 is turned on in the data writing period b to provide the data signal Vd to the second node N2, and is turned on in the adjustment period e to provide the bias adjustment signal Vp to the second node N2. The design simplifies the structure of the pixel driver circuit 12, and reduces the area occupied by pixel driver circuit 12, thereby improving the resolution of the display panel.
The embodiments of the present disclosure further provide a display apparatus. FIG. 14 is a schematic diagram of a display apparatus according to an embodiment of the present disclosure. As shown in
The above descriptions are merely preferred examples of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310695462.9 | Jun 2023 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20080068312 | Kim | Mar 2008 | A1 |
| 20190340977 | Park | Nov 2019 | A1 |
| 20220036814 | Hwang | Feb 2022 | A1 |
| 20220122522 | Li | Apr 2022 | A1 |
| Number | Date | Country |
|---|---|---|
| 110444160 | Nov 2019 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20230419904 A1 | Dec 2023 | US |
