Patent Application
20250095584
The present disclosure claims priority to Chinese Application No. 202410926051.0 with the application title of “DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND DISPLAY APPARATUS”, filed on Jul. 10, 2024, the content of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technologies, and particularly relates to a display panel, a method for driving the display panel, and a display apparatus.
A display panel includes pixel circuits and light-emitting elements. The pixel circuit is configured to provide a driving current to the light-emitting element, to drive the light-emitting element to emit light. The pixel circuit typically includes a driving transistor and multiple switching transistors. The device performances of the driving transistor greatly affect the performance of the pixel circuit, which in turn affects the light-emitting effect of the light-emitting element. Therefore, optimizing the device performances of the driving transistor has become an urgent technical problem.
In a first aspect, embodiments of the present disclosure provide a display panel. The display panel includes pixel circuits. One of the pixel circuits includes: a driving module, a gate reset module, a threshold compensation module, and a data writing module. The driving module includes a control terminal electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node. The gate reset module includes a control terminal electrically connected to a first scan line, a first terminal electrically connected to a first reset line, and a second terminal electrically connected to the first node. The threshold compensation module includes a control terminal electrically connected to a second scan line, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node. The data writing module includes a control terminal electrically connected to a third scan line, a first terminal electrically connected to a data line, and a second terminal electrically connected to the second node. For the first scan line, the second scan line and the third scan line that are electrically connected to a same pixel circuit, within one frame, the first scan line outputs a first valid level and a second valid level, the second scan line outputs a third valid level and a fourth valid level, the third scan line outputs a fifth valid level, and at least a part of the third valid level is located between the first valid level and the second valid level, at least a part of the second valid level is located between the third valid level and the fourth valid level, and the fifth valid level overlaps the fourth valid level.
In a second aspect, embodiments of the present disclosure provide a method for driving a display panel. The display panel includes pixel circuits. One of the pixel circuits includes: a driving module, a gate reset module, a threshold compensation module, and a data writing module. The driving module includes a control terminal electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node. The gate reset module includes a control terminal electrically connected to a first scan line, a first terminal electrically connected to a first reset line, and a second terminal electrically connected to the first node. The threshold compensation module includes a control terminal electrically connected to a second scan line, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node. The data writing module includes a control terminal electrically connected to a third scan line, a first terminal electrically connected to a data line, and a second terminal electrically connected to the second node. For the first scan line, the second scan line and the third scan line that are electrically connected to a same pixel circuit, within one frame, the first scan line outputs a first valid level and a second valid level, the second scan line outputs a third valid level and a fourth valid level, the third scan line outputs a fifth valid level, and at least a part of the third valid level is located between the first valid level and the second valid level, at least a part of the second valid level is located between the third valid level and the fourth valid level, and the fifth valid level overlaps the fourth valid level. A driving cycle of the pixel circuit comprises a first period, a second period, a third period, and a fourth period. The method includes: during the first period, turning on the gate reset module in response to the first valid level, and writing a first reset voltage provided by the first reset line into the first node; during the second period, turning on the threshold compensation module in response to the third valid level; during the third period, turning on the gate reset module in response to the second valid level, and writing the first reset voltage provided by the first reset line into the first node; and during the fourth period, turning on the data writing module in response to the fifth valid level, turning on the threshold compensation module in response to the fourth valid level, and writing a data voltage on the data line into the first node for threshold compensation.
In a third aspect, embodiments of the present disclosure provide a display apparatus. The display apparatus includes a display panel. The display panel includes pixel circuits. One of the pixel circuits includes: a driving module, a gate reset module, a threshold compensation module, and a data writing module. The driving module includes a control terminal electrically connected to a first node, a first terminal electrically connected to a second node, and a second terminal electrically connected to a third node. The gate reset module includes a control terminal electrically connected to a first scan line, a first terminal electrically connected to a first reset line, and a second terminal electrically connected to the first node. The threshold compensation module includes a control terminal electrically connected to a second scan line, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node. The data writing module includes a control terminal electrically connected to a third scan line, a first terminal electrically connected to a data line, and a second terminal electrically connected to the second node. For the first scan line, the second scan line and the third scan line that are electrically connected to a same pixel circuit, within one frame, the first scan line outputs a first valid level and a second valid level, the second scan line outputs a third valid level and a fourth valid level, the third scan line outputs a fifth valid level, and at least a part of the third valid level is located between the first valid level and the second valid level, at least a part of the second valid level is located between the third valid level and the fourth valid level, and the fifth valid level overlaps the fourth valid level.
In order to more clearly illustrate technical solutions of embodiments of the present disclosure, the accompanying drawings used in the embodiments are briefly described below. The drawings described below are merely a part of the embodiments of the present disclosure. Based on these drawings, those skilled in the art can obtain other drawings.
In order to better understand technical solutions of the present disclosure, the embodiments of the present disclosure are described in details with reference to the drawings.
It should be clear that the described embodiments are merely part of the embodiments of the present disclosure rather than all of the embodiments. All other embodiments obtained by those skilled in the art without paying creative labor shall fall into the protection scope of the present disclosure.
The terms used in the embodiments of the present disclosure are merely for the purpose of describing specific embodiment, rather than limiting the present disclosure. The terms “a”, “an”, “the” and “said” in a singular form in the embodiment of the present disclosure and the attached claims are also intended to include plural forms thereof, unless noted otherwise.
It should be understood that although the terms ‘first’ and ‘second’ can be used in the present disclosure to describe scan lines, these scan lines should not be limited to these terms. These terms are used only to distinguish the scan lines from each other. For example, without departing from the scope of the embodiments of the present disclosure, a first scan line can also be referred to as a second scan line. Similarly, the second scan line can also be referred to as the first scan line.
It should be understood that the term “and/or” used in the context of the present disclosure is to describe a correlation relation of related objects, indicating that there can be three relations, e.g., A and/or B can indicate only A, both A and B, and only B. In addition, the symbol “/” in the context generally indicates that the relation between the objects in front and at the back of “/” is an “or” relationship.
The present disclosure provides a display panel, such as an organic light-emitting diode (OLED) display panel.
As shown in
In some embodiments of the present disclosure, a control terminal of the driving module 2 is electrically connected to a first node N1, a first terminal of the driving module 2 is electrically connected to a second node N2, and a second terminal of the driving module 2 is electrically connected to a third node N3. A control terminal of the gate reset module 3 is electrically connected to a first scan line S1, a first terminal of the gate reset module 3 is electrically connected to a first reset line Ref1, and a second terminal of the gate reset module 3 is electrically connected to the first node N1. A control terminal of the threshold compensation module 4 is electrically connected to a second scan line S2, a first terminal of the threshold compensation module 4 is electrically connected to the third node N3, and a second terminal of the threshold compensation module 4 is electrically connected to the first node N1. A control terminal of the data writing module 5 is electrically connected to a third scan line S3, a first terminal is of the data writing module 5 electrically connected to a data line Data, and a second terminal of the data writing module 5 is electrically connected to the second node N2.
Regarding the first scan line S1, second scan line S2 and third scan line S3 that are electrically connected to the same pixel circuit 1: within one frame, the first scan line S1 outputs a first valid level el1 and a second valid level el2, the second scan line S2 outputs a third valid level el3 and a fourth valid level el4, and the third scan line S3 outputs a fifth valid level el5. At least a part of the third valid level el3 is located between the first valid level el1 and the second valid level el2, at least a part of the second valid level el2 is located between the third valid level el3 and the fourth valid level el4, and the fifth valid level el5 overlaps the fourth valid level el4.
Corresponding to the above structure, a driving cycle of the pixel circuit 1 includes a first period T1, a second period T2, a third period T3 and a fourth period T4.
During the first period T1, the gate reset module 3 is turned on in response to the first valid level el1, the first reset voltage provided by the first reset line Ref1 is written into the first node N1.
During the second period T2, the threshold compensation module 4 is turned on in response to the third valid level el3.
During the third period T3, the gate reset module 3 is turned on again in response to the second valid level el2, the first reset voltage provided by the first reset line Ref1 is written into the first node N1 again.
During the fourth period T4, the data writing module 5 is turned on in response to the fifth valid level el5, and the threshold compensation module 4 is turned on in response to the fourth valid level el4, the data voltage provided by the data line Data is written into the first node N1 and the threshold compensation is performed on the driving module 2.
Within one frame, different sub-pixels can display different grayscale, meaning that different pixel circuits can write different data voltages. Consequently, after one frame ends, there can be inconsistent in the residual potentials at various terminals of the driving module 2 in different pixel circuits 1.
In related art, within one frame, the control terminal of the driving module is reset only once prior to charging. However, the driving modules in different pixel circuits can still exhibit inconsistent transistor device performances due to the different residual potentials at their first and second terminals, thereby affecting subsequent charging.
The technical solutions provided by the embodiments of the present disclosure effectively address the above issue. In the technical solutions provided, a three-terminal reset operation is performed on the driving module 2 in advance before the pixel circuit 1 is charged: during the first period T1, the first scan line S1 provides the first valid level el1, which can control the gate reset module 3 to be turned on and then the first reset voltage is written into the first node N1, enabling the driving module 2 to be turned on. Then, during the second period T2, the second scan line S2 provides the third valid level el3, which can control the threshold compensation module 4 to be turned on and then a conductive signal path between the first node N1, the third node N3 and the second node N2 is formed. For example, this allows the voltage on the first node N1 to be further written into the third node N3 and the second node N2, or the voltage on the second node N2 to be further written into the third node N3 and the first node N1. Illustratively, during this period, the first reset voltage on the first node N1 can be transmitted to the third node N3 via the conductive threshold compensation module 4, and then to the second node N2 via the conductive driving module 2, achieving a three-terminal reset of the driving module 2. In this way, prior to charging, the device performances of the driving module 2 in different pixel circuits 1 can be set to the same initial state, effectively resolving the issue of inconsistent device performances of the driving module 2 caused by different grayscale displayed by different sub-pixels in the previous frame.
Furthermore, in some embodiments of the present disclosure, after the three-terminal reset of the driving module 2 is completed and prior to entering the charging period, the first scan line S1 can provide the second valid level el2 to control the gate reset module 3 to be turned on again, resetting the first node N1 once more. This can compensate for potential changes that can occur at the first node N1 during the second period T2, ensuring that the potential at the first node N1 is consistent in different pixel circuits 1 prior to charging.
In some embodiments of the present disclosure, referring to
For the same pixel circuit 1, at least two of first scan line S1, second scan line S2 and third scan line S3 that correspond to the same pixel circuit 1 are electrically connected to the first shift sub-registers 10. In other words, the scan signals provided by at least two of the first scan line S1, second scan line S2 and third scan line S3 are borrowed from signals of different stages within the same shift register. In this way, at most two shift registers are required to drive these three scan lines, reducing the number of shift registers in the display panel and contributing to a narrow border.
Furthermore, in some embodiments of the present disclosure, all three of the first scan line S1, second scan line S2 and third scan line S3 are electrically connected to the first shift register 9, or only two of them are electrically connected to the first shift register 9.
For the i-th circuit row 11_i, its corresponding first scan line S1, second scan line S2 and third scan line S3 are respectively electrically connected to the m-th first shift sub-register 10_m, the (m+1)-th first shift sub-register 10_m+1 and the (m+3)-th first shift sub-register 10_m+3 within the first shift register 9, where i is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.
In some embodiments of the present disclosure, m=i. That is, the first scan line S1, second scan line S2 and third scan line S3 corresponding to the first circuit row 11_1 are respectively electrically connected to the 1st, 2nd and 4th first shift sub-registers 10; the first scan line S1, second scan line S2 and third scan line S3 corresponding to the second circuit row 11_2 are respectively electrically connected to the 2nd, 3rd and 5th first shift sub-registers 10, and so on in a similar fashion.
According to the operating performances of the shift register, when multiple shift sub-registers within the same shift register sequentially output valid levels, the valid levels output by adjacent two shift sub-registers do not overlap each other. When all three scan lines are electrically connected to the first shift register 9, the first valid level el1, second valid level el2, third valid level el3, fourth valid level el4 and fifth valid level el5 can satisfy the following conditions: the third valid level el3 is located between the first valid level el1 and the second valid level el2. A time interval between the third valid level el3 and the first valid level el1 is equal to a time interval between the third valid level el3 and the second valid level el2. The second valid level el2 is located between the third valid level el3 and the fourth valid level el4. A time interval between the second valid level el2 and the third valid level el3 is equal to a time interval between the second valid level el2 and the fourth valid level el4. The period of the fifth valid level el5 overlaps the period of the fourth valid level el4.
Further, it can be realized that: during the first period T1, the gate reset module 3 is controlled to be turned on, resetting the first node N1; during the second period T2, the threshold compensation module 4 is controlled to be turned on, performing a three-terminal reset of the driving module 2; during the third period T3, the gate reset module 3 is controlled to be turned on again, resetting the first node N1 once more; during the fourth period T4, both the data write module 5 and the threshold compensation module 4 are controlled to be turned on, charging the first node N1 and performing threshold compensation.
Furthermore, when the third scan line S3 is connected to the first shift register 9, subsequent to outputting the fifth valid level el5, the third scan line S3 will further output a sixth valid level el6. In this regard, referring further to
In the above structure, the signals required by the first scan line S1, second scan line S2 and third scan line S3 are provided by the same set of shift registers, significantly reducing the number of shift registers required in the display panel. This technical solution is more suitable for the design of display panels with extremely narrow borders.
For the i-th circuit row 11_i, its corresponding fourth scan line S4 is electrically connected to the (m+2)-th first shift sub-register 10_m+2 in the first shift register 9.
Based on the above structure, referring to
When only two of the first scan line S1, the second scan line S2 and the third scan line S3 are electrically connected to the first shift register 9, referring to
The first scan line S1 is electrically connected to the second shift sub-register 16, while the second scan line S2 and the third scan line S3 are electrically connected to the first shift sub-registers 10, respectively. Alternatively, the first scan line S1 and the second scan line S2 are electrically connected to the first shift sub-registers 10, respectively, while the third scan line S3 is electrically connected to the second shift sub-register 16.
When the signals provided by the first scan line S1, the second scan line S2 and the third scan line S3 originate from two shift registers, the parameters of the valid levels output by these scan lines can be controlled diversely through differential design of the types of these two shift registers, the time point of receiving the frame start signal, the pulse width and frequency of the received clock signal, etc., making the driving of the pixel circuit more flexible.
The display panel further includes multiple circuit rows 11 arranged along the first direction x, where each circuit row 11 includes multiple pixel circuits 1 arranged along the second direction y, and the first direction x intersects with the second direction y.
For the i-th circuit row 11_i, its corresponding first scan line S1 is electrically connected to the n-th second shift sub-register 16_n in the second shift register 15, while its corresponding second scan line S2 and third scan line S3 are electrically connected to the m-th first shift sub-register 10_m and the (m+2)-th first shift sub-register 10_m+2, respectively, in the first shift register 9. Where i, m, and n are integers greater than or equal to 1.
In some embodiments of the present disclosure, m=i and n=i. That is, for the first circuit row 11_1, its corresponding first scan line S1 is electrically connected to the 1st second shift sub-register 16_1, and its corresponding second scan line S2 and third scan line S3 are electrically connected to the 1st first shift sub-register 10_1 and the 3rd first shift sub-register 10_3, respectively; for the second circuit row 11_2, its corresponding first scan line S1 is electrically connected to the 2nd second shift sub-register 16_2, and its corresponding second scan line S2 and third scan line S3 are electrically connected to the 2nd first shift sub-register 10_2 and the 4th first shift sub-register 10_4, respectively; and so on.
Furthermore, referring to
In such configuration, the second scan line S2 and the third scan line S3 are electrically connected to the first shift register 9, while the first scan line S1 is separately connected to the second shift register 15. By adjusting the time point when the first shift register 9 receives the frame start signal, the time point when the second scan line S2 and the third scan line S3 output valid levels can be adjusted, such as shortening or lengthening the interval between the third valid level el3 output by the second scan line S2 and the first valid level el1 output by the first scan line S1, thereby achieving more flexible driving of the timing for various operations performed by the pixel circuit 1.
Moreover, the above configuration further specifies that the second valid level el2 does not overlap the fifth valid level el5. In other words, during the period when the fourth valid level el4 overlaps the fifth valid level el5, the first scan line S1 outputs a non-valid level. This avoids signal disturbance at the first node N1 due to simultaneous activation of the gate reset module 3, the data write module 5 and the threshold compensation module 4, and simultaneous writing the first reset voltage and the data voltage into the first node N1.
Furthermore, referring again to
It should be noted that when t1>t2, under the premise that the second valid level el2 does not overlap the fifth valid level el5, referring to
The display panel further includes multiple circuit rows 11 arranged along the first direction x. Each circuit row 11 includes multiple pixel circuits 1 arranged along the second direction y which intersects with the first direction x.
For the i-th circuit row 11_i, its corresponding first scan line S1 and second scan line S2 are electrically connected to the m-th first shift sub-register 10_m and (m+1)-th first shift sub-register 10_m+1, respectively, in the first shift register 9, while its corresponding third scan line S3 is electrically connected to the n1-th second shift sub-register 16_n1 in the second shift register 15, where i, m and n1 are integers greater than or equal to 1.
The potential of the valid level output by the second shift sub-register 16 being opposite to that of the valid level output by the first shift sub-register 10 implies that the transistor type of the data write transistor M3 in the data write module 5 is opposite to the gate reset transistor M1 in the gate reset module 3 and the threshold compensation transistor M2 in the threshold compensation module 4. In embodiments of the present disclosure, the data write transistor M3 can be designed as a p-type low temperature poly-silicon (LTPS) transistor, while the gate reset transistor M1 and the threshold compensation transistor M2 can be designed as a n-type indium gallium zinc oxide (IGZO) transistors with lower leakage current. In this case, the valid level output by the second shift sub-register 16 is a low level, while the valid level output by the first shift sub-register 10 is a high level.
In such configuration, the transistors in the pixel circuit 1 do not necessarily have to be of the same type. For example, some IGZO transistors can be employed to reduce the leakage current of the driving transistor M0. Furthermore, with this structure, the third scan line S3 is solely driven by the second shift register 15, allowing for differential design in the number of valid levels output by the third scan line S3 compared to those of the first scan line S1 and the second scan line S2 within a frame. For instance, only one valid level (the fifth valid level el5) can be controlled to be output by the third scan line S3 within a frame.
For the i-th circuit row 11_i, its corresponding fifth scan line S5 is electrically connected to the n2-th second shift sub-register 16_n2 in the second shift register 15, n2 is an integer greater than or equal to 1, and n2/n1.
Based on the above structure, prior to or subsequent to charging, the bias adjustment module 17 is turned on to write the bias voltage on the bias signal line DVH into the second node N2, refreshing the potential of the second node N2 and adjusting the bias state of the driving transistor M0. This prevents the performances of the driving transistor M0 from drifting and improves hysteresis effect of the driving transistor M0. Moreover, since the fifth scan line S5 and the third scan line S3 are connected to the same shift register, there is no need to dispose an additional shift register for the fifth scan line S5.
Regarding n2, in some embodiments of the present disclosure, referring again to
This structure adjusts the bias state of the driving transistor M0 by the bias drive module 2 subsequent to charging is completed, ensuring that the driving transistor M0 maintains optimal performances during the period from charging to light-emitting.
Furthermore, when n2=n1+1, referring again to
When the fifth scan line S5 outputs a valid level later than the third scan line S3, by having a smaller time interval between the valid levels output sequentially by the second shift register 15, the overall duration required for the first scan line S1, second scan line S2, third scan line S3 and fifth scan line S5 to output valid levels within a frame can be reduced, reducing the non-glowing time.
Typically, the bias voltage is much greater than the reset voltage. In some embodiments of the present disclosure, the bias adjustment module 17 is turned on during the second period T2 during which both the threshold compensation module 4 and the bias adjustment module 17 are turned on. Since the bias voltage is continuously written into the second node N2, the bias voltage of the second node N2 is further written into the third node N3 and the first node N1, allowing for a three-terminal reset of the driving module 2 using only the bias voltage, which avoids excessive potential differences across the two terminals of the driving module 2.
In some embodiments of the present disclosure, as shown in
Currently, shift registers that output high valid levels and those that output low valid levels are of different types. Typically, the pulse width of the valid level output by shift registers that output high valid levels is larger. Therefore, in some embodiments of the present disclosure, differentiated design of the pulse widths of the valid levels output by the first shift register 9 and the second shift register 15 enables the first shift sub-register 10 to output the higher valid level with the larger pulse width. From another perspective, the larger the pulse width of the valid level output by the first shift sub-register 10, the longer the three-terminal reset time of the driving module 2, resulting in better reset effects.
The first mode can be a low-frequency mode. Since the frame in the low-frequency mode is longer, the shift of the driving transistor M0 is more pronounced. Therefore, by enabling the second shift sub-register 16 to output a valid level in at least one holding frame F2, the bias state of the driving transistor M0 can be adjusted during the holding frame F2, improving device performance.
The display panel further includes a third shift register 19 which includes multiple third shift sub-registers 20 in cascade. Within one frame, the third shift sub-register 20 output at least one valid level.
The fifth scan line S5 is electrically connected to the third shift sub-register 20, and the valid levels output by the second shift sub-register 16 and the third shift sub-register 20 connected to the same pixel circuit 1 do not overlap.
In some embodiments of the present disclosure, referring to
In this structure, the data write module 5 and the bias adjustment module 17 in the pixel circuit 1 are driven by two different shift registers, allowing separate control over the activation times and frequencies of the data write module 5 and the bias adjustment module 17. For example, as shown in
In some embodiments of the present disclosure, combining with
When the (m+1)-th first shift sub-register 10 outputs a valid level, the anode reset module 12 is turned on, using the second reset voltage to reset the anode of the light-emitting element 14.
When the (n+1)-th second shift sub-register 16_n+1 outputs a valid level, the anode reset module 12 is turned on, the anode of the light-emitting element 14 is reset using the second reset voltage.
In the above structure, the fourth scan line S4 can share a shift register with other scan lines, so that an additional shift register is not required to dispose for the fourth scan line S4, thereby simplifying the structural design.
With such configuration, the bias adjustment module 17 and the gate reset module 3 share the scan line. During the first period T1 and the third period T3, the bias adjustment module 17 is turned on, the bias voltage is written into the second node N2.
It should be noted that during the first period T1, after the bias voltage is written into the second node N2, since the driving module 2 is turned on, the bias voltage of the second node N2 will further be written into the third node N3 through the driving module 2. During the second period T2, although the threshold compensation module 4 is turned on, since there is no continuous external signal being written into the first node N1 and the third node N3 during this period, the first node N1 maintains the first reset voltage written during the first period T1, and the second node N2 and the third node N3 maintain the bias voltage written during the first period T1, a three-terminal reset of the driving module 2 is performed using the first reset voltage and the bias voltage.
In some embodiments of the present disclosure, referring again to
A circuit structure of pixel circuit 1 is described below in detail.
The pixel circuit 1 includes a driving module 2, a gate reset module 3, a threshold compensation module 4, a data write module 5, an anode reset module 12, a first light-emitting control module 21, a second light-emitting control module 22, a bias adjustment module 17, and a storage capacitor Cst.
The driving module 2 includes a driving transistor M0. A gate of the driving transistor M0 is electrically connected to the first node N1, a first terminal of the driving transistor M0 is electrically connected to the second node N2, and a second terminal of the driving transistor M0 is electrically connected to the third node N3.
The gate reset module 3 includes a gate reset transistor M1. A gate of the gate reset
transistor M1 is electrically connected to the first scan line S1, a first terminal of the gate reset transistor M1 is electrically connected to the first reset line Ref1, and a second terminal of the gate reset transistor M1 is electrically connected to the first node N1.
The threshold compensation module 4 includes a threshold compensation transistor M2. A gate of the threshold compensation transistor M2 is electrically connected to the second scan line S2, a first terminal of the threshold compensation transistor M2 is electrically connected to the third node N3, and a second terminal of the threshold compensation transistor M2 is electrically connected to the first node N1.
The data write module 5 includes a data write transistor M3. A gate of the data write transistor M3 is electrically connected to the third scan line S3, a first terminal of the data write transistor M3 is electrically connected to the data line Data, and a second terminal of the data write transistor M3 is electrically connected to the second node N2.
The anode reset module 12 includes an anode reset transistor M4. A gate of the anode reset transistor M4 is electrically connected to one of the first scan line S1, the second scan line S2, the third scan line S3 and the fourth scan line S4, a first terminal of the anode reset transistor M4 is electrically connected to the second reset line Ref2, and a second terminal of the anode reset transistor M4 is electrically connected to the light-emitting element 14.
The first light-emitting control module 21 includes a first light-emitting control transistor M5. A gate of the first light-emitting control transistor M5 is electrically connected to the light-emitting control signal line Emit, the first terminal of the first light-emitting control transistor M5 is electrically connected to the first power supply line PVDD, and the second terminal of the first light-emitting control transistor M5 is electrically connected to the second node N2.
The second light-emitting control module 22 includes a second light-emitting control transistor M6. A gate of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal line Emit, the first terminal of the second light-emitting control transistor M6 is electrically connected to the third node N3, and the second terminal of the second light-emitting control transistor M6 is electrically connected to the light-emitting element 14.
The bias adjustment module 17 includes a bias adjustment transistor M7. The gate of the bias adjustment transistor M7 is electrically connected to the fifth scan line S5 or the first scan line S1, the first terminal of the bias adjustment transistor M7 is electrically connected to the bias signal line DVH, and the second terminal of the bias adjustment transistor M7 is electrically connected to the second node N2.
A first plate of the storage capacitor Cst is electrically connected to the first power supply line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the first node N1.
A driving cycle of pixel circuit 1 further includes a seventh period T7, during which the light-emitting control signal line Emit provides a valid level, the first light-emitting control module 21 and the second light-emitting control module 22 are turned on, and the driving current converted by the driving module 2 flows into the light-emitting element 14, driving it to emit light.
Based on a same inventive concept, the embodiments of the present disclosure further provide a method for driving a display panel, which is applied to the above-mentioned display panel.
As shown in
The control terminal of the driving module 2 is electrically connected to the first node N1, the first terminal of the driving module 2 is electrically connected to the second node N2, and the second terminal of the driving module 2 is electrically connected to the third node N3. The control terminal of the gate reset module 3 is electrically connected to the first scan line S1, the first terminal of the gate reset module 3 is electrically connected to the first reset line Ref1, and the second terminal of the gate reset module 3 is electrically connected to the first node N1. The control terminal of the threshold compensation module 4 is electrically connected to the second scan line S2, the first terminal of the threshold compensation module 4 is electrically connected to the third node N3, and the second terminal of the threshold compensation module 4 is electrically connected to the first node N1. The control terminal of the data write module 5 is electrically connected to the third scan line S3, the first terminal of the data write module 5 is electrically connected to the data line Data, and the second terminal of the data write module 5 is electrically connected to the second node N2.
For the first scan line S1, second scan line S2, and third scan line S3 that are electrically connected to the same pixel circuit 1, within one frame, the first scan line S1 outputs a first valid level el1 and a second valid level el2, the second scan line S2 outputs a third valid level el3 and a fourth valid level el4, and the third scan line S3 outputs a fifth valid level el5. Additionally, at least a part of the third valid level el3 is located between the first valid level el1 and the second valid level el2, at least a part of the second valid level el2 is located between the third valid level el3 and the fourth valid level el4, and the fifth valid level el5 overlaps the fourth valid level el4.
The driving cycle of the pixel circuit 1 includes a first period T1, a second period T2, a third period T3 and a fourth period T4.
The driving method includes following steps.
In the first period T1, turning on the gate reset module 3 in response to the first valid level el1, and writing a first reset voltage provided by the first reset line Ref1 into the first node N1.
In the second period T2, turning on the threshold compensation module 4 in response to the third valid level el3.
In the third period T3, turning on the gate reset module 3 in response to the second valid level el2 again, and writing the first reset voltage provided by the first reset line Ref1 into the first node N1 once more.
In the fourth period T4, turning on the data write module 5 in response to the fifth valid level el5, turning on the threshold compensation module 4 in response to the fourth valid level el4 simultaneously, and writing the data voltage on the data line Data into the first node N1 for threshold compensation.
Based on the aforementioned analysis, by adopting this driving method, prior to charging, the driving module 2 in the pixel circuit 1 undergoes a three-terminal reset operation in advance. This ensures that the device performances of the driving module 2 in different pixel circuits 1 are reset to the same initial state, effectively addressing the issue of inconsistent device performances of the driving module 2 caused by different sub-pixels displaying different grayscale in the previous frame.
In some embodiments of the present disclosure, as shown in
In some embodiments of the present disclosure, as shown in
During the first period T1, both the gate reset module 3 and the bias adjustment module 17 respond to the first valid level el1 to be turned on, and the bias voltage on the bias signal line DVH is written into the second node N2 and then into the third node N3 through the driving module 2. During the second period T2, the threshold compensation module 4 is turned on in response to the third valid level el3, while the first node N1 maintains the first reset voltage and the third node N3 maintains the bias voltage, thereby performing a three-terminal reset of the driving module 2 using both the first reset voltage and the bias voltage.
Furthermore, in some embodiments of the present disclosure, as shown in
The driving cycle of the pixel circuit 1 further includes a fifth period T5 and a sixth period T6. For the pixel circuit 1 in the i-th circuit row 11, the driving method further includes: during the sixth period T6, turning on the data write module 5 in response to the sixth valid level el6 and writing the voltage on the data line Data into the second node N2, thereby refreshing the potential of the second node N2 again subsequent to charging, the bias state of the driving transistor M0 is adjusted, preventing the performances of the driving transistor M0 from drifting, which improves the hysteresis effect of the driving transistor M0, ultimately contributing to optimizing the display effect, such as improving the residual image.
In some embodiments of the present disclosure, referring again to
The display panel further includes a first shift register 9 and a second shift register 15. The first shift register 9 includes multiple first shift sub-registers 10 arranged in cascade, and the second shift register 15 includes multiple second shift sub-registers 16 arranged in cascade. During one frame, each first shift sub-register 10 outputs at least two valid levels, while each second shift sub-register 16 outputs at least one valid level. In addition, the potential of the valid level output by the first shift sub-registers 10 is opposite to that of the valid level output by the second shift sub-registers 16.
For the i-th circuit row 11_i, its corresponding first scan line S1 and second scan line S2 are respectively connected to the m-th first shift sub-register 10_m and the (m+1)-th first shift sub-register 10_m+1 in the first shift register 9, while its corresponding third scan line S3 is connected to the n1-th second shift sub-register 16_n1 in the second shift register 15. Where i, m and n1 are integers greater than or equal to 1.
The display panel further includes a bias adjustment module 17. A control terminal of the bias adjustment module 17 is electrically connected to a fifth scan line S5, a first terminal of the bias adjustment module 17 is electrically connected to a bias signal line DVH, and a second terminal of the bias adjustment module 17 is electrically connected to the second node N2.
For the i-th circuit row 11_i, its corresponding fifth scan line S5 is electrically connected to the n2-th second shift sub-register 16 in the second shift register 15, where n2 is an integer greater than or equal to 1, and n2+n1.
For the i-th circuit row 11_i, either prior to or subsequent to the fourth period T4, the driving method further includes: turning on the bias adjustment module 17 in response to the valid level output by the n2-th second shift sub-register 16, and writing the bias voltage on the bias signal line DVH into the second node N2. This refreshes the potential of the second node N2, adjusts the bias state of the driving transistor M0, which prevents the performances of the driving transistor M0 from drifting, and improves the hysteresis effect of the driving transistor M0, ultimately contributing to optimizing the display effect, such as improving the residual image.
Furthermore, referring to
For the i-th circuit row 11_i, during the second period T2, after the voltage on the bias signal line DVH is written into the second node N2, then written into the third node N3 through the conductive driving module 2, and further into the first node N1 through the conductive threshold compensation module 4.
Typically, the bias voltage is much greater than the reset voltage. In some embodiments of the present disclosure, the bias adjustment module 17 is turned on during the second period T2. During this period, both the threshold compensation module 4 and the bias adjustment module 17 are turned on. Since the bias voltage is continuously written into the second node N2, it is further written into the third node N3 and the first node N1, allowing for a three-terminal reset of the driving module 2 solely using the bias voltage, thereby avoiding excessive potential differences across the two terminals of the driving module 2.
Based on a same inventive concept, embodiments of the present disclosure further provide a display apparatus, as shown in
The above are merely exemplary embodiments of the present disclosure, which, as mentioned above, are not used to limit the present disclosure. Whatever within the principles of the present disclosure, including any modification, equivalent substitution, improvement, etc., shall fall into the protection scope of the present disclosure.
Finally, it should be noted that the technical solutions of the present disclosure are illustrated by the above embodiments, but not intended to limit thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art can understand that the present disclosure is not limited to the specific embodiments described herein, and can make various modifications, readjustments, and substitutions without departing from the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202410926051.0 | Jul 2024 | CN | national |
