CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 112109993, filed on Mar. 17, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND
Technical Field
The disclosure relates to a photoelectric device and a manufacturing method thereof; more particularly, the disclosure relates to a display panel, a tiled display device including the display panel, and a manufacturing method of the display panel.
Description of Related Art
Micro light-emitting diode (micro-LED) display devices possess advantages including power conservation, high efficiency, elevated brightness, and rapid response time. Given the small dimensions of the micro-LEDs, the prevailing methodology for manufacturing the micro-LED display devices involves the utilization of a mass transfer technology; that is, a micro-electromechanical array technology is applied to pick up and place micro-LED chips, facilitating the simultaneous transfer of a substantial quantity of the micro-LED chips onto a circuit substrate.
Nevertheless, owing to the ongoing necessity for enhancing the yield of the mass transfer technology, the prevailing approach involves the initial fabrication of small display panels and subsequent action of tiling the panels to form a large display device. To achieve a seamless tiling configuration, the entire display surface of the individual panels is considered an effective region, which leads to a stringent requirement for high thickness uniformity in an encapsulation layer of the display panel and thus poses a significant challenge to the encapsulation process. Moreover, the encapsulation structure has a multi-layer design, and after undergoing high temperature and high humidity reliability tests, peeling often occurs between layers and may even adversely impact circuit connections, thereby compromising overall reliability.
SUMMARY
The disclosure provides a display panel with an improved reliability.
The disclosure provides a tiled display device with an improved reliability.
The disclosure provides a manufacturing method of a display panel that can improve thickness uniformity of an encapsulation layer in the display panel.
An embodiment of the disclosure provides a display panel, and the display panel has a display region and a lead out wiring region adjacent to the display region and includes a circuit substrate, a plurality of light-emitting elements, an encapsulation layer, and a sealing layer. The circuit substrate has a top surface, a bottom surface opposite to the top surface, and a first side surface connecting the top surface and the bottom surface, where the first side surface extends from the display region to the lead out wiring region. The light-emitting elements are disposed at the display region and located on the circuit substrate. The encapsulation layer is disposed at the display region and located between the circuit substrate and the light-emitting elements, where a first terminal surface of the encapsulation layer is aligned with a first side surface of the circuit substrate. The sealing layer covers the first side surface of the circuit substrate and the first terminal surface of the encapsulation layer.
In an embodiment of the disclosure, a height of the encapsulation layer is less than or equal to a height of the light-emitting elements.
In an embodiment of the disclosure, a thickness of the encapsulation layer is 5 μm to 10 μm, an optical density (OD) value of the encapsulation layer is greater than or equal to 3, and an OD value of the sealing layer is greater than or equal to 2.
In an embodiment of the disclosure, a height of the encapsulation layer is greater than a height of the light-emitting elements.
In an embodiment of the disclosure, a transmittance of the encapsulation layer is greater than or equal to 80%, and a transmittance of the sealing layer is greater than or equal to 80%.
In an embodiment of the disclosure, the sealing layer extends from one portion of the first side surface of the circuit substrate located in the display region to the other portion of the first side surface of the circuit substrate located in the lead out wiring region.
In an embodiment of the disclosure, the display panel further includes a chip bonding film disposed at the lead out wiring region and electrically connected to the circuit substrate.
In an embodiment of the disclosure, the display panel further includes a protection adhesive located at the lead out wiring region and covering the chip bonding film.
In an embodiment of the disclosure, a material of the protection adhesive is different from a material of the encapsulation layer.
In an embodiment of the disclosure, the protection adhesive covers a second side surface of the circuit substrate located in the lead out wiring region, and the second side surface adjoins the first side surface of the circuit substrate.
In an embodiment of the disclosure, a second terminal surface of the encapsulation layer is located between the light-emitting elements and the second side surface.
In an embodiment of the disclosure, the chip bonding film is located between the second terminal surface and the second side surface.
In an embodiment of the disclosure, the display panel further includes an optical layer disposed at the display region and located on the light-emitting elements and the encapsulation layer.
In an embodiment of the disclosure, a first edge surface of the optical layer extends beyond the first terminal surface of the encapsulation layer, and the sealing layer physically contacts the encapsulation layer and the optical layer.
In an embodiment of the disclosure, a cutting mark on the first edge surface of the optical layer continuously extends to a cutting surface of the sealing layer.
In an embodiment of the disclosure, a top surface of the encapsulation layer is aligned with a top surface of the sealing layer.
In an embodiment of the disclosure, a first edge surface of the optical layer is aligned with the first terminal surface of the encapsulation layer, and the sealing layer further covers the first edge surface of the optical layer.
Another embodiment of the disclosure provides a tiled display device that includes two of the above-mentioned display panels.
In an embodiment of the disclosure, the first side surfaces of the circuit substrates of the two display panels are opposite to each other.
In an embodiment of the disclosure, the sealing layers are located between the two display panels.
Another embodiment of the disclosure provides a manufacturing method of a display panel, and the method includes following steps. A circuit substrate is provided. A plurality of light-emitting elements are disposed on the circuit substrate. An encapsulation layer is formed on the circuit substrate and the light-emitting elements. The circuit substrate and the encapsulation layer are cut to expose a first side surface of the circuit substrate and a first terminal surface of the encapsulation layer. A sealing layer is formed on the first side surface of the circuit substrate and the first terminal surface of the encapsulation layer.
In an embodiment of the disclosure, the manufacturing method further includes performing a planarization process on the encapsulation layer after forming the encapsulation layer on the circuit substrate and the light-emitting elements.
In an embodiment of the disclosure, the manufacturing method further includes forming an optical layer on the encapsulation layer and the light-emitting elements after cutting the circuit substrate and the encapsulation layer.
In an embodiment of the disclosure, the sealing layer is further formed on a bottom surface of the optical layer.
In an embodiment of the disclosure, the manufacturing method further includes cutting the optical layer and the sealing layer after forming the sealing layer, so as to expose a first edge surface of the optical layer and a cutting surface of the sealing layer.
In an embodiment of the disclosure, a cutting mark on the first edge surface of the optical layer continuously extends to the cutting surface of the sealing layer.
In an embodiment of the disclosure, the manufacturing method further includes forming an optical layer on the encapsulation layer and the light-emitting elements before cutting the circuit substrate and the encapsulation layer, and the step of cutting the circuit substrate and the encapsulation layer further includes cutting the optical layer, so as to expose a first edge surface of the optical layer.
In an embodiment of the disclosure, the sealing layer is further formed on the first edge surface of the optical layer.
Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1A to FIG. 1Ia are schematic cross-sectional diagrams illustrating steps of a manufacturing method of a display panel 10 according to an embodiment of the disclosure.
FIG. 1Ib is a schematic cross-sectional diagram taken along a sectional line A-A′ in FIG. 1Ia.
FIG. 1Ic is a schematic cross-sectional diagram taken along a sectional line B-B′ in FIG. 1Ia.
FIG. 2 is a schematic cross-sectional diagram illustrating a display panel 20 according to an embodiment of the disclosure.
FIG. 3A to FIG. 3Da are schematic cross-sectional diagrams illustrating steps of a manufacturing method of a display panel 30 according to an embodiment of the disclosure.
FIG. 3Db is a schematic cross-sectional diagram taken along a sectional line C-C′ in FIG. 3Da.
FIG. 4 is a schematic cross-sectional diagram illustrating a display panel 40 according to an embodiment of the disclosure.
FIG. 5A is a schematic three-dimensional diagram illustrating a tiled display device 100 according to an embodiment of the disclosure.
FIG. 5B is a schematic cross-sectional diagram taken along a sectional line D-D′ in FIG. 5A.
FIG. 5C is a schematic cross-sectional diagram taken along a sectional line E-E′ in FIG. 5A.
FIG. 6 is a schematic three-dimensional diagram illustrating a tiled display device 200 according to an embodiment of the disclosure.
DESCRIPTION OF THE EMBODIMENTS
In the accompanying drawings, the thickness of layers, films, panels, regions, and so forth are enlarged for clarity. The same reference numbers refer to the same elements throughout the specification. It should be understood that when an element, such as a layer, a film, a region, or a substrate is referred to as being “on” or “connected to” another element, it can be directly on or connected to the another element, or an intermediate element may also be present. By contrast, when an element is referred to as being “directly on” or “directly connected to” another element, no intermediate element is present. As used herein, being “connected” may refer to a physical and/or electrical connection. Furthermore, being “electrically connected” or “coupled” may refer to the presence of other elements between the two elements.
It should be understood that, although the terminologies “first,” “second,” “third,” and so forth may serve to describe various elements, components, regions, layers, and/or sections in this disclosure, these elements, components, regions, layers, and/or sections shall not be limited by these terminologies. These terminologies merely serve to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, or section. Thus, a first “element,” “component,” “region,” “layer,” or “section” discussed below may be called as a second element, component, region, layer, or section without departing from the teachings herein.
The terminologies used herein are only for the purpose of describing particular embodiments and are not restrictive. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms including “at least one” or represent “and/or” unless the content clearly indicates otherwise. As used herein, the terminology “and/or” includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this disclosure, the terminologies “include” and/or “comprise” indicate the presence of the described features, regions, overall scenarios, steps, operations, elements, and/or components but do not exclude the presence or addition of one or more other features, regions, overall scenarios, steps, operations, elements, components, and/or combinations thereof.
Furthermore, relative terminologies, such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another element, as shown in the drawings. It should be understood that relative terminologies are intended to encompass different orientations of the device in addition to the orientation shown in the drawings. For instance, if a device in one of the accompanying drawings is turned upside down, elements described as being on the “lower” side of other elements would then be oriented on the “upper” sides of the other elements. Thus, the exemplary terminology “lower” may include an orientation of being on the “lower” side and the “upper” side, depending on the particular orientation of the accompanying drawings. Similarly, if the device in one of the accompanying drawings is turned upside down, elements described as being “below” or “beneath” other elements would then be oriented “above” the other elements. Thus, the exemplary terminology “below” or “beneath” may encompass an orientation of being above and below.
Exemplary embodiments are described herein with reference to the cross-sectional schematic views illustrating idealized embodiments. Therefore, variations of shapes resulting from the manufacturing technologies and/or tolerances, for instance, are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result from manufacturing, for instance. For instance, regions shown or described as being flat may typically have rough and/or non-linear features. Besides, the acute angle as shown may be round. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the exact shape of the regions, and are not intended to limit the scope of the claims.
FIG. 1A to FIG. 1Ia are schematic cross-sectional diagrams illustrating steps of a manufacturing method of a display panel 10 according to an embodiment of the disclosure. With reference to FIG. 1A, a circuit substrate 110 is provided. In some embodiments, the circuit substrate 110 includes elements or circuits required by the display panel 10, such as a driving element, a switch element, a storage capacitor, a power line, a driving signal line, a timing signal line, a current compensation line, a detection signal line, and so on. In some embodiments, the circuit substrate 110 includes a switch element array. In some embodiments, the circuit substrate 110 includes a plurality of pads PD for electrically connecting the circuit substrate 110 to the outside. In some embodiments, the pads PD are disposed on a top surface 110T of the circuit substrate 110.
With reference to FIG. 1B, a plurality of light-emitting elements 120 are disposed on the circuit substrate 110. In some embodiments, the light-emitting elements 120 formed on a growth substrate (e.g., a sapphire substrate) may be transferred to a temporary carrier (not shown) through a mass transfer process, and the light-emitting elements 120 may be fixed onto the temporary carrier by, for instance, an adhesive material. Subsequently, pick-up bonding, direct bonding, or another method may be performed to move the light-emitting elements 120 on the temporary carrier to the circuit substrate 110. The light-emitting elements 120 may be electrically connected to the circuit substrate 110. In some embodiments, the light-emitting elements 120 may be electrically connected to the circuit substrate 110 through the pads PD on the circuit substrate 110. In some embodiments, the circuit substrate 110 has a display region AA, a peripheral region NA, and a lead out wiring region LA, and the light-emitting elements 120 are exclusively disposed at the display region AA and are not disposed at the peripheral region NA nor at the lead out wiring region LA. In some embodiments, the pads PD are located in the display region AA and the lead out wiring region LA. In some embodiments, the peripheral region NA and the lead out wiring region LA surround the display region AA. In some embodiments, the peripheral region NA adjoins a first side S1, a third side S3, and a fourth side S4 of the circuit substrate 110, and the lead out wiring region LA adjoins a second side S2 of the circuit substrate 110.
With reference to FIG. 1C, an initial encapsulation layer 130′ is formed on the circuit substrate 110 and the light-emitting elements 120. The initial encapsulation layer 130′ may completely cover the light-emitting elements 120. In some embodiments, the initial encapsulation layer 130′ completely covers the display region AA of the circuit substrate 110, and the initial encapsulation layer 130′ further covers a portion of the peripheral area NA adjacent to the display region AA. As such, an edge portion EP of the initial encapsulation layer 130′, which has a relatively thin thickness due to an impact of a flow, may be located in the peripheral area NA, so that a main body portion CP of the initial encapsulation layer 130′ located in the display region AA may have an improved thickness uniformity. In some embodiments, the initial encapsulation layer 130′ does not extend to the lead out wiring region LA. In some embodiments, the initial encapsulation layer 130′ further extends to a portion of the lead out wiring region LA adjacent to the display region AA. In some embodiments, a material of the initial encapsulation layer 130′ may include an organic material, such as epoxy resin, which should however not be construed as a limitation in the disclosure.
With reference to FIG. 1D, a planarization process is performed on the initial encapsulation layer 130′ to expose the light-emitting elements 120 and form an encapsulation layer 130. In some embodiments, the initial encapsulation layer 130′ may be planarized by plasma etching. In some embodiments, the encapsulation layer 130 includes an anti-reflection material, and a height of the encapsulation layer 130 is less than or equal to a height of the light-emitting elements 120, so as to expose light-emitting surfaces of the light-emitting elements 120. In some embodiments, the encapsulation layer 130 includes a transparent encapsulation material, and the height of the encapsulation layer 130 is greater than the height of the light-emitting elements 120, so that the encapsulation layer 130 completely covers the light-emitting elements 120.
With reference to FIG. 1E, the circuit substrate 110 and the encapsulation layer 130 may be cut to remove the peripheral area NA of the circuit substrate 110 and a portion of the encapsulation layer 130 located on the peripheral area NA. After the cutting process is performed, a cutting surface of the circuit substrate 110 and a cutting surface of the encapsulation layer 130 may be exposed. For instance, the cutting surface of the circuit substrate 110 includes a first side surface 111, a third side surface 113, and a fourth side surface 114, where the first side surface 111 and the third side surface 113 extend from the display region AA to the lead out wiring region LA, and the fourth side surface 114 is located in the display region AA. The cutting surface of the encapsulation layer 130 may include a first terminal surface 131, a third terminal surface 133, and a fourth terminal surface 134, where the first terminal surface 131 and the third terminal surface 133 extend from the display region AA to the lead out wiring region LA, and the fourth terminal surface 134 is located in the display region AA. In addition, the second side surface 112 of the circuit substrate 110 disposed at the second side S2 is located in the lead out wiring region LA, and the second side surface 112 connects the first side surface 111 and the third side surface 113 of the circuit substrate 110. In some embodiments, a cutting wheel or an infrared (IR) laser may be applied to cut the circuit substrate 110. In some embodiments, an ultraviolet (UV) laser or an IR laser may be applied to cut the encapsulation layer 130.
With reference to FIG. 1F, an optical layer 140 is formed on the encapsulation layer 130 and the light-emitting elements 120. In some embodiments, the optical layer 140 extends beyond the cutting surface of the circuit substrate 110 and the cutting surface of the encapsulation layer 130. For instance, the optical layer 140 extends beyond the first side surface 111, the third side surface 113, and the fourth side surface 114 of the circuit substrate 110 and the first terminal surface 131, the third terminal surface 133, and the fourth terminal surface 134 of the encapsulation layer 130, but the optical layer 140 does not extend beyond the second side surface 112 of the circuit substrate 110. In some embodiments, a portion of the optical layer 140 overlaps the lead out wiring region LA of the circuit substrate 110. In some embodiments, the optical layer 140 does not overlap the lead out wiring region LA of the circuit substrate 110.
With reference to FIG. 1G, a sealing layer 150 is formed on the cutting surface of the circuit substrate 110 and the cutting surface of the encapsulation layer 130. For instance, the sealing layer 150 is formed on the first side surface 111, the third side surface 113, and the fourth side surface 114 of the circuit substrate 110 and on the first terminal surface 131, the third terminal surface 133, and the fourth terminal surface 134 of the encapsulation layer 130. In some embodiments, the sealing layer 150 is further formed on a bottom surface of the optical layer 140 facing the encapsulation layer 130. In some embodiments, the sealing layer 150 may be formed by spraying or coating.
With reference to FIG. 1H, the optical layer 140 and the sealing layer 150 are cut to expose the first edge surface 141, the third edge surface 143, and the fourth edge surface 144 of the optical layer 140 and expose cutting surfaces 151, 153, and 154 of the sealing layer 150. In some embodiments, the optical layer 140 and the sealing layer 150 may be cut in one single cutting step, so that cutting marks formed by the cutting step extend continuously from the first edge surface 141 of the optical layer 140 to the cutting surface 151 of the sealing layer 150, from the third edge surface 143 of the optical layer 140 to the cutting surface 153 of the sealing layer 150, and from the fourth edge surface 144 of the optical layer 140 to the cutting surface 154 of the sealing layer 150. In some embodiments, the UV laser may be applied to cut the optical layer 140 and the sealing layer 150. Next, with reference to FIG. 1Ia, a chip bonding film CF is disposed at the lead out wiring region LA. In some embodiments, the chip bonding film CF is electrically connected to the pads PD.
FIG. 1Ia is a schematic three-dimensional diagram illustrating the display panel 10 according to an embodiment of the disclosure. FIG. 1Ib is a schematic cross-sectional diagram taken along a sectional line A-A′ in FIG. 1Ia. FIG. 1Ic is a schematic cross-sectional diagram taken along a sectional line B-B′ in FIG. 1Ia.
With reference to FIG. 1Ia to FIG. 1Ic, the display panel 10 may have the display region AA and the lead out wiring region LA adjacent to each other and includes the circuit substrate 110, the light-emitting elements 120, the encapsulation layer 130, and the sealing layer 150. The light-emitting elements 120 may be disposed on the circuit substrate 110, and the light-emitting elements 120 are disposed at the display region AA. In some embodiments, the circuit substrate 110 has the top surface 110T, a bottom surface 110B opposite thereto, and the adjacent first side surface 111 and second side surface 112, the first side surface 111 connects the top surface 110T and the bottom surface 110B, and the second side surface 112 also connects the top surface 110T and the bottom surface 110B. The light-emitting elements 120 may be disposed at the top surface 110T of the circuit substrate 110.
In some embodiments, the encapsulation layer 130 is disposed at the display region AA, and the encapsulation layer 130 is located on the top surface 110T of the circuit substrate 110 and between the light-emitting elements 120. In some embodiments, the encapsulation layer 130 is exclusively disposed at the display region AA. In some embodiments, the encapsulation layer 130 further extends to the lead out wiring region LA. In some embodiments, the first terminal surface 131 of the encapsulation layer 130 is substantially aligned with the first side surface 111 of the circuit substrate 110.
In some embodiments, the display panel 10 is an opaque display panel, and the encapsulation layer 130 includes an anti-reflection material, such as a black light-absorbing material. In some embodiments, a horizontal height of a top surface 130T of the encapsulation layer 130 is less than or equal to a horizontal height of a surface 120T of the light-emitting elements 120. In other words, the encapsulation layer 130 at least exposes the light-emitting surfaces of the light-emitting elements 120. In some embodiments, when a thickness T3 of the encapsulation layer 130 is approximately 5 μm to 10 μm, an optical density (OD) value or a light blocking value of the encapsulation layer 130 is greater than or equal to 3.
In some embodiments, the sealing layer 150 covers the first side surface 111 of the circuit substrate 110 and the first terminal surface 131 of the encapsulation layer 130. In some embodiments, the sealing layer 150 continuously extends from the first side surface 111 of the circuit substrate 110 to the first terminal surface 131 of the encapsulation layer 130. As such, the sealing layer 150 may seal an interface IF between the encapsulation layer 130 and the circuit substrate 110, thereby preventing the interface IF from peeling off due to a high temperature and high humidity environment and improving the reliability of the display panel 10. In some embodiments, a thickness T5 of the sealing layer 150 is about 150 μm to 500 μm. In some embodiments, when the thickness of the sealing layer 150 is about 150 μm to 500 μm, an OD value of the sealing layer 150 is greater than or equal to 2.
With reference to FIG. 1Ia and FIG. 1Ic, in some embodiments, the display panel 10 further includes pads PD located in the lead out wiring region LA. In some embodiments, the display panel 10 further includes chip bonding films CF, and the chip bonding films CF are electrically connected to the pads PD. In some embodiments, pins of the chip bonding films CF are electrically connected to the pads PD through a conductive adhesive AF (e.g., an anisotropic conductive adhesive). In some embodiments, the display panel 10 further includes a protection adhesive PG that is located at the lead out wiring region LA and covers the chip bonding films CF. In some embodiments, a material of the protection adhesive PG is different from a material of the encapsulation layer 130. In some embodiments, the protection adhesive PG further extends to the second side surface 112 of the circuit substrate 110.
In some embodiments, the second terminal surface 132 of the encapsulation layer 130 is located between the light-emitting elements 120 and the second side surface 112 of the circuit substrate 110. In some embodiments, the second terminal surface 132 of the encapsulation layer 130 is located at the lead out wiring region LA. In some embodiments, there is a pitch SP between the second terminal surface 132 of the encapsulation layer 130 and the second side surface 112 of the circuit substrate 110. In some embodiments, the pads PD are disposed between the second terminal surface 132 of the encapsulation layer 130 and the second side surface 112 of the circuit substrate 110.
With reference to FIG. 1Ia and FIG. 1Ib, in some embodiments, the display panel 10 further includes the optical layer 140 that is disposed at the display region AA and located on the light-emitting elements 120 and the encapsulation layer 130. In some embodiments, the first edge surface 141 of the optical layer 140 extends beyond the first terminal surface 131 of the encapsulation layer 130, and the optical layer 140 is further located on the sealing layer 150. In other words, the sealing layer 150 may physically contact the first terminal surface 131 of the encapsulation layer 130 and a bottom surface 140B of the optical layer 140. In some embodiments, the top surface 130T of the encapsulation layer 130 is aligned with the surface 150T of the sealing layer 150. In some embodiments, the cutting marks on the first edge surface 141 of the optical layer 140 continuously extend to the cutting surface 151 of the sealing layer 150. In some embodiments, the optical layer 140 includes a plurality of film layers. In some embodiments, a thickness T4 of the optical layer 140 is approximately 100 μm to 150 μm. In some embodiments, the display panel 10 further includes an adhesive layer (not shown) located between the light-emitting elements 120 and the encapsulation layer 130 and the optical layer 140, and the adhesive layer is, for instance, an acrylic adhesive layer.
Other embodiments provided in the disclosure are described below with reference to FIG. 2 to FIG. 6, and reference numbers of the elements and a part of contents of the embodiments depicted in FIG. 1A to FIG. 1Ic are also used in the following embodiments, where the same reference numbers denote the same or like elements, and descriptions of the same technical contents are omitted. The previous embodiments depicted in FIG. 1A to FIG. 1Ic may be referred to for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiments.
FIG. 2 is a schematic cross-sectional diagram illustrating a display panel 20 according to an embodiment of the disclosure. The display panel 20 includes the circuit substrate 110, the light-emitting elements 120, an encapsulation layer 230, the optical layer 140, and a sealing layer 250.
In comparison, the display panel 10 shown in FIG. 1Ia to FIG. 1Ic and the display panel 20 shown in FIG. 2 are different, and the difference lies in that the display panel 20 is a transparent display panel, and that the encapsulation layer 230 of the display panel 20 may include a transparent encapsulation adhesive. In some embodiments, a horizontal height of the top surface 230T of the encapsulation layer 230 is greater than the horizontal height of the top surface 120T of the light-emitting elements 120. In other words, the encapsulation layer 230 may completely cover the light-emitting elements 120. In some embodiments, a transmittance of the encapsulation layer 230 is greater than or equal to 80%. In some embodiments, a thickness of the encapsulation layer 230 is about 10 μm to 50 μm. In some embodiments, the sealing layer 250 includes a transparent sealing adhesive. In some embodiments, a transmittance of the sealing layer 250 is greater than or equal to 80%. In addition, the sealing layer 250 may cover a first terminal surface 231 of the encapsulation layer 230 and the first side surface 111 of the circuit substrate 110.
FIG. 3A to FIG. 3Da are schematic cross-sectional diagrams illustrating steps of a manufacturing method of a display panel 30 according to an embodiment of the disclosure. The steps depicted in FIG. 3A to FIG. 3Da may be carried out following the steps depicted in FIG. 1A to FIG. 1D.
With reference to FIG. 3A, after the encapsulation layer 130 is formed on the circuit substrate 110 and between the light-emitting elements 120, the optical layer 140 may be formed on the encapsulation layer 130 and the light-emitting elements 120. In some embodiments, the optical layer 140 at least completely covers the light-emitting elements 120. In some embodiments, the optical layer 140 completely covers the encapsulation layer 130.
With reference to FIG. 3B, after the optical layer 140, the encapsulation layer 130, and the circuit substrate 110 are cut, the display region AA where the light-emitting elements 120 are disposed and the lead out wiring region LA where the pads PD are disposed are left, and the cutting surfaces of the optical layer 140, the encapsulation layer 130, and the circuit substrate 110 are exposed. For instance, after the cutting process is performed, the first edge surface 141, the third edge surface 143, and the fourth edge surface 144 of the optical layer 140, the first terminal surface 131, the third terminal surface 133, and the fourth terminal surface 134 of the encapsulation layer 130, and the first side surface 111, the third side surface 113, and the fourth side surface 114 of the circuit substrate 110 are exposed. In some embodiments, a laser may be applied to cut the optical layer 140, the encapsulation layer 130, and the circuit substrate 110. In some embodiments, a UV laser may be applied to cut the optical layer 140 and the encapsulation layer 130, and an IR laser may be applied to cut the circuit substrate 110. With reference to FIG. 3B to FIG. 3C, a sealing layer 350 is formed on the cutting surfaces of the optical layer 140, the encapsulation layer 130, and the circuit substrate 110. For instance, the sealing layer 350 may be formed on the first edge surface 141, the third edge surface 143, and the fourth edge surface 144 of the optical layer 140, the first terminal surface 131, the third terminal surface 133, and the fourth terminal surface 134 of the encapsulation layer 130, and the first side surface 111, the third side surface 113, and the fourth side surface 114 of the circuit substrate 110. With reference to FIG. 3Da, the chip bonding films CF are disposed at the lead out wiring region LA, and the chip bonding films CF are electrically connected to the pads PD, thereby completing the fabrication of the display panel 30.
FIG. 3Da is a schematic three-dimensional diagram illustrating the display panel 30 according to an embodiment of the disclosure. FIG. 3Db is a schematic cross-sectional diagram taken along a sectional line C-C′ in FIG. 3Da. With reference to FIG. 3Da and FIG. 3Db, the display panel 30 includes the circuit substrate 110, the light-emitting elements 120, the encapsulation layer 130, the optical layer 140, and a sealing layer 350.
In comparison, the display panel 10 shown in FIG. 1Ia to FIG. 1Ic and the display panel 30 shown in FIG. 3Da to FIG. 3Db are different, and the difference lies in that the first edge surface 141 of the optical layer 140 is aligned with the first terminal surface 131 of the encapsulation layer 130, and the sealing layer 350 covers the first edge surface 141 of the optical layer 140, the first terminal surface 131 of the encapsulation layer 130, and the first side surface 111 of the circuit substrate 110. As such, the sealing layer 350 may prevent an interface OF between the optical layer 140 and the encapsulation layer 130 and the interface IF between the encapsulation layer 130 and the circuit substrate 110 from peeling off, thereby improving the reliability of the display panel 30.
FIG. 4 is a schematic cross-sectional diagram illustrating a display panel 40 according to an embodiment of the disclosure. The display panel 40 includes the circuit substrate 110, the light-emitting elements 120, the encapsulation layer 230, the optical layer 140, and a sealing layer 450.
In comparison, the display panel 30 shown in FIG. 3Da to FIG. 3Db and the display panel 40 shown in FIG. 4 are different, and the difference lies in that the display panel 40 is a transparent display panel, and that the encapsulation layer 230 of the display panel 40 includes a transparent encapsulation material. In some embodiments, the horizontal height of the top surface 230T of the encapsulation layer 230 is greater than the horizontal height of the top surface 120T of the light-emitting elements 120. In other words, the encapsulation layer 230 may completely cover the light-emitting elements 120. In some embodiments, the transmittance of the encapsulation layer 230 is greater than or equal to 80%. In some embodiments, the thickness of the encapsulation layer 230 is about 10 μm to 50 μm. The sealing layer 450 may cover the first edge surface 141 of the optical layer 140, the first terminal surface 231 of the encapsulation layer 230, and the first side surface 111 of the circuit substrate 110. In some embodiments, the sealing layer 450 includes a transparent sealing material. In some embodiments, the transmittance of the sealing layer 450 is greater than or equal to 80%.
FIG. 5A is a schematic three-dimensional diagram illustrating a tiled display device 100 according to an embodiment of the disclosure. FIG. 5B is a schematic cross-sectional diagram taken along a sectional line D-D′ in FIG. 5A. FIG. 5C is a schematic cross-sectional diagram taken along a sectional line E-E′ in FIG. 5A. With reference to FIG. 5A, the tiled display device 100 includes two of the above-mentioned display panels 10.
With reference to FIG. 5B, in some embodiments, the first side surface 111 of the circuit substrate 110 of the left display panel 10 faces the first side surface 111 of the circuit substrate 110 of the right display panel 10. In some embodiments, the sealing layers 150 of the two display panels 10 are located between the two display panels 10. In some embodiments, the first edge surfaces 141 of the optical layers 140 of the two display panels 10 substantially physically contact each other, thus enabling seamless tiling of the optical layers 140 of the two display panels 10.
With reference to FIG. 5A and FIG. 5C, in some embodiments, the sealing layer 150 further extends from one portion of the first side surface 111 located in the display region AA to the other portion of the first side surface 111 located in the lead out wiring region LA, and in the lead out wiring region LA, the sealing layer 150 is sandwiched between the two circuit substrates 110. In some embodiments, the tiled display device 100 includes two of the above-mentioned display panels 20.
FIG. 6 is a schematic three-dimensional diagram illustrating a tiled display device 200 according to an embodiment of the disclosure. In comparison, the tiled display device 100 shown in FIG. 5A to FIG. 5C and the tiled display device 200 shown in FIG. 6 are different, and the difference lies in that the tiled display device 200 includes two of the above-mentioned display panels 30.
In some embodiments, the first side surface 111 of the circuit substrate 110 of the left display panel 30 adjoins the first side surface 111 of the circuit substrate 110 of the right display panel 30. In some embodiments, the sealing layers 350 of the two display panels 30 are sandwiched between the optical layers 140, the encapsulation layers 130, and the circuit substrates 110 of the two display panels 30, thus enabling seamless tiling of the two display panels 30. A width W3 of the sealing layer 350 is not particularly limited as long as the pitch between the light-emitting elements 120 on both sides of the sealing layer 350 is roughly equal to the pitch between the two adjacent light-emitting elements 120 in each display panel 30. In some embodiments, the width W3 of the sealing layer 350 is about 30 μm to 100 μm. In some embodiments, the tiled display device 200 includes two of the above-mentioned display panels 40.
To sum up, in the display panel provided in one or more embodiments of the disclosure, the interface between the encapsulation layer and the circuit substrate is sealed by the sealing layer, thus preventing the interface from peeling off in the high temperature and high humidity environment and further improving the reliability of the display panel. In addition, according to the manufacturing method of the display panel provided in one or more embodiments of the disclosure, the thickness uniformity of the encapsulation layer in the display region is improved by applying the initial encapsulation layer to the display region and the peripheral region and then performing the cutting process.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Patent Application
20240313181
