The entire disclosures of Japanese Patent Applications Nos. 2005-290423 and 2006-248114 including specification, claims, drawings, and abstract are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display panel on which a plurality of pixels are formed in a matrix form, and, in particular, to a line for supplying power to a display element of each pixel..
2. Description of the Related Art
Self-emissive electroluminescence (hereinafter referred to as “EL”) elements, in particular, organic EL elements which use an organic light emitting material in a light emitting layer are known types of current-driven display elements. In particular, because active matrix displays in which a pixel transistor (thin film transistor or “TFT”) is provided in each pixel for controlling, for each pixel, the display element by the transistor are advantageous for realizing a high quality display, much recent development has focused on active matrix displays using an EL element as the display element.
The element driving transistor Td has a source connected to the power supply line PL and a drain connected to an anode of the organic EL element 55. A cathode of the organic EL element 55 is connected to a cathode power supply CV which is formed common to the pixels. One electrode of the storage capacitor Cs is connected between the gate of the element driving transistor Td and the source of the selection transistor Ts. The other electrode of the storage capacitor Cs is connected to a power supply of a constant voltage such as, for example, ground and a power supply line.
In this circuit, when a selection signal is output and the gate line GL is set to the high (H) level, the selection transistor Ts is switched on, a data signal on the data line DL is supplied via the selection transistor Ts to the storage capacitor Cs and to the gate of the element driving transistor Td, the element driving transistor Td allows a drive current corresponding to the gate signal voltage of the element driving transistor Td to flow from the power supply line PL to the organic EL element 55, and the organic EL element 55 emits light at a luminance corresponding to the drive current. As a result of the storage capacitor Cs storing charges corresponding to the supplied data signal, the gate voltage of the element driving transistor Td is maintained at a voltage corresponding to the data signal for a predetermined period. Therefore, even when the gate line GL is set to the low (L) level, the element driving transistor Td is operated by the stored voltage of the storage capacitor Cs, supply of the drive current is maintained, and the organic EL element 55 continues to emit light.
In
The plurality of the external connection terminals provided at the lower side of the organic EL display panel 100 include, in addition to the drive power supply terminal T1, a cathode terminal T2, a terminal T3 for supplying a timing signal or the like to the V-related driver 108, and a terminal T4 for supplying a timing signal and a data signal to the H-related driver 106.
As described in the above-described Patent Document 1, the power supply line PL connected to the EL element of each pixel via the element driving transistor Td and which supplies a current to the EL element is connected to the wide portion 110 provided along one side of a peripheral portion of the display region and the wide portion 110 is connected to the power supply terminal T1 via an extension line 112 which is also formed in a wide width. The wide portion 110 and wide extension line 112 are employed in order to supply drive current to each power supply line PL with a minimum power loss. Regarding the power supply line PL within the display region connected to each EL element, however, when the line distance from the terminal T1 becomes longer, the voltage drop generated due to the line resistance is increased. Because of this, the EL element of a pixel at a position more distant from the power supply terminal T1 would have a lower light emission luminance compared to the EL element of a pixel at a closer position. Specifically, a slope occurs among light emission luminance of EL elements in the display region, and the difference in the light emission luminance in the display region is recognized as luminance unevenness, resulting in degradation of the display quality as a display. Such a slope in light emission luminance becomes more significant as the area of the display panel, number of pixels, or resolution is increased, hampering efforts to increase the size and resolution of displays.
The present invention advantageously ensures the uniformity of power supplied to display elements within the display region.
According to one aspect of the present invention, there is provided a display panel comprising a plurality of pixels arranged in a matrix form in a display region, wherein each pixel comprises a display element which performs a display operation according to power supplied from a power supply line, the power supply line comprises a plurality of branch lines each of which is provided in the display region, is electrically connected to the display element, and supplies power to the display element and a trunk line which is provided on a peripheral portion of the display region and electrically connected to the plurality of the branch lines, the trunk line is formed along at least two sides on the peripheral portion of the display region, and a line width of the trunk line is larger than a line width of the branch line.
According to another aspect of the present invention, there is provided a display panel comprising a plurality of pixels arranged in a matrix form in a display region, wherein each pixel comprises a display element which performs a display operation according to power supplied from a power supply line, the power supply line comprises a plurality of branch lines each of which is provided in the display region, is electrically connected to the display element, and supplies power to the display element and a trunk line which is provided on a peripheral portion of the display region and electrically connected to the plurality of the branch lines, and the trunk line is formed along at least three sides of the peripheral portion of the display region. In the display panel, a line width of the trunk line can be set larger than a line width of the branch line at least on two sides of the peripheral portion of the display region.
According to another aspect of the present invention, there is provided a display panel comprising a plurality of pixels arranged in a matrix form in a display region, wherein each pixel comprises a display element which performs a display operation according to power supplied from a power supply line, the power supply line comprises a plurality of branch lines each of which is provided in the display region, is electrically connected to the display element, and supplies power to the display element and a trunk line which is provided on a peripheral portion of the display region and electrically connected to the plurality of the branch lines, an external connection terminal to which the power supply line is electrically connected is provided on a first side along a vertical scan direction of the display region, the trunk line extends from the first side and is provided at least along a second side along a horizontal scan direction of the display region and a fourth side which opposes the second side with the display region therebetween, and the plurality of the branch lines are connected to the trunk line of the second side and the trunk line of the fourth side and formed along the vertical scan direction.
According to another aspect of the present invention, it is preferable that, in the display panel, the trunk line is provided on the peripheral portion of the display region also on a third side which opposes the first side, on which the external connection terminal is provided, with the display region therebetween, and a cross sectional area of the trunk line which is provided on the third side is larger than a cross sectional area of the trunk line which is provided on the first side.
According to another aspect of the present invention, it is preferable that, in the display panel, the external connection terminal to which the power supply line is electrically connected is provided on a first side along a vertical scan direction of the display region and the trunk line is provided at least from the first side and along a second side along a horizontal scan direction of the display region, and the plurality of branch lines are provided from the second side toward the vertical scan direction.
According to another aspect of the present invention, it is preferable that, in the display panel, the trunk line is provided on the peripheral portion of the display region also on a third side opposing the first side, on which the external connection terminal is provided, with the display region therebetween and on a fourth side which opposes the second side with the display region therebetween, and a cross sectional area of the trunk line which is provided on the third side is larger than a cross sectional area of the trunk line which is provided on the first side.
According to another aspect of the present invention, it is preferable that, in the display panel, a cross sectional area of the trunk line is larger than a cross sectional area of the branch line. The trunk line may be provided along four sides on the peripheral portion of the display region, or the trunk line may be provided surrounding all peripheries of the display region.
According to another aspect of the present invention, it is preferable that, in the display panel, a current-driven electroluminescence element, for example, be used as the display element.
According to another aspect of the present invention, it is preferable that, in the display panel, the trunk line comprises a first line layer which is formed simultaneously with the branch line and with a same material as the branch line and a second line layer which is formed separately from the first line layer and electrically connected to the first line layer.
According to another aspect of the present invention, it is preferable that, in the display panel, the display element comprises a lower electrode which is individual for each pixel and an upper electrode which is common to the pixels, and the second line layer is formed simultaneously with the upper electrode and with a same material as the upper electrode. As the second line layer, it is possible to use a layer which is formed above an insulating layer which is formed above the first line layer in the peripheral region of the display region.
By providing a trunk line electrically connected to a branch line on at least two sides on the peripheral portion of the display region in addition to the branch line provided on the display region and electrically connected to the display element of each pixel, the line resistance of the power supply line of the display panel as a whole can be reduced. In addition, by providing the trunk line on the peripheral portion of the display region, it is possible to increase the line width and the cross sectional area of the trunk line without being limited by factors such as the pixel pitch or the like.
For example, by providing the trunk line on the peripheral portion of the display region along a plurality of sides, power can be supplied from the external connection terminal to the display elements not only from one end within the display region and via a branch line, but also from the other end of the branch line via the trunk line detouring around the peripheral portion of the display region. Thus, it is possible to set the voltage values of both ends to be close to each other even in a configuration in which the branch line is provided only along one direction of the pixel region.
In addition, when the trunk line is provided on a plurality of sides along the peripheral portion of the display region, by increasing the line width and the cross sectional area of a side farther away from the external connection terminal to which the power supply line is electrically connected than the side nearer to the external connection terminal, it is possible to reduce the line resistance at the side which is farther away from the terminal in which the voltage drop is large, to reduce the voltage drop. In other words, it is possible to increase a percentage of the trunk line having a low resistance in a route of the drive power supply line from the external power supply terminal to the pixel, and, thus, the voltage drop can be reduced.
By providing, as the trunk line, a second line layer which is formed separately from a first line layer and which is electrically connected to the first line layer in addition to the first line layer which is formed simultaneously with the branch line and with a same material as the branch line, it is possible to increase the cross sectional area of the trunk line while inhibiting the area along a planar direction of the panel. Thus, the line resistance of the power supply line can be reduced while not reducing the display area.
Preferred embodiments of the present invention will be described in detail by reference to the drawings, wherein:
Preferred embodiments of the present invention will now be described referring to the drawings.
Each pixel is formed approximately in a region defined by these lines and comprises, for example, an organic EL element as a display element, a selection transistor Tr1, an element driving transistor Tr2, and a storage capacitor Cs.
The selection transistor Tr1 in this configuration is an n-channel thin film transistor (TFT) and the element driving transistor is a p-channel TFT. The selection transistor Tr1 has a drain connected to a data line 18 for supplying a data voltage to the pixels positioned along the vertical scan direction and a gate connected to a gate line 16 for selecting pixels positioned along one horizontal scan line.
The element driving transistor Tr2 has a gate connected to the source of the selection transistor Tr1, a source connected to a power supply line 20, and a drain connected to a first electrode (in the exemplified configuration, an anode) of the organic EL element 55. In the present embodiment, the first electrode (anode) of the organic EL element 55 is formed in an individual pattern for each pixel and a second electrode (cathode) of the organic EL element 55 is formed common to the pixels and is connected to a common cathode power supply CV. One electrode (first electrode) of the storage capacitor Cs is connected to the gate of the element driving transistor Tr2 and to the source of the selection transistor Tr1, and another electrode (second electrode) of the storage capacitor Cs is maintained at a constant voltage. In the exemplified configuration, the second electrode of the storage capacitor Cs is connected to a power supply line 20 and is maintained at a power supply voltage (PVDD).
In both the selection transistor Tr1 and the element driving transistor Tr2, a semiconductor material is used as an active layer. For example, amorphous silicon and crystalline silicon such as, for example, polycrystalline silicon obtained by polycrystallization through laser annealing may be used in the active layer. In addition, when the crystalline silicon is used in the active layer, an n-channel thin film transistor and a p-channel thin film transistor can be easily formed by doping an n conductive impurity and a p conductive impurity into the active layer using the gate as a mask.
The crystalline silicon thin film transistor can be used not only for the pixel circuit, but also as circuit elements of a peripheral driver circuit for sequentially selecting and controlling the transistors in the pixel circuit. Therefore, in the organic EL display 10 of the present embodiment, a crystalline silicon thin film transistor having a structure similar to that of the pixel transistor is formed on the panel substrate 12, simultaneously with the formation of the pixel transistors, so that a peripheral driver circuit is built in. More specifically, the peripheral driver circuit includes an H-related driver 22 and a V-related driver 24, and, as shown in
In addition, a drive current trunk line 26 which is a part of a drive current line for supplying a drive current from the drive power supply PVDD to each pixel is provided on a side region of the display region 14 opposing the H-related driver 22 (lower side region of the panel in
In the EL display panel according to the present embodiment, external connection terminals 32 connected to an external circuit for supplying various timing signals, data signals, power supplies, etc. to the H-related driver 22, V-related driver 24, drive current lines (20, 26, and 28), or the like are provided on one of two opposing sides along the vertical scan direction of the panel. The present embodiment, however, is not limited to such a configuration, and can be applied to a configuration in which the external connection terminals 32 are formed on other sides such as, for example, a side opposing the H-related driver 22 and along the horizontal scan direction (lower side of the panel in
In the example structure of
In the present embodiment, the cross sectional areas of the first and second trunk lines 26 and 28 are formed to be larger than that of the branch line 20. The cross sectional area of the trunk line is preferably twice or larger that of the branch line 20. When the drive current lines are to be simultaneously formed by patterning a same conductive layer, because the thickness is identical, the cross sectional area of the line is adjusted by adjusting the width of the line (length in a direction perpendicular to the extension direction of the line). In other words, as shown in
Alternatively, it is also possible to employ a configuration in which only one of the third and fourth trunk lines 72 and 74 is provided. A portion of current supplied from the external connection terminal.32 flows through the third and fourth trunk lines 72 and 74 to the second trunk line 28 at the upper side, and is supplied to corresponding pixels via each branch line 20 in addition to the current from the first trunk line 26. The third and fourth trunk lines 72 and 74 have a larger cross sectional area than the branch line 20 similar to the first and second trunk lines 26 and 28, and preferably have twice or larger cross sectional area. It is preferable that the line width (cross sectional area) of the fourth trunk line 74 be larger than the line width (cross sectional area) of the third trunk line 72. By employing such a relationship, the voltage drop in the fourth trunk line 74 which is provided at a position farther away from the external connection terminal 32 is minimized. On the other hand, the third trunk line 72 is provided at a position close to the terminal 32, and, thus, by setting the line width of the third trunk line 72 to be small, the potential difference with the side of the fourth trunk line 74 is reduced. With this structure, the voltage difference between the voltage applied to a pixel at an upper right corner which is farthest away from the external connection terminal 32 and the voltage applied to the pixel of the lower left corner which is closest to the external connection terminal 32 in the structure of
A placement method of the second trunk line 28 provided between the H-related driver 22 and the display region 14 will now be described referring to
A data line 18 extends from the H-related driver 22 along the vertical scan direction. The data line 18 and the branch line 20 of the drive power supply line formed in the display region 14 along the vertical scan direction similar to the data line 18 are formed using the same conductive layer (for example, Al layer). The trunk line can be formed simultaneously and integrally with the branch line 20 through patterning of the same conductive layer as the branch line 20. In this case, if the second trunk line 28 is to be simply provided between the H-related driver 22 and the display region 14, it is necessary to employ a measure to prevent short-circuiting of the second trunk line 28 and the data line 18.
In the present embodiment, as shown in
At an intersecting portion between the data line 18 and the second trunk line 28, by separately placing the data line 18 by the intersecting line 46 rather than the second trunk line 28, a a much higher voltage (for example, +12V), even compared to the other power supplies, other data signals, etc., is applied, and any increase in the line resistance in the drive current line route having a high voltage drop due to the line resistance can be inhibited.
A structure of and a method of manufacturing a TFT and EL element built into the panel shown in
The gate electrode 44 is selectively left above the active layer 40 at a position in which a channel region of the TFT is to be formed and the active layer 40 is doped with an impurity with the gate electrode 44 functioning as a mask. An intrinsic channel region which is not doped with the impurity is formed in a region of the active layer 40 covered by the gate electrode 44, and regions on both sides of the channel region and not covered by the gate electrode are doped with an impurity so that a drain region and a source region are formed. After the impurity doping process, an interlayer insulating layer 48 in which a SiN film and a SiO2 film are layered in this order is formed covering the entire surface of the substrate.
Then, contact holes are formed though the interlayer insulating layer 48 and a gate insulating layer 42 at positions corresponding to the source and drain regions of the TFT and a contact hole is formed through the interlayer insulating layer 48 at a position of formation of a contact between the intersecting line 46 and the data line 18 at the upper layer. A layered metal conductive layer having a structure comprising layers of Mo, Al, and Mo is formed above the interlayer insulating layer 48 and is patterned to form the data line 18, the power supply line (branch line) 20, and the trunk lines (26, 28, 72, and 74) which are integral with the power supply line 20. The layered structure of Mo, Al, and Mo may also be used for the external connection terminal 32.
Then, a first planarizing insulating layer 54 is formed over an entire surface of the substrate covering these lines using an insulating material made of, for example, an acrylic resin and a contact hole through the first planarizing insulating layer 54 is formed in a region corresponding to the source (or the drain) of the element driving transistor Tr2. A conductive transparent metal oxide layer such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) is then formed above the first planarizing insulating layer 54, patterned into a desired shape so that a pixel electrode 56 (first electrode of the organic EL element) having an individual pattern for each pixel is formed. Alternatively, it is also possible to form the transparent conductive metal oxide layer also above the Mo/Al/Mo metal terminal layer 78 exposed by removing the first planarizing insulating layer 54 at the terminal portion simultaneously with the formation of the pixel electrode 56. With this structure, by covering the metal terminal layer by a metal oxide layer 80, it is possible to inhibit increase in connection resistance by surface oxidation or the like even when the terminal is exposed to the outside environment.
After the pixel electrode 56 is formed, a second planarizing insulating layer 58 made of an insulating material such as an acrylic resin is formed covering the entire substrate, and, in a region of formation of the pixel electrode 56, an edge portion of the second planarizing insulating layer 58 is removed to form an opening and expose a surface of the pixel electrode 56. A light emitting element layer 60 including an organic light emitting material is layered above the second planarizing insulating layer 58 through vacuum evaporation or the like and a second electrode 62 common to the pixels is formed above the light emitting element layer 60 using Al, an Al alloy, a MgAg alloy, etc. and through, for example, layering by vacuum evaporation.
The light emitting element layer 60 comprises at least a light emitting layer containing an organic compound having a light emitting function, and may have a single layer structure or a multi-layer structure depending on the function of the compound to be used. When the first electrode 56 is an anode and the second electrode 62 opposing the first electrode 56 is a cathode as in the present embodiment, for example, the light emitting element layer 60 may have a layered structure of a hole injection layer 601, a hole transport layer 602, a light emitting layer 603, and an electron transport layer 604, formed in this order from the side of the first electrode.
The charge transport layer and injection layer other than the light emitting layer may be formed common to all pixels. When an emission color of the EL element of each pixel is white and a full-color display is to be realized by obtaining light of R, G, and B using color filters, the light emitting layer 603 of the organic EL element does not need to be formed in an individual pattern for each pixel using a mask even when the light emitting layer 603 is to be formed through vacuum evaporation, and may be formed common to all pixels. When the EL element of each pixel emits corresponding light of R, G, or B, organic light emitting materials different for each emission color needs to be used, and at least the light emitting layer 603 is formed in an individual pattern for each pixel. Although not shown in
As is clear from the structure of
The fourth trunk line 74 formed along the third side of the panel is provided between the V-related driver 24 and the display region 14. However, the gate line 16 extending from the V-related driver 24 and the fourth trunk line 74 are separate conductive layers and the interlayer insulating layer 48 is present between these conductive layers. Therefore, also regarding the fourth trunk line 74, there is no need for forming a special three-dimensional intersection structure, even when the fourth trunk line 74 is formed on the third side.
When, for example, the branch line 20 is formed in a lattice shape in the display region, that is, when the branch line 20 is also laid out along the horizontal scan direction in the display region, it is also possible to omit the second trunk line to be provided between the H-related driver 22 and the display region, and form the trunk lines on three sides including two sides along the vertical scan direction (first and third sides) and a side along the horizontal scan direction (second side).
In the above-described layout of the EL panel, a case is described in which the external connection terminals are formed on a side along the vertical scan direction of the panel. However, the present embodiment is not limited to such a configuration, and similar advantages can be obtained by providing external connection terminals 92 on a side along the horizontal scan direction of the panel (lower side in the example configuration of
In this case, the trunk line for supplying power connected to the branch line 20, provided along two or more sides, and formed to have a cross sectional area larger than that of the branch line 20 may be formed, for example, surrounding four sides of the display region 14 at the peripheral portion of the display region 14 as shown in
The line widths (and corresponding cross sectional areas) of the trunk lines 94 and 96 located on the left and right sides can be set equal because the positions from the external connection terminals 92 are close to the center portion along the horizontal scan direction. The line width (and corresponding cross sectional area) of the second trunk line 28 provided on the upper side may be set larger than the third trunk line 94 and the fourth trunk line 96, because the second trunk line 28 is at a position which is farthest away from the terminals. Alternatively, it is also possible to employ a configuration in which the trunk lines are formed only on the upper and lower sides of the panel as shown in
The position of the contact hole 88 can also be suitably changed. As shown in
As shown in
Number | Date | Country | Kind |
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2005-290423 | Oct 2005 | JP | national |
2006-248114 | Sep 2006 | JP | national |