Patent Application
20150269910
1. Field of the Invention
The present invention illustrates a display panel, and more particularly, the display panel having the capability for detect failed stages of the gate driving circuit.
2. Description of the Prior Art
With the advancement of the liquid crystal display (LCD), several multi-functional and convenient LCD screens are developed and widely applied to various electronic devices in recent years, such as televisions, mobile phones, tablets, etc. Generally, an LCD device includes a gate driving circuit. The gate driving circuit outputs the scan signal to the corresponding gate line for enabling the pixels coupled to the gate line. To reduce the volume of the display and improve the display efficiency, a gate in panel (GIP) technique is further developed. The main idea of GIP technique is to integrate the gate driving circuit on the array fabricated board instead of using a driving chip to realize the driving circuit in a conventional LCD device. The array fabricated board can be a circuit board with a glass material or even a bendable material. Like the driving method of the conventional LCD device, in GIP circuit, the scan signals sequentially output different voltage amplitudes (i.e., high or low voltage amplitude) to the corresponding gate lines according to a clock signal for enabling a plurality of pixels of the display panel.
However, since the gate driving circuit includes a plurality of stages of gate driving unit and each stage of the gate driving unit outputs the scan signal to the gate line according to the scan signal produced by the previous stage of gate driving unit, all scan signals produced by the gate driving units have causality properties. This means that when N stages of a gate driving unit are used in the gate driving circuit and the nth stage of the gate driving unit has failed, all the scan signals produced by nth to Nth are involved to error signal waveforms while decreasing the image display quality. Thus, an appropriate inspection circuit used to detect the scan signals in the gate driving circuit for identifying the failed stage of gate driving unit is an important device to improve the image display quality.
According to the claimed invention, a display panel includes a plurality of rows of pixels, agate driving circuit, a source driving circuit, and an inspection circuit. Each row of pixels includes a plurality of pixels. The gate driving circuit includes a plurality of gate driving units. Each gate driving unit outputs a scan single for enabling the corresponding row of pixels. The source driving circuit is coupled to the plurality of pixels for transmitting data signals to the plurality of pixels. The inspection circuit includes a plurality of transistors. Each transistor includes a first terminal coupled to a test pad, a control terminal coupled to the corresponding gate driving unit and the corresponding row of pixels, and a second terminal coupled to the control terminal of the transistor. When the gate driving unit outputs the scan signal, the scan signal enables the transistor so that the transistor can transmit the scan signal to the test pad for determining whether the gate driving unit outputs the correct scan signal or not.
According to the claimed invention, another display panel includes a plurality of rows of pixels, a first gate driving circuit, a second gate driving circuit, a source driving circuit, a first inspection circuit, and a second inspection circuit. Each row of pixels includes a plurality of pixels. The first gate driving circuit includes a plurality of first gate driving units. Each first gate driving unit outputs a first scan single for enabling the row of pixels coupled to the first gate driving unit . The second gate driving circuit includes a plurality of second gate driving units. Each second gate driving unit outputs a second scan single for enabling the row of pixels coupled to the second gate driving unit. The source driving circuit is coupled to the plurality of pixels for transmitting data signals to the plurality of pixels. The first inspection circuit includes a plurality of first transistors. Each first transistor includes a first terminal coupled to a first test pad, a control terminal coupled to the corresponding first gate driving unit, and a second terminal coupled to the control terminal of the first transistor. The second inspection circuit includes a plurality of second transistors. Each second transistor includes a first terminal coupled to a second test pad, a control terminal coupled to the corresponding second gate driving unit, and a second terminal coupled to the control terminal of the second transistor. When the first gate driving unit outputs the first scan signal, the first scan signal enables the first transistor so that the first transistor can transmit the first scan signal to the first test pad for determining whether the first gate driving unit outputs the correct first scan signal or not. When the second gate driving unit outputs the second scan signal, the second scan signal enables the second transistor so that the second transistor can transmit the second scan signal to the second test pad for determining whether the second gate driving unit outputs the correct second scan signal or not.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
In the inspection circuit 110, the plurality of transistors N1 to NN can be a plurality of N-type metal-oxide-semiconductor field-effect transistors (N-type MOSFET). Each transistor N1 to NN includes a first terminal, a control terminal, and a second terminal. The first terminal is coupled to the test line T1. The control terminal is coupled to the gate line G1 to GN with respect to the corresponding gate driving unit GD1 to GDN. The second terminal is coupled to the control terminal of the transistor N1 to NN. The test pad 105 is coupled to a terminal of the test line T1.
In other words, in this embodiment, the first terminal of the transistor N1 is coupled to the test line T1. The second terminal and the control terminal of the transistor N1 is coupled to the 1st gate line G1. The first terminal of the transistor N2 is coupled to the test line T1. The second terminal and the control terminal of the transistor N2 is coupled to the 2nd gate line G2. The first terminal of the transistor N3 is coupled to the test line T1. The second terminal and the control terminal of the transistor N3 is coupled to the 3rd gate line G3. And so on, the first terminal of the transistor NN is coupled to the test line T1. The second terminal and the control terminal of the transistor NN is coupled to the nth gate line GN.
In this embodiment, the pixel array 120 is considered as an N×M pixel array, where M is a positive integer. The plurality of pixels of the pixel array 120 are operated by using N gate lines G1 to GN and M data lines S1 to SM. When the display panel 20 displays the image, the plurality of gate driving units GD1 to GDN sequentially transmit the scan signals to the corresponding plurality of gate lines G1 to GN for sequentially enabling the 1st rows of the pixels to the Nth rows of the pixels in the pixel array 120. Then, the image data can be transmitted to the pixels according to the corresponding data lines S1 to SM.
For example, the 1st gate driving unit GD1 produces a high voltage scan signal with unit width of the clock signal waveform in the 1st timing interval of the clock signal and transmits the high voltage scan signal to the 1st gate line G1 for enabling the 1st row of pixels corresponding to the 1st gate line G1 in the pixel array 120. The 2nd gate driving unit GD2 produces a high voltage scan signal with unit width of the clock signal waveform in the 2nd timing interval of the clock signal and transmits the high voltage scan signal to the 2nd gate line G2 for enabling the 2nd row of pixels corresponding to the 2nd gate line G2 in the pixel array 120. The 3rd gate driving unit GD3 produces a high voltage scan signal with unit width of the clock signal waveform in the 3rd timing interval of the clock signal and transmits the high voltage scan signal to the 3rd gate line G3 for enabling the 3rd row of pixels corresponding to the 3rd gate line G3 in the pixel array 120. And so on, the Nth gate driving unit GDN produces a high voltage scan signal with unit width of the clock signal waveform in the Nth timing interval of the clock signal and transmits the high voltage scan signal to the Nth gate line GN for enabling the Nth row of pixels corresponding to the Nth gate line GN in the pixel array 120.
Specifically, the scan signals are sequentially produced by the plurality of gate driving units GD1 to GDN. A positive delay timing interval exists between the falling edge of the scan signal outputted by the former stage and the rising edge of the scan signal outputted by the latter stage of the gate driving unit. Such positive delay timing interval is equal or greater than the resistor-capacitor delay (RC delay) and can avoid the pulses overlapping effect of the scan signals in adjacent timing intervals. By using the positive delay timing interval to eliminate the interference caused by the pulses overlapping, the image display quality can be improved. When the plurality of gate driving units GD1 to GDN respectively produce the high voltage scan signals, since the control terminal and the second terminal of the plurality of transistors N1 to NN in the inspection circuit 100 are respectively coupled to the plurality of gate lines G1 to GN, the high voltage scan signal enables the corresponding transistor. Thus, the high voltage scan signal can be further transmitted from the second terminal of the enabled transistor to the test line T1 coupled to the first terminal of the enabled transistor.
This means that when the 1st gate line G1 carries a high voltage scan signal, the transistor N1 is enabled and the high voltage scan signal can be transmitted to the test line T1 through the transistor N1. When the 2nd gate line G2 carries a high voltage scan signal, the transistor N2 is enabled and the high voltage scan signal can be transmitted to the test line T1 through the transistor N2. When the 3rd gate line G3 carries a high voltage scan signal, the transistor N3 is enabled and the high voltage scan signal can be transmitted to the test line T1 through the transistor N3. And so on, when the Nth gate line GN carries a high voltage scan signal, the transistor NN is enabled and the high voltage scan signal can be transmitted to the test line T1 through the transistor NN.
Since the test pad 105 is coupled to the test line T1, by observing the scan signal on the test pad 105 in each timing interval, the error waveform of the scan signal and the corresponding failed stage of the gate driving unit can be identified. For instance, when the Kth gate driving unit GDK is inspected, by observing the scan signal on the test pad 105 in the Kth timing interval, if the signal waveform of the scan signal in the Kth timing interval shows error (i.e., The error signal waveform includes the amplitude of signal wave being in error or the pulse width of signal wave being in error), the Kth gate driving unit GDK can be identified as the failed stage of the gate driving unit.
Please refer to
In this embodiment, a first inspection circuit 210 is located between the first gate driving circuit 200 and the pixel array 220. The first inspection circuit 210 includes a first test line T1, a plurality of first transistors NL1, NL2, NL3, . . . NLN/2, and a first test pad 140. The plurality of first transistors NL1, NL2, NL3, . . . NLN/2, can be a plurality of N-type metal-oxide-semiconductor field-effect transistors (N-type MOSFET) . Each first transistor includes a first terminal coupled to the first test line T1, a control terminal coupled to the corresponding odd-ordered gate line of the gate lines G1, G3, G5, . . . , GN-1 with respect to the odd-ordered gate driving units GD1, GD3, GD5, . . . , GDN-1, and a second terminal coupled to the control terminal of the first transistor. The first test pad 140 is coupled to a terminal of the first test line T1. A second inspection circuit 211 is located between the second gate driving circuit 240 and the pixel array 220. The second inspection circuit 211 includes a second test line T2, a plurality of second transistors NR1, NR2, NR3, . . . , NRN/2, and a second test pad 150. The plurality of second transistors NR1, NR2, NR3, . . . , NRN/2 can be a plurality of N-type metal-oxide-semiconductor field-effect transistors (N-type MOSFET) . Each second transistor includes a first terminal coupled to the second test line T2, a control terminal coupled to the corresponding even-ordered gate line of the gate lines G2, G4, G6, . . . , GN with respect to the even-ordered gate driving units GD2, GD4, GD6, . . . , GDN, and a second terminal coupled to the control terminal of the second transistor. The second test pad 150 is coupled to a terminal of the second test line T2.
In other words, in this embodiment, the first terminal of the first transistor NL1 is coupled to the first test line T1. The second terminal and the control terminal of the first transistor NL1 are coupled to the 1st gate line G1. The first terminal of the first transistor NL2 is coupled to the first test line T1. The second terminal and the control terminal of the first transistor NL2 are coupled to the 3rd gate line G3. The first terminal of the first transistor NL3 is coupled to the first test line T1. The second terminal and the control terminal of the first transistor NL3 are coupled to the 5th gate line G5. And so on, the first terminal of the first transistor NLN/2 is coupled to the first test line T1. The second terminal and the control terminal of the first transistor NLN/2 are coupled to the N-1th gate line GN-1. In this embodiment, the first terminal of the second transistor NR1 is coupled to the second test line T2. The second terminal and the control terminal of the second transistor NR1 are coupled to the 2nd gate line G2. The first terminal of the second transistor NR2 is coupled to the second test line T2. The second terminal and the control terminal of the second transistor NR2 are coupled to the 4th gate line G4. The first terminal of the second transistor NR3 is coupled to the second test line T2. The second terminal and the control terminal of the second transistor NR3 are coupled to the 6th gate line G6. And so on, the first terminal of the second transistor NRN/2 is coupled to the second test line T2 . The second terminal and the control terminal of the second transistor NRN/2 are coupled to the Nth gate line GN.
In this embodiment, the pixel array 220 is considered as an N×M array. The plurality of pixels of the pixel array 220 is operated by using N gate lines G1 to GN and M data lines S1 to SM. When the display panel 30 displays the image, the plurality of odd-ordered gate driving units GD1, GD3, GD5, . . . , GDN-1 in the first gate driving circuit 200 sequentially transmits the odd-ordered scan signals to the corresponding plurality of odd-ordered gate lines G1, G3, G5, . . . , GN-1 for sequentially enabling the 1st, 3rd, 5th, . . . , N-1th rows of pixels in the pixel array 220. The plurality of even-ordered gate driving units GD2, GD4, GD6, . . . , GDN in the second gate driving circuit 240 sequentially transmits the even-ordered scan signals to the corresponding plurality of even-ordered gate lines G2, G4, G6 , . . . , GN for sequentially enabling the 2st, 4th, 6th, . . . Nth rows of pixels in the pixel array 220. Then, the image data can be transmitted to the plurality of pixels according to the corresponding data lines S1 to SM.
For example, the 1st gate driving unit GD1 in the first gate driving circuit 200 produces a first high voltage scan signal with unit width of the clock signal waveform in the 1st timing interval of the clock signal and transmits the first high voltage scan signal to the 1st gate line G1 for enabling the 1st row of pixels corresponding to the 1st gate line G1 in the pixel array 220. The 2nd gate driving unit GD2 in the second gate driving circuit 240 produces a second high voltage scan signal with unit width of the clock signal waveform in the 2nd timing interval of the clock signal and transmits the second high voltage scan signal to the 2nd gate line G2 for enabling the 2nd row of pixels corresponding to the 2nd gate line G2 in the pixel array 220. The 3rd gate driving unit GD3 in the first gate driving circuit 200 produces a first high voltage scan signal with unit width of the clock signal waveform in the 3rd timing interval of the clock signal and transmits the first high voltage scan signal to the 3rd gate line G3 for enabling the 3rd row of pixels corresponding to the 3rd gate line G3 in the pixel array 220. The 4th gate driving unit GD4 in the second gate driving circuit 240 produces a second high voltage scan signal with unit width of the clock signal waveform in the 4th timing interval of the clock signal and transmits the second high voltage scan signal to the 4th gate line G4 for enabling the 4th row of pixels corresponding to the 4th gate line G4 in the pixel array 220. And so on, the N-lth gate driving unit GDN-1 in the first gate driving circuit 200 produces a first high voltage scan signal with unit width of the clock signal waveform in the N-1th timing interval of the clock signal and transmits the first high voltage scan signal to the N-lth gate line GN-1 for enabling the N-1th row of pixels corresponding to the N-1th gate line GN-1 in the pixel array 220. The Nth gate driving unit GDN in the second gate driving circuit 240 produces a second high voltage scan signal with unit width of the clock signal waveform in the Nth timing interval of the clock signal and transmits the second high voltage scan signal to the Nth gate line GN for enabling the Nth row of pixels corresponding to the Nth gate line GN in the pixel array 220.
Briefly speaking, the first driving circuit 200 respectively produces the first high voltage scan signals and transmits the first high voltage scan signals to the corresponding odd-ordered gate lines according to the odd-ordered timing intervals of the clock signal. The second driving circuit 240 respectively produces the second high voltage scan signals and transmits the second high voltage scan signals to the corresponding even-ordered gate lines according to the even-ordered timing intervals of the clock signal. Specifically, in this embodiment, since the plurality of gate driving units GD1 to GDN respectively produce the first scan signal and the second scan signal according to the odd-ordered timing intervals and even-ordered timing intervals of the clock signal, no interference (i.e., The interference is caused by pulses overlapping) between the first scan signal and the second scan signal in adjacent intervals occurs, even no RC delay.
When the plurality of gate driving units GD1 to GDN respectively produce the first high voltage scan signals and the second high voltage scan signals, since the control terminals and the second terminals of the plurality of the first transistors NL1, NL2, NL3, . . . , NLN/2 in the first inspection circuit 210 are respectively coupled to the corresponding odd-ordered gate lines G1, G3, G5, . . . , GN-1 and the control terminals and the second terminals of the plurality of the second transistors NR1, NR2, NR3, . . . , NRN/2 in the second inspection circuit 211 are respectively coupled to the corresponding even-ordered gate lines G2, G4, G6, . . . , GN and the control terminals, the first or the second high voltage scan signals enable the corresponding transistors according to the odd-ordered timing intervals of the clock signal or even-ordered timing intervals of the clock signal. Thus, the high voltage scan signals can be transmitted to the first test line T1 coupled to the first transistors NL1, NL2, NL3, . . . , NLN/2 or the second test line T2 coupled to the second transistors NR1, NR2, NR3, . . . , NRN/2 through the second terminals of the transistors.
This means that when the 1st gate line G1 carries the first high voltage scan signal, the first transistor NL1 is enabled and the first high voltage scan signal can be transmitted to the first test line T1 through the first transistor NL1. When the 2nd gate line G2 carries the second high voltage scan signal, the second transistor NR1 is enabled so that the second high voltage scan signal can be transmitted to the second test line T2 through the second transistor NR1. When the 3rd gate line G3 carries the first high voltage scan signal, the first transistor NL2 is enabled so that the first high voltage scan signal can be transmitted to the first test line T1 through the first transistor NL2. When the 4th gate line G4 carries the second high voltage scan signal, the second transistor NR2 is enabled so that the second high voltage scan signal can be transmitted to the second test line T2 through the second transistor NR2. And so on, when the N-1th gate line GN-1 carries the first high voltage scan signal, the first transistor NLN/2 is enabled so that the first high voltage scan signal can be transmitted to the first test line T1 through the first transistor NLN/2. When the Nth gate line GN carries the second high voltage scan signal, the second transistor NRN/2 is enabled so that the second high voltage scan signal can be transmitted to the second test line T2 through the second transistor NRN/2.
Since the first test pad 140 and the second test pad 150 are respectively coupled to the terminal of the first test line T1 and the terminal of the second test line T2, by observing the first scan signal on the first test pad 140 in each odd-ordered timing interval, the error waveform of the first scan signal and the corresponding odd-ordered failed stage of the gate driving unit can be identified. By observing the second scan signal on the second test pad 150 in each even-ordered timing interval, the error waveform of the second scan signal and the corresponding even-ordered failed stage of the gate driving unit can be identified.
For example, when the Pth gate driving unit GDP is inspected where the positive integer P is odd, by observing the waveform of the first scan signal on the first test pad 140 in the Pth timing interval, if the waveform of the first scan signal in the Pth timing interval is in error, the Pth gate driving unit GDP can be identified as the failed stage of the gate driving unit . When the Qth gate driving unit GDQ is inspected where the positive integer Q is even, by observing the waveform of the second scan signal on the second test pad 150 in the Qth timing interval, if the waveform of the second scan signal in the Qth timing interval is in error, the Qth gate driving unit GDQ can be identified as the failed stage of the gate driving unit.
To sum up the present invention, a display panel having the capability for detecting the failed stages of the gate driving circuit is developed. In the display panel, since the control terminals of the transistors in the inspection circuit are respectively coupled to the gate lines, when the gate line carries a high voltage scan signal, the transistor is enabled. Further, since the second terminals of the transistors are respectively coupled to the gate lines, when the corresponding transistor is enabled, the high voltage scan signal can be transmitted to the test pad coupled to the first terminal of the corresponding transistor. Thus, high voltage scan signal in each timing interval in the display panel can be detected by observing the signal waveform on the test pad. As a result, the display panel of the present invention can inspect the gate driving circuit and can identify the failed stage of the gate driving unit in the gate driving circuit, thereby improving the image display quality.
| Number | Date | Country | Kind |
|---|---|---|---|
| 103204932 | Mar 2014 | TW | national |
