Patent Application
20230165059
The present invention relates to display technology, more particularly, to a display panel.
Organic Light Emitting Diode (OLED) display is one of the hotspots in the field of flat panel display research today. Unlike Thin Film Transistor-Liquid Crystal Display (TFT-LCD), which uses a stable voltage to control brightness, OLED is driven by a driving current required to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units configured with pixel-driving circuits arranged in multiple rows and columns. Each pixel-driving circuit includes a driving transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When the row in which the pixel unit is gated is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied from the data line to the driving transistor via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to an OLED device. The OLED device is driven to emit light of a corresponding brightness.
In one aspect, the present disclosure provides a display panel, comprising a base substrate, a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit; wherein the respective pixel driving circuit comprises a third transistor; and a storage capacitor comprising a first capacitor electrode in a first conductive layer and a second capacitor electrode in a second conductor layer; wherein the second conductive layer is on a side of the first conductive layer away from the base substrate; the second capacitor electrode comprises an extension extending away from an electrode main body of the second capacitor electrode; and an orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate.
Optionally, the third transistor comprises a first gate electrode and a second gate electrode; an orthographic projection of the first gate electrode on the base substrate overlaps with an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate; an orthographic projection of the second gate electrode on the base substrate overlaps with an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate; the active layer of the third transistor further comprises a portion connecting the first channel part and the second channel part; and the orthographic projection of the extension on a base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel part and the second channel part on the base substrate.
Optionally, the display panel further comprises a first signal line layer on a side of the storage capacitor away from the base substrate; wherein multiple second capacitor electrodes respectively from multiple pixel driving circuits are sequentially connected to each other along a first direction; the first signal line layer comprises a plurality of first high voltage signal lines respectively along a first direction; and a respective one of the plurality of first high voltage signal lines is connected to the second capacitor electrode.
Optionally, the extension comprises a first extension part along a second direction and a second extension part along a first direction; the first extension part connects the second extension part with the electrode main body of the second capacitor electrode; and an orthographic projection of the second extension part on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate.
Optionally, the second extension part comprises a shielding portion and a non-shielding portion; an orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; an orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; and a line width of the shielding portion is greater than a line width of the non-shielding portion.
Optionally, the respective pixel driving circuit further comprises a driving transistor, and a node connecting line connecting a drain electrode of the third transistor with a gate electrode of the driving transistor; wherein the drain electrode of the third transistor is connected to the gate electrode of the driving transistor; a source electrode of the third transistor is connected to a drain electrode of the driving transistor; and an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line.
Optionally, the display panel further comprises a plurality of data lines; wherein the first extension part is between the node connecting line and a respective data line of the plurality of data lines.
Optionally, the display panel further comprises a plurality of gate lines; wherein a respective gate line of the plurality of gate lines comprises a plurality of metal blocks spaced apart from each other in a first conductive layer, and a metal line along a first direction in a first signal line layer, the metal line along the first direction being connected to the plurality of metal blocks through vias, respectively.
Optionally, a respective metal block of the plurality of metal blocks has a L shape; an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a first metal portion of the respective metal block of the plurality of metal blocks on the base substrate; an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a second metal portion of the respective metal block of the plurality of metal blocks on the base substrate; and the first metal portion and the second metal portion are a first gate electrode and a second gate electrode of the third transistor.
Optionally, the display panel further comprises a plurality of first reset signal lines respectively along a first direction in a semiconductor material layer; and a plurality of second reset signal lines respectively along a second direction in a second signal line layer; wherein the plurality of first reset signal lines respectively cross over the plurality of second reset signal lines; a respective one of the plurality of first reset signal lines is connected to at least multiple ones of the plurality of second reset signal lines through vias; and a respective one of the plurality of second reset signal lines is connected to at least multiple ones of the plurality of first reset signal lines through vias.
Optionally, the display panel further comprises a plurality of second low voltage signal lines respectively along a second direction in a second signal line layer; wherein the plurality of second low voltage signal lines are electrically connected to a cathode of a light emitting element.
Optionally, the display panel further comprises a plurality of first high voltage signal lines respectively extending along the first direction in a first signal line layer; a plurality of second high voltage signal lines respectively extending along a second direction in a second signal line layer; wherein the plurality of first high voltage signal lines respectively cross over the plurality of second high voltage signal lines; a respective one of the plurality of first high voltage signal lines is connected to at least multiple ones of the plurality of second high voltage signal lines through vias; and a respective one of the plurality of second high voltage signal lines is connected to at least multiple ones of the plurality of first high voltage signal lines through vias.
Optionally, a respective one of the plurality of first high voltage signal lines comprises a main body extending along a first direction; a first protrusion protruding away from the main body along a second direction, and a second protrusion protruding away from the first protrusion along the second direction; wherein the second protrusion connects to the main body through the first protrusion; and the second protrusion is a portion of the respective one of the plurality of second high voltage signal line where the respective one of the plurality of second high voltage signal line is connected to a respective one of the plurality of first high voltage signal lines through one or more vias.
Optionally, the respective pixel driving circuit further comprises a driving transistor, and a node connecting line connecting a drain electrode of the third transistor with a gate electrode of the driving transistor; wherein the drain electrode of the third transistor is connected to the gate electrode of the driving transistor; a source electrode of the third transistor is connected to a drain electrode of the driving transistor; and an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate covers an orthographic projection of the node connecting line on the base substrate.
Optionally, an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate.
Optionally, the display panel comprises a plurality of light emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements; wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area; the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer; the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines.
Optionally, the interconnected first voltage supply network comprises a plurality of first-first voltage signal lines respectively along a first direction; and a plurality of second-first voltage signal lines respectively along a second direction; wherein the plurality of first-first voltage signal lines respectively cross over the plurality of second-first voltage signal lines.
Optionally, the interconnected first voltage supply network comprises a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines.
Optionally, a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines; and a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines.
Optionally, the plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines interconnect through first vias respectively extending through the planarization layer, at least some of the first vias being in the display area; a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines respectively through multiple first vias extending through the planarization layer; and a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines respectively through multiple first vias extending through the planarization layer.
In another aspect, the present disclosure provides a display panel, comprising a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit; wherein the display panel comprises a plurality of light emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements; wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area; the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer; the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines.
Optionally, the interconnected first voltage supply network comprises a plurality of first-first voltage signal lines respectively along a first direction; and a plurality of second-first voltage signal lines respectively along a second direction; wherein the plurality of first-first voltage signal lines respectively cross over the plurality of second-first voltage signal lines.
Optionally, the interconnected first voltage supply network comprises a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines.
Optionally, a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines; and a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines.
Optionally, the plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines interconnect through first vias respectively extending through the planarization layer, at least some of the first vias being in the display area; a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines respectively through multiple first vias extending through the planarization layer; and a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines respectively through multiple first vias extending through the planarization layer.
Optionally, the display panel further comprises a gate-on-array circuit in a peripheral area of the display panel; wherein the interconnected first voltage supply network comprises a first peripheral first voltage line in the peripheral area on a first side of the display panel; and an orthographic projection of the first peripheral first voltage line on a base substrate at least partially overlaps with an orthographic projection of the gate-on-array circuit on the base substrate.
Optionally, the display panel further comprises an anode metal layer on a side of the first peripheral first voltage line away from the gate-on-array circuit; and a cathode layer on a side of the anode metal layer away from the first peripheral first voltage line; wherein the cathode layer is connected to the anode metal layer through one or more first peripheral vias in the peripheral area and extending through a third planarization layer, the anode metal layer is connected to the first peripheral first voltage line through one or more second peripheral vias in the peripheral area and extending through a second planarization layer, thereby providing the first voltage signal to the cathodes of the plurality of light emitting elements; the one or more first peripheral vias connecting the cathode layer and the anode metal layer, and the one or more second peripheral vias connecting the anode metal layer and the interconnected first voltage supply network are limited in the peripheral area, and absent in the display area; and the first peripheral first voltage line and the anode metal layer connected to the first peripheral first voltage line respectively partially surround a display area.
Optionally, the display panel further comprises an interconnected reset signal supply network configured to provide a reset signal to a plurality of pixel driving circuits; wherein the interconnected reset signal supply network comprises signal lines in a display area of the display panel.
Optionally, the interconnected reset signal supply network comprises a plurality of first reset signal lines respectively along a first direction; and a plurality of second reset signal lines respectively along a second direction; wherein the plurality of first reset signal lines respectively cross over the plurality of second reset signal lines.
Optionally, a respective one of the plurality of first reset signal lines is connected to at least multiple ones of the plurality of second reset signal lines; and a respective one of the plurality of second reset signal lines is connected to at least multiple ones of the plurality of first reset signal lines.
Optionally, a minimal distance between a respective second reset signal line of the plurality of second reset signal lines and a respective second-first voltage signal line of the plurality of second-first voltage signal lines that is most adjacent to the respective second reset signal line is less than a minimal distance between the respective second reset signal line and a respective data line of a plurality of data line that is most adjacent to the respective second reset signal line.
Optionally, a total of three data lines and a total of one second-first voltage signal line are between two most adjacent second reset signal lines of the plurality of second reset signal lines.
Optionally, the display panel comprises a base substrate; a semiconductor material layer on the base substrate; a planarization layer on a side of the semiconductor material layer away from the base substrate; a second signal line layer on a side of the planarization layer away from the semiconductor material layer; wherein the display panel further comprises an interconnected reset signal supply network configured to provide a reset signal to a plurality of pixel driving circuits; the interconnected reset signal supply network comprises a plurality of first reset signal lines respectively along a first direction and a plurality of second reset signal lines respectively along a second direction; and the semiconductor material layer comprises the plurality of first reset signal lines, and the second signal line layer comprises the plurality of second reset signal lines.
Optionally, the plurality of first reset signal lines and the plurality of second reset signal lines interconnect through second vias respectively extending through at least the planarization layer; wherein the display panel further comprises a gate insulating layer on a side of the semiconductor material layer away from the base substrate; an insulating layer on a side of the gate insulating layer away from the semiconductor material layer; and an inter-layer dielectric layer a side of the insulating layer away from the gate insulating layer; wherein the planarization layer is on a side of the inter-layer dielectric layer away from the insulating layer; and the plurality of first reset signal lines and the plurality of second reset signal lines interconnect through second vias, a respective second via extending through the planarization layer, the inter-layer dielectric layer, the insulating layer, and the gate insulating layer.
Optionally, a respective one of the plurality of first reset signal lines is connected to at least multiple ones of the plurality of second reset signal lines respectively through multiple second vias extending through at least the planarization layer; and a respective one of the plurality of second reset signal lines is connected to at least multiple ones of the plurality of first reset signal lines respectively through multiple second vias extending through at least the planarization layer.
Optionally, the plurality of first reset signal lines comprise a semiconductor material; the plurality of second reset signal lines comprise a metallic material; and the plurality of first reset signal lines and at least active layers of a plurality of thin film transistors are in the semiconductor material layer, and comprise a same semiconductor material.
Optionally, the display panel further comprises an interconnected second voltage supply network configured to provide a second voltage signal to a plurality of pixel driving circuits; wherein the interconnected second voltage supply network comprises a plurality of first-second voltage signal lines respectively along a first direction; and a plurality of second-second voltage signal lines respectively along a second direction; wherein the plurality of first-second voltage signal lines respectively cross over the plurality of second-second voltage signal lines.
Optionally, a respective one of the plurality of first-second voltage signal lines is connected to at least multiple ones of the plurality of second-second voltage signal lines; and a respective one of the plurality of second-second voltage signal lines is connected to at least multiple ones of the plurality of first-second voltage signal lines.
Optionally, the display panel comprises a base substrate; a first signal line layer on the base substrate; a planarization layer on a side of the first signal line layer away from the base substrate; a second signal line layer on a side of the planarization layer away from the first signal line layer; wherein the interconnected second voltage supply network comprises a plurality of first-second voltage signal lines respectively along a first direction and a plurality of second-second voltage signal lines respectively along a second direction; wherein the first signal line layer comprises the plurality of first-second voltage signal lines, and the second signal line layer comprises the plurality of second-second voltage signal lines.
Optionally, the plurality of first-second voltage signal lines and the plurality of second-second voltage signal lines interconnect through third vias respectively extending through the planarization layer; a respective one of the plurality of first-second voltage signal lines is connected to at least multiple ones of the plurality of second-second voltage signal lines respectively through multiple third vias extending through the planarization layer; and a respective one of the plurality of second-second voltage signal lines is connected to at least multiple ones of the plurality of first-second voltage signal lines respectively through multiple third vias extending through the planarization layer.
Optionally, a respective one of a plurality of first-second voltage signal lines comprises a main body extending along a first direction; a first protrusion protruding away from the main body along a second direction, and a second protrusion protruding away from the first protrusion along the second direction; wherein the second protrusion connects to the main body through the first protrusion; the first protrusion is a portion of the respective one of the plurality of first-second voltage signal lines where the respective one of a plurality of first-second voltage signal lines connects to a second capacitor electrode; and the second protrusion is a portion of the respective one of the plurality of first-second voltage signal lines where the respective one of the plurality of first-second voltage signal lines connects to a source electrode of a fourth transistor of a respective pixel driving circuit, a drain electrode of the fourth transistor being connected to a source electrode of a driving transistor.
Optionally, the display panel further comprises a plurality of second-second voltage signal lines at least partially in the display area; and a peripheral second voltage signal line in the peripheral area on a second side of the display panel; wherein the interconnected first voltage supply network comprises a plurality of first-first voltage signal lines and a plurality of second-first voltage signal lines at least partially in the display area; and a second peripheral first voltage signal line and a third peripheral first voltage signal line in the peripheral area on the second side of the display panel; wherein one or more of the plurality of second-second voltage signal lines are connected to the peripheral second voltage signal line; one or more of the plurality of second-first voltage signal lines are connected to the second peripheral first voltage signal line; the second peripheral first voltage signal line and the third peripheral first voltage signal line are connected to each other through a plurality of bridges; the plurality of first-first voltage signal lines, the peripheral second voltage signal line, and the plurality of bridges are in a first signal line layer; the plurality of second-second voltage signal lines, the second peripheral first voltage signal line are in a second signal line layer; and the third peripheral first voltage signal line comprise a first sub-layer in the first signal line layer and a second sub-layer in the second signal line layer.
Optionally, the display panel further comprises a plurality of gate lines; wherein a respective gate line of the plurality of gate lines comprises a plurality of metal blocks spaced apart from each other in a first conductive layer, and a metal line along a first direction in the first signal line layer, the signal line along the first direction being connected to the plurality of metal blocks, respectively.
Optionally, the display panel further comprises a plurality of first reset control signal line and a plurality of second reset control signal lines; a respective first reset control signal line and a respective second reset control signal line are respectively configured to reset a gate electrode of a driving transistor and an anode of a respective light emitting element; the respective first reset control signal line comprises a plurality of first metal blocks spaced apart from each other in a first conductive layer, and a first metal line along a first direction in the first signal line layer, the first metal line along the first direction being connected to the plurality of first metal blocks, respectively; and the respective second reset control signal line comprises a plurality of second metal blocks spaced apart from each other in the first conductive layer, and a second metal line along the first direction in the first signal line layer, the second metal line along the first direction being connected to the plurality of second metal blocks, respectively.
Optionally, a respective first-first voltage signal line of a plurality of first-first voltage signal lines comprises a first linear portion, a second linear portion, and a connecting portion connecting the first linear portion and the second linear portion; a virtual extension of the first linear portion crosses over the plurality of first metal blocks of the respective first reset control signal line; and an orthographic projection of the second linear portion on a base substrate is spaced apart from orthographic projections the plurality of first metal blocks on the base substrate.
Optionally, the display panel further comprises a second capacitor electrode of a storage capacitor in a second conductive layer; the second capacitor electrode comprises an extension extending away from an electrode main body of the second capacitor electrode; an orthographic projection of the extension on a base substrate at least partially overlaps with an orthographic projection of an active layer of a third transistor of the respective pixel driving circuit on the base substrate; and a portion of the extension is between a first node of the respective pixel driving circuit and a respective data line, configured to prevent interference from signals passing through the respective data line to the first node, the first node being configured to have a same voltage level as a gate electrode of a driving transistor.
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention.
The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
The present disclosure provides, inter alia, a display panel that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a display panel including a plurality of subpixels. A respective subpixel includes a respective light emitting element and a respective pixel driving circuit. In some embodiments, the display panel includes a plurality of light emitting elements and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements. Optionally, the interconnected first voltage supply network includes signal lines in a display area of the display panel. The display area is at least partially surrounded by a peripheral area. The signal lines include a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer. The display panel further includes a planarization layer between the first signal line layer and the second signal line layer. The plurality of first signal lines are electrically connected to the plurality of second signal lines. In one example, a first voltage signal line is a low voltage signal line, and a second voltage signal line is a high voltage signal line.
As used herein, the term “display area” refers to an area of the display panel where an image is actually displayed. Optionally, the display area may include both a subpixel region and an inter-subpixel region. A subpixel region refers to a light emission region of a subpixel, such as a region corresponding to a pixel electrode in a liquid crystal display or a region corresponding to a light emissive layer in an organic light emitting display. An inter-subpixel region refers to a region between adjacent subpixel regions, such as a region corresponding to a black matrix in a liquid crystal display or a region corresponding a pixel definition layer in an organic light emitting display. Optionally, the inter-subpixel region is a region between adjacent subpixel regions in a same pixel. Optionally, the inter-subpixel region is a region between two adjacent subpixel regions from two adjacent pixels.
As used herein the term “peripheral area” refers to an area of a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display panel, non-transparent or opaque components of the display panel (e.g., battery, printed circuit board, metal frame), can be disposed in the peripheral area rather than in the display areas.
Various appropriate light emitting elements may be used in the present display panel. Examples of appropriate light emitting elements include organic light emitting diodes, quantum dots light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.
In some embodiments, the interconnected low voltage supply network VSSN includes a plurality of first low voltage signal lines Vss1 respectively along a first direction DR1; and a plurality of second low voltage signal lines Vss2 respectively along a second direction DR2. The first direction DR1 and the second direction DR2 are different from each other. The plurality of first low voltage signal lines Vss1 respectively cross over the plurality of second low voltage signal lines Vss2.
The display panel in some embodiments includes a plurality of subpixels. In some embodiments, the plurality of subpixels includes a respective first subpixel, a respective second subpixel, a respective third subpixel, and a respective fourth subpixel. Optionally, a respective pixel of the display panel includes the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel. The plurality of subpixels in the display panel are arranged in an array. In one example, the array of the plurality of subpixels includes a S1-S2-S3-S4 format repeating array, in which S1 stands for the respective first subpixel, S2 stands for the respective second subpixel, S3 stands for the respective third subpixel, and S4 stands for the respective fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, C3 stands for the respective third subpixel of a third color, and C4 stands for the respective fourth subpixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2′ format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, C3 stands for the respective third subpixel of a third color, and C2′ stands for the respective fourth subpixel of the second color. In another example, the C1-C2-C3-C2′ format is a R-G-B-G format, in which the respective first subpixel is a red subpixel, the respective second subpixel is a green subpixel, the respective third subpixel is a blue subpixel, and the respective fourth subpixel is a green subpixel.
In some embodiments, a minimum repeating unit of the plurality of subpixels of the display panel includes the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel. Optionally, each of the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel, includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td.
Various appropriate pixel driving circuits may be used in the present display panel. Examples of appropriate driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, the respective one of the plurality of pixel driving circuits is an 7T1C driving circuit. Various appropriate light emitting elements may be used in the present display panel. Examples of appropriate light emitting elements include organic light emitting diodes, quantum dots light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.
Referring to
The pixel driving circuit further include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the source electrode of the third transistor T3. The second node N2 is connected to the drain electrode of the fourth transistor T4, the drain electrode of the second transistor T2, and the source electrode of the driving transistor Td. The third node N3 is connected to the drain electrode of the driving transistor Td, the drain electrode of the third transistor T3, and the source electrode of the fifth transistor T5. The fourth node N4 is connected to the drain electrode of the fifth transistor T5, the drain electrode of the sixth transistor T6, the drain electrode of the sensing transistor Ts, and the anode of the light emitting element LE.
Referring to
Referring to
As used herein, the active layer refers to a component of the transistor comprising at least a portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a gate electrode on the base substrate. As used herein, a source electrode refers to a component of the transistor connected to one side of the active layer, and a drain electrode refers to a component of the transistor connected to another side of the active layer. In the context of a double-gate type transistor (for example, the third transistor T3), the active layer refers to a component of the transistor comprising a first portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a first gate on the base substrate, a second portion of the semiconductor material layer whose orthographic projection on the base substrate overlaps with an orthographic projection of a second gate on the base substrate, and a third portion between the first portion and the second portion. In the context of a double-gate type transistor, a source electrode refers to a component of the transistor connected to a side of the first portion distal to the third portion, and a drain electrode refers to a component of the transistor connected to a side of the second portion distal to the third portion.
Referring to
As used herein, the term “same layer” refers to the relationship between the layers simultaneously formed in the same step. In one example, the plurality of light emitting control signal lines em and the first capacitor electrode Ce1 are in a same layer when they are formed as a result of one or more steps of a same patterning process performed in a same layer of material. In another example, the plurality of light emitting control signal lines em and the first capacitor electrode Ce1 can be formed in a same layer by simultaneously performing the step of forming the plurality of light emitting control signal lines em, and the step of forming the first capacitor electrode Ce1. The term “same layer” does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.
In some embodiments, a respective gate line of the plurality of gate lines comprises a plurality of metal blocks (e.g., G3 in
In some embodiments, referring to
Referring to
Referring to
In some embodiments, the respective first reset control signal line rst1 include a plurality of first metal blocks spaced apart from each other in a first conductive layer, and a first metal line along a first direction in the first signal line layer, the first metal line along the first direction being connected to the plurality of first metal blocks, respectively. In some embodiments, the respective second reset control signal line comprises a plurality of second metal blocks spaced apart from each other in the first conductive layer, and a second metal line along the first direction in the first signal line layer, the second metal line along the first direction being connected to the plurality of second metal blocks, respectively.
In some embodiments, a respective first low voltage signal line of a plurality of first low voltage signal lines Vss1 includes a first linear portion, a second linear portion, and a connecting portion connecting the first linear portion and the second linear portion. A virtual extension of the first linear portion crosses over the plurality of first metal blocks (e.g., G1 in
Referring to
Referring to
Referring to
In some embodiments, referring to
By having the extension E, the active layer of the third transistor can be protected from irradiation. Because the extension E is part of the second capacitor electrode, the extension E has a stable voltage level, obviating the need to electrically connecting the extension E to a signal line having a stable voltage level.
Referring to
In some embodiments, the extension E includes a first extension part along a first direction DR1 and a second extension part along a second direction DR2. The first extension part connects the second extension part with the electrode main body emb of the second capacitor electrode Ce2. In some embodiments, an orthographic projection of the second extension part on the base substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 of the respective pixel driving circuit on the base substrate.
In some embodiments, the second extension part includes a shielding portion and a non-shielding portion. An orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 of the respective pixel driving circuit on the base substrate. An orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer ACT3 of the third transistor T3 of the respective pixel driving circuit on the base substrate. A line width of the shielding portion is greater than a line width of the non-shielding portion, ensuring that the active layer ACT3 of the third transistor T3 of the respective pixel driving circuit is shielded.
In some embodiments, an orthographic projection of the first extension part on the base substrate at least partially overlaps with an orthographic projection of the node connecting line Cln on the base substrate. The first extension part is between the node connecting line Cln and a respective data line of the plurality of data lines dl. The first extension part between the node connecting line Cln and the respective data line is configured to prevent interference to the first node N1 from signals passing through the respective data line.
In some embodiments, an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line. The first extension part is configured to prevent interference to the first node N1 from signals transmitting along the first direction.
In some embodiments, an orthographic projection of the respective one of the plurality of second high voltage signal lines Vdd2 on the base substrate covers an orthographic projection of the node connecting line Cln on the base substrate. By having the respective one of the plurality of second high voltage signal lines Vdd2 shielding the node connecting line Cln, a voltage level at the node N1 can be stabilized because a constant voltage level is provided to the respective one of the plurality of second high voltage signal lines Vdd2.
In some embodiments, an orthographic projection of the respective one of the plurality of second high voltage signal lines Vdd2 on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor T3 on the base substrate. By having the respective one of the plurality of second high voltage signal lines Vdd2 shielding the at least one gate electrode of the third transistor T3, a voltage level at the node N1 can be further stabilized.
Optionally, the plurality of first reset signal lines Vint1 include a semiconductor material; and the plurality of second reset signal lines Vint2 include a metallic material. Optionally, the plurality of first reset signal lines Vint1 and at least active layers (e.g., ACTd, and ACT1 to ACT6) of a plurality of thin film transistors (e.g., Td, and T1 to T6) are in the semiconductor material layer SML, and include a same semiconductor material.
Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be disposed in the first conductive layer. Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be disposed in the first signal line layer. Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be disposed in the second conductive layer. Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be disposed in the second signal line layer. Alternatively, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are in a same layer, interconnecting with each other to form a network.
Referring to
In some embodiments, referring to
Referring to
In some embodiments, the cathode layer CDL is a unitary cathode layer extending substantially throughout the display panel and functions as cathodes for the plurality of light emitting elements. Optionally, the one or more vias connecting the cathode layer CDL and the anode metal layer AML are limited in the peripheral area PA, and absent in the display area DA. The cathode layer CDL is connected to the interconnected low voltage supply network VSSN only through the anode metal layer AML.
In the present display panel, the low voltage line shares a same space as the gate-on-array circuit GOA. The display panel can be made with a very narrow bezel. In one example, the present display panel has a bezel width on the first side S1 (or the side opposite to the first side S1) of approximately 1.5 mm, as compared to 2.5 mm in a related display panel.
Moreover, in the present display panel, the connection between the low voltage line and the cathode layer CDL (through the anode metal layer) may be made exclusively in the peripheral area PA (e.g., in the GOA region), obviating the need of making vias (or any process at all) in the display area DA to connect the low voltage line and the cathode layer CDL. The display panel can be fabricated with much less complexity, significantly lowering occurrence of defects in the display panel.
The inventors of the present disclosure discover that, surprisingly and unexpectedly, the implementation of the interconnected low voltage supply network dramatically reduces a degree of voltage drop of the low voltage signal (e.g., the VSS signal) throughout the display panel.
To accommodate the implementation of the interconnected network in the present display panel, the layers and signal lines in the peripheral area have adopted a novel and unique structure that is advantageous in further reducing the bezel width, improving voltage uniformity throughout the display panel, and minimizing occurrence of defects in the display panel.
Referring to
Various appropriate implementations of the interconnected low voltage supply network may be practiced according to the present disclosure.
In some embodiments, the plurality of first low voltage signal lines Vss1 form a sub-network whereas the plurality of second low voltage signal lines Vss2 do not form a sub-network. In some embodiments, the plurality of second low voltage signal lines Vss2 form a sub-network whereas the plurality of first low voltage signal lines Vss1 do not form a sub-network.
In another aspect, the present invention provides a display apparatus, including the display panel described herein or fabricated by a method described herein, and one or more integrated circuits connected to the display panel. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Optionally, the display apparatus is an organic light emitting diode display apparatus. Optionally, the display apparatus is a liquid crystal display apparatus.
In another aspect, the present disclosure provides a method of fabricating a display panel. In some embodiments, the method includes forming a plurality of light emitting elements; and forming an interconnected low voltage supply network configured to provide a low voltage signal to cathodes of the plurality of light emitting elements. Optionally, forming the interconnected low voltage supply network includes forming signal lines in a display area of the display panel.
The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first”, “second”, etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
This application is a continuation of U.S. application Ser. No. 17/764,479, filed Jun. 25, 2021, which a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2021/102249, filed Jun. 25, 2021. Each of the forgoing applications is herein incorporated by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17764479 | Jan 0001 | US |
| Child | 18152438 | US |
