This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 103123658 filed in Taiwan, Republic of China on Jul. 9, 2014, the entire contents of which are hereby incorporated by reference.
1. Field of Invention
The invention relates to a display panel and, in particular, to a display panel that can reduce the Mura diffusing from the border region to the display region to affect the quality of the image.
2. Related Art
With the progress of technologies, flat display devices have been widely applied to various kinds of fields. Especially, liquid crystal display (LCD) devices, having advantages such as compact structure, low power consumption, less weight and less radiation, gradually take the place of cathode ray tube (CRT) display devices, and are widely applied to various electronic products, such as mobile phones, portable multimedia devices, notebooks, LCD TVs and LCD screens.
A conventional liquid crystal display (LCD) apparatus mainly includes an LCD panel and a backlight module. The LCD panel mainly includes a thin film transistor (TFT) substrate, a color filter (CF) substrate and a liquid crystal layer disposed between the two substrates. The conventional manufacturing process of the LCD panel includes the steps of: disposing a sealant on the edges of a TFT substrate for example; disposing the liquid crystal within the sealant; making the TFT substrate and a CF substrate adhere to each other in a vacuum environment; and curing the sealant to obtain an LCD panel.
When the liquid crystal is injected, the liquid crystal will flow to the edges of the panel. However, because the sealant has not been cured, the chemical reaction generated between the liquid crystal molecules and the sealant will cause the dissolution of the sealant. In the worse case, the liquid crystal will be polluted, and therefore the Mura will be generated in the border region of the display device.
Therefore, it is an important subject to provide a display panel that can reduce the Mura occurring in the border region.
In view of the foregoing subject, an objective of the invention is to provide a display panel that can reduce the Mura occurring in the border region.
To achieve the above objective, a display panel according to the invention comprises a first substrate, a second substrate disposed opposite the first substrate, a liquid crystal layer, a sealant, at least a spacer, a first alignment layer and a second alignment layer. The liquid crystal layer is disposed between the first substrate and the second substrate. The sealant surrounds the liquid crystal layer. The spacer is disposed within the sealant. The first alignment layer is disposed on the first substrate. The second alignment layer is disposed on the second substrate. The first alignment layer or the second alignment layer at least covers partial surface of the spacer.
In one embodiment, the first alignment layer covers the entire surface of the spacer and is extended to an edge of the first substrate.
In one embodiment, the second alignment layer covers the entire surface of the spacer and is extended to an edge of the second substrate.
In one embodiment, the display panel further comprises a first transparent conductive layer. The first transparent conductive layer is disposed on the first substrate and extended to an edge of the first substrate. The spacer is disposed on the first transparent conductive layer.
In one embodiment, the display panel further comprises a protective layer. The protective layer is disposed on the second substrate and comprises at least a recess corresponding to the sealant.
In one embodiment, the recess is disposed within the sealant or disposed partially within the sealant and partially outside the sealant.
In one embodiment, the display panel further comprises a second transparent conductive layer disposed on the protective layer. The second alignment layer is disposed on the second transparent conductive layer and extended to cover the recess.
In one embodiment, the second transparent conductive layer is disposed on the protective layer that is disposed within the sealant, and the spacer is disposed on the second transparent conductive layer.
In one embodiment, the spacer is disposed corresponding to the protective layer.
In one embodiment, the display panel further comprises a light blocking layer disposed on the first substrate and comprising at least a recess corresponding to the sealant. The recess is disposed within the sealant or disposed partially within the sealant and partially outside the sealant.
As mentioned above, in the display panel of the invention, the spacer is disposed within the sealant, the first alignment layer and the second alignment layer are extended to within the sealant, and the first alignment layer or the second alignment layer at least covers the partial surface of the spacer. In comparison with the conventional art, the spacer, first alignment layer and second alignment layer disposed in this invention can lower down the flow rate of the liquid crystal flowing to the sealant. Thereby, the total time of the chemical reaction between the liquid crystal molecules and the sealant can be reduced. Therefore, the Mura occurring in the border region and diffusing to the display region to affect the quality of the image of the display panel can be reduced.
The invention will become more fully understood from the detailed description and accompanying drawings, which are given for illustration only, and thus are not limitative of the present invention, and wherein:
The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements.
As shown in
The first substrate 11 and the second substrate 12 are disposed oppositely. The first substrate 11 or the second substrate 12 can be made by transparent material, such as glass, quartz or the like, plastic material, rubber, fiberglass or other polymer materials. Otherwise, the first substrate 11 or the second substrate 12 can be made by opaque material and can be a metal-fiberglass composite board, metal-ceramic composite board, printed circuit board or others. In this embodiment, the substrate 11 and the second substrate 12 are both made by transparent glass for example.
The sealant 13 is disposed between the first substrate 11 and second substrate 12 and surrounds the liquid crystal layer (comprising liquid crystal molecules). Herein, the sealant 13 is disposed on and seals the periphery of the first substrate 11 and second substrate 12. The sealant 13 can be a heat-curing adhesive, photo-curing adhesive or their combination. Herein for example, the sealant 13 is a photo-curing adhesive (such as UV adhesive) and is formed on the periphery of the first substrate 11 and second substrate 12 in a coating manner under the atmosphere. The sealant 13, the first substrate 11 and the second substrate 12 can form an accommodating space (not shown) for the liquid crystal so that the liquid crystal molecules LC can be disposed in the accommodating space. That is, the accommodating space is the space between the first substrate and the second substrate and surrounded by the sealant 13, and the liquid crystal molecules, the wires and the thin film transistors area are disposed within the accommodating space. Herein for example, the liquid crystal molecules LC are formed by the ODF (one drop filling) process and disposed within the region formed by the sealant 13.
The spacer 14 is disposed between the first substrate 11 and the second substrate 12 and within the sealant 13. Herein for example, two spacers 14 are disposed on the first substrate 11 and within the sealant 13. The material of the spacer 14 can include resin, silicate, fiberglass or other photosensitive photoresist materials. As shown in
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The light blocking layer 17 is disposed on the first substrate 11 and corresponding to the sealant 13. In this embodiment, in a top view of the first substrate 11, the light blocking layer 17 at least covers the sealant 13 and the spacer 14. The light blocking layer 17 is a black matrix and made by opaque material, such as metal (e.g. chromium, chromium oxide or Cr—O—N compound) or resin. Since the light blocking layer 17 is opaque, an opaque region can be formed on the first substrate 11 to define a transparent region. The display panel 1 can further include a color filter layer (not shown) disposed on the first substrate 11 or the light blocking layer 17. The color filter layer can include a red filter portion, a green filter portion and a blue filter portion. The color filter layer can be made by transparent material, such as pigment or dye. Moreover, the light blocking layer 17 and the color filter layer of this embodiment both can be disposed on the first substrate 11. In another embodiment, the light blocking layer 17 and/or the color filter layer can be disposed on the second substrate 12 so that the second substrate 12 can become a BOA (Black Matrix on array) substrate or a COA (color filter on array) substrate. To be noted, the above structures are just for the illustrative purpose but not for limiting the scope of the invention.
The first transparent conductive layer 18 is disposed on the side of the first substrate 11 facing the second substrate 12 and between the light blocking layer 17 and the first alignment layer 15. Herein, the first transparent conductive layer 18 is extended to the edge of the first substrate 11. The first transparent conductive layer 18 is a transparent conductive layer with the material of ITO or IZO for example, and herein ITO is taken as an example. The first transparent conductive layer 18 can be a common electrode. The display panel 1 of this embodiment is an LCD panel of a vertical switch type. However, in other embodiments, if the display panel 1 is an IPS (in-plane switch) LCD panel, the first transparent conductive layer 18 will be removed from the first substrate 11.
The first alignment layer 15 is disposed on the first substrate 11 and extended to the range of the sealant 13. The first alignment layer 15 or the second alignment layer 16 at least covers a partial surface of the spacer 14. In this embodiment, the spacer 14 is disposed on the first transparent conductive layer 18. The first alignment layer 15 is extended from the accommodating space for the liquid crystal molecules LC to the inside of the sealant 13 and covers the entire surface of the spacer 14. Besides, the first alignment layer 15 is extended to the edge of the first substrate 11 for example.
The protective layer 19 is disposed on the second substrate 12. The material of the protective layer 19 is, for example but not limited to, SiNx or SiOx. Moreover, the protective layer 19 includes at least a recess U corresponding to the sealant 13 (or the light blocking layer 17). The recess U can be disposed within the sealant 13 or disposed partially within the sealant 13 and partially outside the sealant 13. Herein for example, there are two recesses U corresponding to the sealant 13, one of the recesses U is disposed within the sealant 13, and the other is disposed partially within the sealant 13 and partially outside the sealant 13. Furthermore, the spacer 14 of this embodiment is disposed corresponding to the protective layer 19 that is within the sealant 13. However, in other embodiments, the spacer 14 may be disposed corresponding to the recess U. The recess U can elongate the flowing path of the liquid crystal molecules LC to delay the time that the liquid crystal molecules LC reach the sealant 13, and also can increase the contact area between the sealant 13 and the second substrate 12 so as to enhance the adhesion of the sealant 13. In another embodiment, the recess U can be disposed on the first substrate 11 and can be formed by the light blocking layer 17, the first transparent conductive layer 18 or the color filter layer (not shown).
The second transparent conductive layer 20 is disposed on the protective layer 19. The second transparent conductive layer 20 of this embodiment is just disposed in the accommodating space for the liquid crystal molecules LC but not disposed within the sealant 13. The second alignment layer 16 is disposed on the second transparent conductive layer 20 and extended from the accommodating space for the liquid crystal molecules LC to cover the recesses U and further extended to the edge of the second substrate 12. The second transparent conductive layer 20 can be a pixel electrode and disposed between the protective layer 19 and the second alignment layer 16. To be noted, the recess U of this embodiment can be formed by etching the portion of the second transparent conductive layer 20 within the sealant and etching the partial portion of the protective layer 19. In other embodiments, the recess U may be formed by only removing the second transparent conductive layer 20 or by removing the second transparent conductive layer 20 and the partial protective layer 19. In practice, there are other film layers, such as the first metal layer (M1), protective layer, second metal layer (M2), insulating layer or others, disposed between the protective layer 19 and the second substrate 12. In addition to removing the second transparent conductive layer 20 and protective layer 19 to form the recess U, the recess U also can be formed by removing the second transparent conductive layer 20, the protective layer 19 and the film layers between the second transparent conductive layer 20 and the protective layer 19. Moreover, the first alignment layer 15 covering the spacer 14 doesn't contact the second alignment layer 16. However, in another embodiment, the first alignment layer 15 covering the spacer 14 may contact the second alignment layer 16.
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Since the flow rate of the liquid crystal molecules is lower on the alignment layer, in this embodiment as shown in
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Summarily, in the display panel of the invention, the spacer is disposed within the sealant, the first alignment layer and the second alignment layer are extended to within the sealant, and the first alignment layer or the second alignment layer at least covers the partial surface of the spacer. In comparison with the conventional art, the spacer, first alignment layer and second alignment layer disposed in this invention can lower down the flow rate of the liquid crystal flowing to the sealant. Thereby, the time that the liquid crystal molecules LC reach the sealant 13 and the generated chemical reaction can be delayed, and the probability of the liquid crystal molecules LC polluted due to the sealant 13 can be reduced. Therefore, the Mura occurring in the border region and diffusing to the display region to affect the quality of the image of the display panel can be reduced.
Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the invention.
Number | Date | Country | Kind |
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103123658 | Jul 2014 | TW | national |