The present application relates to the field of display technology, in particular to a display panel.
OLED (Organic Light-Emitting Diode) display technology is a new type of display technology, which has gradually attracted people's attention due to its unique advantages such as low power consumption, high saturation, fast response time, and wide viewing angle, occupying a certain position in the field of panel display technology.
In the related art, a pixel driving circuit of an OLED display panel is usually an 8T2C circuit. For the pixel driving circuit, a complementary metal oxide semiconductor (CMOS) gate driving circuit (Gate On Array, GOA) is currently proposed to solve the technical problem of high power consumption of conventional gate driving circuits.
The CMOS GOA circuit needs to generate two kinds of gate driving signals, Nout and Pout, therefore, the gate driving circuit is provided with two buffer parts corresponding to Nout and Pout respectively. Existing signal generation parts are usually located close to a frame. The buffer part is usually disposed close to a display area. Two buffer parts may overlap vertically. In the case that each stage of GOA unit has a limited longitudinal size, a vertical size of the two buffer parts may become smaller. In order to ensure a performance of transistors in Nout and Pout, it is necessary to increase a size of the buffer part in a horizontal direction. It is necessary to reserve a wider area on the frame of the product to set up the gate driving circuit, which is contrary to a narrow frame design of the product.
The present application provides a display panel to improve the technical problem of excessively large frames of existing display devices.
In order to solve the above-mentioned solution, the technical solution provided by the application is as follows:
The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present application and are not intended to limit the present application. In this application, unless stated otherwise, the used orientation words such as “up” and “down” generally refer to up and down in the actual use or working state of the device. Specifically, it is the orientation in the drawings. The “inside” and “outside” refer to the outline of the installation.
In related OLED display panels, a CMOS gate driving circuit is usually used to solve the technical problem of high power consumption of conventional gate driving circuits. The CMOS GOA circuit needs to generate two kinds of gate driving signals, Nout and Pout, therefore, the gate driving circuit is provided with two buffer parts corresponding to Nout and Pout respectively. In contrast, existing signal generation parts are usually located close to the frame. The buffer part is usually disposed close to a display area, resulting in a wider area reserved on the frame of the product to set the buffer part, which is contrary to a narrow frame design of the product. The present application proposes the following solutions based on the above technical problems.
Referring to
In this embodiment, each GOA unit 310 includes a signal generation module 10, a first output module 20, and a second output module 30 disposed along a second direction Y. The first output module 20 is disposed on a side of the signal generation module 10 close to the display unit 200. The first output module 20 is configured to output a first gate driving signal. The second output module 30 is disposed on a side of the signal generation module 10 away from the display unit 200. The second output module 30 is configured to output a second gate driving signal. The first gate driving signal is different from the second gate driving signal.
In this embodiment, in the second direction Y, lengths of the first output module 20 and the second output module 30 are different. The second direction Y is parallel to scan lines of the display panel 100, the first direction X is perpendicular to the second direction Y, and N is a positive integer.
In this embodiment, an angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. Referring to
In the present application, two output modules outputting different gate driving signals and having different lengths are disposed on both sides of the signal generation module 10. This makes the two output modules have sufficient width in the first direction X, which ensures the performance of transistors in the two output modules. This avoids the technical problem of increased frames caused by two output modules being stacked on the same side and realizes a narrow frame design.
It should be noted that the first gate driving signal is a positive pulse signal, and the second gate driving signal is a negative pulse signal. Within a time interval of one frame, the first signal output terminal Nout outputs two positive pulse signals, and the second signal output terminal Pout outputs one negative pulse signal. A pulse width of one positive pulse signal is greater than a pulse width of one negative pulse signal.
The CMOS GOA circuit of the present application needs to output the first gate driving signal and the second gate driving signal. The pulse width of the first gate driving signal is greater than the pulse width of the second gate driving signal. That is, an output load of the first output module 20 is greater than an output load of the second output module 30. Therefore, a width of the first output module 20 of the present application may be greater than a width of the second output module 30, so that the first output module 20 has a larger buffer space and has a larger output load capacity.
It should be noted that a low temperature polysilicon semiconductor has a large leakage current, and a metal oxide transistor has a small leakage current. Therefore, in order to reduce a leakage current of the first output module 20, the present application may set the transistors in the first output module 20 as a combination of low temperature polysilicon transistors and metal oxide transistors.
Referring to
In this application, the first output module 20 is configured as a combination of low temperature polysilicon transistors and metal oxide transistors. The device effect of the first output module 20 is improved by utilizing high mobility of the low temperature polysilicon transistor and low leakage current of the metal oxide transistor.
In this embodiment, the metal oxide semiconductor is also provided in the display area AA, that is, the metal oxide semiconductor in the non-display area NA and the display area AA can be formed in the same photomask process. The patterning density of metal oxide semiconductors in the non-display area NA and the display area AA is different. If the first output transistor T10 is disposed close to the display area AA, the patterning density of the metal oxide semiconductor in the first output transistor T10 may deviate from the design value.
In the present application, the first output transistor T10 having a metal oxide semiconductor is disposed away from the display area AA, and the second output transistor T9 having a low temperature polysilicon semiconductor is disposed close to the display area AA. This makes a pattern of the metal oxide semiconductor of the first output transistor T10 away from a pattern of the metal oxide semiconductor in the display area AA. This prevents a pitch of the pattern of the metal oxide semiconductor in the non-display area NA from deviating from the designed value due to the patterned adjacent arrangement of the metal oxide semiconductor in the display area AA and the non-display area NA.
Referring to
In this embodiment, the first output transistor T10 is a metal oxide transistor. The metal oxide transistor has less leakage current, but mobility of metal oxide transistor is lower. Therefore, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first output transistor T10 in the second direction Y as much as possible in a limited space, so as to improve the driving capability of the first output transistor T10.
In the display panel 100 of the present application, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7. The third output transistor T6 includes a third active part T6A, and the fourth output transistor T7 includes a fourth active part T7A. The third active part T6A and the fourth active part T7A are low temperature polysilicon semiconductors. The third output transistor T6 and the fourth output transistor T7 are disposed in parallel along the first direction X.
In this embodiment, both the third output transistor T6 and the fourth output transistor T7 in the second output module 30 are low temperature polysilicon semiconductors with high mobility. Therefore, the transistors in the second output module 30 do not need to increase the length in the second direction Y to improve the driving capability of the third output transistor T6 and the fourth output transistor. In addition, the second gate driving signal output by the second output module 30 is a negative pulse signal, and the pulse width of the negative pulse signal is smaller than the pulse width of the positive pulse signal output by the first output module 20. Therefore, the output load of the second output module 30 is lower than the output load of the first output module 20. Therefore, the length of the first output module 20 of the present application in the second direction Y is smaller than the length of the second output module 30 in the second direction Y.
The technical solution of the present application will now be described in conjunction with specific embodiments.
Referring to
Referring to
In this embodiment, a plurality of light emitting devices LEDs and sub-pixel circuits for driving the light emitting devices LEDs can be arranged in an array in the display area AA. The sub-pixel circuits may be pixel driving circuits such as 7T1C, 7T2C, and 8T2C, which are not specifically limited in this application.
In this embodiment, the gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 may be disposed on both sides of the display area AA. The gate driving circuit 300 may include N GOA units 310 connected in cascade. N GOA units 310 may be arranged along the first direction X. The structure of the GOA unit 310 can be various, for example, the circuit structure in
Taking the structure of
Cascade signal selection module 301 is electrically connected between a start signal line STV and a fourth node O.
Pull-up control module 302 controls a potential of a first node K according to a potential of the fourth node O and a potential of a second clock signal line XCK.
First filter module 303 is electrically connected between a fifth node W and the first node K, and a control terminal of the first filter module 303 is electrically connected to a reset signal line RST.
Second filter module 304 is electrically connected between the fifth node W and a second node Q, and a control terminal of the second filter module 304 receives a first gate driving signal of a N−2th cascade.
First inverting module 305 is connected between the first node K and the third node P.
Feedback module 306 is connected between the first node K and the third node P.
First output module 20 is connected between the first node K and a first signal output terminal Nout and is configured to output the first gate driving signal.
Second output module 30 outputs a second gate driving signal according to a potential of the second node Q and a potential of the third node P.
First storage capacitor C1, wherein a first plate C1a of the first storage capacitor C1 is connected to the second node Q, and a second plate C1b of the first storage capacitor C1 is connected to a second signal output terminal Pout.
Voltage regulation module 307, wherein a first end of the voltage regulation module 307 is electrically connected to a first low potential line Nvgl1, a second end of the voltage regulation module 307 is connected to a gate of the first output transistor T10, and a control terminal of the voltage regulation module 307 is electrically connected to the third node P.
In this embodiment, in one frame, the gate driving circuit 300 includes a stage S100 and a stage S200. In this stage S100, the pulses of each first gate driving signal and the pulses of each second gate driving signal are outputted. However, in the stage S200, the pulses of the first gate driving signals and the pulses of the second gate driving signals are unnecessary.
In this embodiment, the cascade signal selection module 301 includes a first cascade transistor T13 and a second cascade transistor T12. The first cascade transistor T13 is a double-gate transistor. Two gates of the first cascade transistor T13 and a gate of the second cascade transistor T12 are connected to the start signal line STV. The source of the first cascade transistor T13 is connected to the second low potential line Pvgl. The drain of the first cascade transistor T13 and the source of the second cascade transistor T12 are connected to the fourth node O. The drain of the second cascade transistor T12 is connected to the third high potential line Pvgh2.
In this embodiment, the pull-up control module 302 includes a pull-up transistor T2. The gate of the pull-up transistor T2 is connected to the second clock signal line XCK. The source of the pull-up transistor T2 is connected to the fourth node O. The drain of the pull-up transistor T2 is connected to the first node K.
In this embodiment, the first filter module 303 includes a first filter transistor T11 and a second storage capacitor C2. A gate of the first filter transistor T11 and a third plate C2a of the second storage capacitor C2 are connected to a reset signal line RST. A source of the first filter transistor T11 is connected to the first node K. A drain of the first filter transistor T11 and a fourth plate C2b of the second storage capacitor C2 are connected to the fifth node W.
In this embodiment, the second filter module 304 includes a second filter transistor T8. A gate of the second filter transistor T8 is connected to a first signal output terminal Nout of a N−2th cascade GOA unit 310. A source of the second filter transistor T8 is connected to the fifth node W, and a drain of the second filter transistor T8 is connected to the second node Q.
In this embodiment, the first inverting module 305 includes a first inverting transistor T3 and a second inverting transistor T1. The second inverting transistor T1 is a double-gate transistor. A gate of the first inverting transistor T3 and both gates of the second inverting transistor T1 are connected to the first node K. A source of the first inverting transistor T3 is connected to a third high potential line Pvgh2. A drain of the first inverting transistor T3 and a source of the second inverting transistor T1 are connected to the third node P. A drain of the second inverting transistor T1 is connected to a second low potential line Pvgl.
In this embodiment, the feedback module 306 includes a first feedback transistor T4 and a second feedback transistor T5. A gate of the first feedback transistor T4 is connected to a first clock signal line CK. A source of the first feedback transistor T4 is connected to the first node K. A drain of the first feedback transistor T4 is connected to a source of the second feedback transistor T5. A gate of the second feedback transistor T5 is connected to the third node P, and a drain of the second feedback transistor T5 is connected to a second high potential line Pvgh1.
In this embodiment, the voltage regulation module 307 includes a regulation transistor T14. The regulation transistor T14 is a double-gate transistor. Both gates of the regulation transistor T14 are connected to the third node P. A source of the regulation transistor T14 is connected to the first node K. A drain of the regulation transistor T14 is connected to a first low potential line Nvgl1.
In this embodiment, the first output module 20 includes a first output transistor T10 and a second output transistor T9. The second output transistor T9 is a double-gate transistor. A first gate T10G of the first output transistor T10 and a second gate T9G of the second output transistor T9 are connected to the first node K of the signal generation module 10. A first source T10S of the first output transistor T10 is connected to the first high potential line Nvgh. A first drain T10D of the first output transistor T10 and a second source T9S of the second output transistor T9 are connected to the first signal output terminal Nout. A second drain T9D of the second output transistor T9 is connected to the first low potential line Nvgl1.
In this embodiment, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7. A third gate T6G of the third output transistor T6 is connected to the second node Q of the signal generation module 10. A third source T6S of the third output transistor T6 is connected to the first clock signal line CK. A third drain T6D of the third output transistor T6 and a fourth source T7S of the fourth output transistor T7 are connected to a second signal output terminal Pout. A fourth gate T7G of the fourth output transistor T7 is connected to the third node P of the signal generation module 10. A fourth drain T7D of the fourth output transistor T7 is connected to the second high potential line Pvgh1.
In this embodiment, the first cascade transistor T13, the second inverting transistor T1, the first output transistor T10, the regulation transistor T14N-type transistor, the second cascade transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.
In the gate driving circuit 300 provided in this embodiment, under the control of the third node P, the voltage regulation module 307 can stabilize or lower the gate potential of the first output transistor T10 through the first low potential line Nvgl1. This makes the first output transistor T10 stable or better in an off state to reduce leakage current. This further enables the potential of the first gate driving signal to be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate driving signal.
In this embodiment, the voltage regulation module 307 is configured to stabilize or reduce the low potential of the first node K. Alternatively, in another embodiment, the voltage regulation module 307 is further configured to stabilize or reduce the gate potential of the first output transistor T10 during the duration of the positive pulse of the first gate driving signal.
It should be noted that the regulation transistor T14 can stabilize or reduce the gate potential of the first output transistor T10 during the duration of the positive pulse of the first gate driving signal. This makes the first output transistor T10 stable or better in an off state to reduce leakage current. This further enables the potential of the first gate driving signal to be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate driving signal.
In this embodiment, the internal node is the third node P. The second low potential line Pvgl is a low potential line having the same potential as the first low potential line Nvgl1. The channel type of the regulation transistor T14 is the same as that of the first output transistor T10.
It should be noted that in this embodiment, the first output transistor T10 and the regulation transistor T14 can share the same low potential line, which can save the number of wires required by the gate driving circuit 300. The channel type of the regulation transistor T14 is the same as that of the first output transistor T10. This can turn on the regulation transistor T14 when the first output transistor T10 is in the cut-off state, so as to further reduce the gate potential of the first output transistor T10.
In an embodiment, referring to
It should be noted that the channel type of the regulation transistor T14 is the same as that of the first output transistor T10. This can transmit the second low potential signal to the gate of the first output transistor T10 through the regulation transistor T14 when the first output transistor T10 is in the cut-off state. This can further reduce the gate potential of the first output transistor T10, thereby reducing the leakage current of the first output transistor T10. In this way, the stability of the low potential of the second node QK and the low potential of the intermediate node W can be improved.
In one embodiment, the potential difference between the first low potential signal and the second low potential signal is greater than or equal to 2V.
It should be noted that this embodiment can not only reduce the leakage current of the first output transistor T10, but also adjust the threshold voltage of the first output transistor T10 to shift positively. This further increases the range of the threshold voltage of the first output transistor T10.
The film layers of the display panel 100 of the present application will be described below with reference to the structure of
Referring to
In this embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom emission light emitting display device or a double side emission light emitting display device, a transparent base substrate is used. When the display panel 100 is a top emission light emitting display device, a translucent or opaque base substrate as well as a transparent base substrate may be used.
In this embodiment, the base substrate 110 is configured to support various film layers disposed on the base substrate 110. The base substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that may be bent, folded, rolled, or the like. Examples of flexible materials for the flexible substrate include polyimide (PI) but are not limited to polyimide (PI).
In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide. The first barrier layer 112 and the second barrier layer 114 may be formed of, for example, an inorganic material including at least one of SiOx and SiNx.
In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a support substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the same material as that of the first flexible substrate 111 and curing the material. The second flexible substrate 113 is formed by the same method as that of the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, so that the above-mentioned defects can be removed.
Referring to
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In this embodiment, the first gate layer 125 may include a second gate T9G and a third gate T6G. In the second direction Y, the length of the second gate T9G is greater than the length of the third gate T6G, and an area of the second gate T9G is greater than an area of the third gate T6G.
In this embodiment, the second output transistor T9 is configured to output the first gate driving signal, and the third output transistor T6 is configured to output the second gate driving signal. The load of the first gate driving signal is greater than the load of the second gate driving signal, therefore, in order to increase the output load of the first output module 20, the application makes the area of the second gate T9G larger than the area of the third gate T6G.
Referring to
Referring to
In this embodiment, both the length and the number of the strip branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the second gate T9G and the third gate T6G, the present application sets the second gate T9G and the third gate T6G as a plurality of strip-shaped branch gates arranged separately. Each strip branch gate bears the load of the corresponding transistor. The strip-shaped branch electrodes correspond to the channels of the active parts of the corresponding transistors. Between two adjacent strip-shaped branch gates corresponds to the source and drain of the upper layer. The composite electric field formed by a plurality of separately arranged strip-shaped branch gates can improve the driving capability of the transistor.
In this embodiment, in the first direction X, the distance between two adjacent second branch gates T9Gb and the distance between two adjacent third branch gates T6Gb may be equal.
Referring to
In this embodiment, the third output transistor T6 is connected to the first clock signal line CK, and it needs to bear a relatively large load. Therefore, in the present application, the third gate T6G is provided with three strip-shaped branch gates. The fourth gate T7G is not connected to the corresponding clock signal line, and the load that the fourth output transistor T7 needs to bear is relatively small. Therefore, the fourth gate T7G is only provided with a strip-shaped branch gate.
In this embodiment, in the first direction X, a distance between the fourth gate T7G and the adjacent third branch gate T6Gb may be equal to the distance between two adjacent third branch gates T6Gb. That is, the distance between two adjacent second branch gates T9Gb, the distance between two adjacent third branch gates T6Gb, and the distance between the fourth gate T7G and the adjacent third branch gate T6Gb are all equal. That is, the spacing between the strip-shaped branch electrodes is equal, which reduces the difficulty of patterning.
Referring to
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In this embodiment, the gate T2G of the pull-up transistor T2, the gate T3G of the first inverting transistor T3, the gate T11G of the first filter transistor T11, the gate T12G of the second cascade transistor T12, the third plate C2a of the second storage capacitor C2 extend along the second direction Y, the gate T12G of the second cascade transistor T12 disposed close to the first output module 20, the gate T3G of the first inverting transistor T3, the gate T2G of the pull-up transistor T2, and the gate T11G of the first filter transistor T11 are sequentially arranged along the first direction X in the middle area of the signal generation module 10. The gate T12G of the second cascade transistor T12 is on the same straight line as the third plate C2a of the second storage capacitor C2. The gate T11G of the first filter transistor T11 is directly connected to the third plate C2a of the second storage capacitor C2.
In this embodiment, the gate T4G of the first feedback transistor T4, the gate T5G of the second feedback transistor T5, and the gate T8G of the second filter transistor T8 extend along the first direction X, and the three are arranged close to the second output module 30. The gate T4G of the first feedback transistor T4 and the gate T5G of the second feedback transistor T5 are arranged in parallel along the second direction Y. The gate T4G of the first feedback transistor T4 is disposed away from the fourth gate T7G, and the gate T5G of the second feedback transistor T5 is disposed close to the fourth gate T7G. The gate T5G of the second feedback transistor T5 and the gate T8G of the second filter transistor T8 are arranged along the first direction X. The gate T5G of the second feedback transistor T5 is directly connected to the extended section of the fourth gate T7G of the fourth output transistor T7 in the second direction Y.
Referring to
The second gate layer 127 may include a first gate T10G. The first gate T10G includes two first trunk gates T10Ga and a plurality of first branch gates T10Gb disposed between the two first trunk gates T10Ga. The two first trunk gates T10Ga are opposite and arranged in parallel. The two first trunk gates T10Ga extend along the first direction X, and the plurality of first branch gates T10Gb extend along the second direction Y. Both ends of the plurality of first branch gates T10Gb are respectively connected to two first trunk gates T10Ga. For example, the first gate T10G includes two first trunk gates T10Ga and four first branch gates T10Gb. Both ends of the four first branch gates T10Gb are respectively connected to the two first trunk gates T10Ga.
In this embodiment, in the second direction Y, the length of the first branch gate T10Gb is greater than the length of the second branch gate T9Gb. The first output transistor T10 is a metal oxide semiconductor transistor with low mobility. Therefore, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first branch gate T10Gb. That is, it is equivalent to increasing the width of the channel in the first active portion T10A and improving the electron mobility in the first output transistor T10. This ensures the driving capability of the first output transistor T10.
Referring to
In this embodiment, the second gate layer 127 further includes the first gate T1G of the second inverting transistor T1, the first gate T131G of the first cascade transistor T13, the first gate T14G of the regulation transistor T14, and the fourth plate C2b of the second storage capacitor C2. The first gate T1G of the second inverting transistor T1, the first gate T13G of the first cascade transistor T13, and the fourth plate C2b of the second storage capacitor C2 extend along the second direction Y. The first gate T14G of the regulation transistor T14 extends along the first direction X.
Referring to
In this embodiment, the orthographic projection of the third plate C2a on the fourth plate C2b is located inside the fourth plate C2b. That is, the area of the third plate C2a is smaller than or equal to the area of the fourth plate C2b. In this embodiment, the area of the third plate C2a is smaller than the area of the fourth plate C2b. That is, increase the area of the fourth plate C2b as much as possible to increase the facing area between the two plates. This increases the capacitance of the second storage capacitor C2 to improve the stability of the voltage in the fifth node W.
In this embodiment, the capacitance of the second storage capacitor C2 needs to be larger than 50 F.
In this embodiment, the area of the first plate C1a is greater than the area of the third plate C2a, and the area of the second plate is greater than the area of the fourth plate C2b. The ratio of the capacitance of the first storage capacitor C1 to the capacitance of the second storage capacitor C2 is greater than 2. The first plate C1a of the first storage capacitor C1 is connected to the third gate T6G of the third output transistor T6. The second plate C1b of the first storage capacitor C1 is connected to the third drain T6D of the third output transistor T6. The third source T6S of the third output transistor T6 is connected to the first clock signal line CK. The output signal of the clock signal line at different times may be reversed, which may affect the stability of the output signal of the second signal output terminal Pout connected to the third drain T6D of the third output transistor T6. Therefore, the present application ensures the output stability of the first signal output terminal Nout by increasing the capacitance of the first storage capacitor C1.
In the structure of
Referring to
The array driving layer 120 further includes a third gate layer 131 disposed on a side of the second gate layer 127 away from the base substrate 110. The third gate layer 131 includes a fifth gate T10H. The fifth gate T10H includes two fifth trunk gates T10Ha and a plurality of fifth branch gates T10Hb disposed between the two fifth trunk gates T10Ha. The two fifth trunk gates T10Ha are opposite and arranged in parallel. The two fifth trunk gates T10Ha extend along the first direction X, and the plurality of fifth branch gates T10Hb extend along the second direction Y. Both ends of the plurality of fifth branch gates T10Hb are respectively connected to the two first trunk gates T10Ga. For example, the fifth gate T10H may include 2 fifth trunk gates T10Ha and 4 fifth branch gates T10Hb. Both ends of the four fifth branch gates T10Hb are connected to the two fifth trunk gates T10Ha.
In this embodiment, the first output transistor T10 is a double-gate transistor. The first gate T10G and the fifth gate T10H of the first output transistor T10 are disposed on upper and lower sides of the first active part T10A. The first gate T10G and the fifth gate T10H are electrically connected to simultaneously drive the transfer of carriers in the first active part T10A, thereby increasing the conduction rate of the first output transistor T10.
In this embodiment, in the second direction Y, the length of the first branch gate T10Gb is equal to the length of the fifth branch gate T10Hb. Both the first branch gate T10Gb and the fifth branch gate T10Hb bear the output load of the first output transistor T10. In addition, the fifth branch gate T10Hb needs to be used as a shielding layer to perform ion doping on the first active part T10A. Therefore, the length of the channel in the first active part T10A in the first direction X is equal to the length of the fifth branch gate T10Hb in the fifth gate T10H in the first direction X. In order to ensure that external light enters the first active part T10A, the present application makes the orthographic projection of the fifth branch gate T10Hb on the corresponding first branch gate T10Gb be located within the corresponding first branch gate T10Gb. That is, the area of the first branch gate T10Gb is greater than or equal to the area of the fifth branch gate T10Hb. In this embodiment, the area of the first branch gate T10Gb may be greater than the area of the fifth branch gate T10Hb. It may also be that the distance between two adjacent first branch gates T10Gb is smaller than the distance between two adjacent fifth branch gates T10Hb.
In this embodiment, the distance between two adjacent first branch gates T10Gb may be smaller than the distance between two adjacent second branch gates T9Gb in the second output transistor T9. The distance between two adjacent second branch gates T9Gb may be smaller than the distance between two adjacent fifth branch gates T10Hb.
Referring to
The second inverting transistor T1, the first cascade transistor T13, and the regulation transistor T14 are metal oxide semiconductor transistors. Therefore, in order to improve the driving capability of the second inverting transistor T1, the first cascade transistor T13, and the regulation transistor T14, the second inverting transistor T1, the first cascade transistor T13, and the regulation transistor T14 can all be double-gate transistors. That is, the third gate layer 131 may further include a second gate T1H of the second inverting transistor T1, a second gate T13H of the first cascade transistor T13, and a second gate T14H of the regulation transistor T14. The second gate T1H of the second inverting transistor T1 and the second gate T13H of the first cascade transistor T13 extend along the second direction Y. The second gate T14H of the regulation transistor T14 extends along the first direction X.
In this embodiment, in order to prevent external light from entering the active parts of the second inverting transistor T1, the first cascade transistor T13, and the regulation transistor T14, the second gate T1H of the second inverting transistor T1 is orthographically projected on the corresponding first gate T1G into the corresponding first gate T1G. The second gate T13H of the first cascade transistor T13 is orthographically projected on the corresponding first gate T13G into the corresponding first gate T13G. The second gate T14H in the regulation transistor T14 is projected orthographically on the corresponding first gate T14G within the corresponding first gate T14G. The area of the second gate T1H of the second inverting transistor T1 is smaller than the area of the corresponding first gate T1G. The area of the second gate T13H of the first cascade transistor T13 is smaller than the area of the corresponding first gate T13G. The area of the second gate T14H in the regulation transistor T14 is smaller than the area of the corresponding first gate T14G.
Referring to
The array driving layer 120 also includes a first active layer 123 disposed between the first gate layer 125 and the base substrate 110. The first active layer 123 includes a low temperature polysilicon semiconductor. The first active layer 123 includes a second active part T9A and a third active part T6A. The second active part T9A overlaps with the plurality of second branch gates T9Gb. The third active part T6A overlaps with the plurality of third branch gates T6Gb.
In this embodiment, the second output transistor T9 and the third output transistor T6 are top-gate transistors. The second gate T9G can be used as a shielding layer of the second active part T9A to perform ion doping on the second active part T9A. The third gate T6G may serve as a shielding layer for the third active part T6A, so as to perform ion doping on the third active part T6A. Therefore, the part of the active part that overlaps with the corresponding branch gate is the channel part, and the non-overlapping part of the active part is the source connection part and the drain connection part on both sides of the channel part. For example, in the structure of
In this embodiment, the lengths of the second branch gate T9Gb and the third branch gate T6Gb in the second direction Y are sufficiently long. Therefore, in order to increase the width of the channel in the active part, the dimensions of the second active part T9A and the third active part T6A in the second direction Y are increased as much as possible. When the size of the low temperature polysilicon semiconductor in the second direction Y is too large, static electricity may be concentrated in the active part. This may cause the active part to be damaged by static electricity. Therefore, in the present application, the second active part T9A and the third active part T6A can be set as two sub-active parts separately arranged.
Referring to
In this embodiment, in the second direction Y, the width of the second sub-active part T9Aa is greater than the width of the third sub-active part T6Aa. The output load of the second output transistor T9 is larger than the output load of the third output transistor T6. Therefore, the present application increases the second output load by increasing the width of the second sub-active part T9Aa.
It should be noted that, the width of the second sub-active part T9Aa and the width of the third sub-active part T6Aa correspond to the width of the sub-active part in the second direction Y.
Referring to
In this embodiment, in the second direction Y, the width of the fourth sub-active part T7Aa may be equal to the width of the third sub-active part T6Aa.
In this embodiment, in order to simplify the process, the pattern of the third active part T6A may be connected to the pattern of the fourth active part T7A. This increases the pattern area of the active part in the second output module 30, reduces the film forming precision of the active part in this area, and simplifies the film forming process.
In the structure of
Referring to
In this embodiment, the array driving layer 120 further includes a second active layer 129 disposed between the third gate layer 131 and the second gate layer 127. The second active layer 129 includes metal oxide semiconductor. The second active layer 129 includes the first active part T10A. The first active part T10A includes two first sub-active parts T10Aa arranged at intervals. The first sub-active part T10Aa extends along the first direction X, and the two first sub-active parts T10Aa overlap with the plurality of first branch gates T10Gb.
In this embodiment, since the first output transistor T10 is a double-gate transistor, both the first gate T10G and the fifth gate T10H of the first output transistor T10 can serve as switches of the first output transistor T10. In addition, the fifth gate T10H may serve as a shielding layer for the first active part T10A, so as to perform ion doping on the first active part T10A. Therefore, the part of the first active part T10A overlapping with the plurality of first branch gates T10Gb is the channel part of the first active part T10A. Parts of the first active part T10A that do not overlap with the plurality of first branch gates T10Gb are source connection parts and drain connection parts on both sides of the channel part. For example, in the structures of
In this embodiment, the first output transistor T10 is a metal-oxide-semiconductor transistor, and this type of transistor has the advantage of low leakage current, but its mobility is small. Therefore, in order to increase the mobility of the first output transistor T10, it is necessary to increase the width of the channel part in the first active part T10A. That is, it corresponds to the width of the first sub-active part T10Aa in the second direction Y. Therefore, in the second direction Y, the width of the first sub-active part T10Aa is larger than the width of the second sub-active part T9Aa.
In addition, when the width of the first active part T10A in the second direction Y is too large, static electricity may be concentrated on the first active part T10A. This may cause the first active part T10A to be damaged by static electricity. Therefore, in the present application, the first active part T10A can be configured as two first sub-active parts T10Aa that are separately arranged.
Referring to
In the structures of
In this embodiment, the distance between the first trunk gate T10Ga, the fifth trunk gate T10Ha and the first active part T10A in the second direction Y is the first distance. The distance between the end of the second branch gate T9Gb away from the second trunk gate T9Ga and the second active part T9A in the second direction Y is the second distance. The distance between the end of the third branch gate T6Gb away from the third trunk gate T6Ga and the third active part T6A in the second direction Y is the third distance. The first distance is greater than the second distance, and the second distance is greater than or equal to the third distance.
In this embodiment, the first distance may be greater than 5 microns, the second distance may be greater than 2.5 microns, and the third distance may be greater than 2.5 microns.
Referring to
In this embodiment, the array driving layer 120 further includes a first source-drain layer 133 disposed on a side of the third gate layer 131 away from the second gate layer 127. The first source-drain layer 133 includes a first source T10S, a first drain T10D, a second source T9S, and a second drain T9D.
In this embodiment, the first source T10S includes a first trunk source T10Sa and a plurality of first branch sources T10Sb arranged at intervals and in parallel. The first drain T10D includes a plurality of first branch drains T10Db. The first trunk source T10Sa extends along the first direction X, and the first branch source T10Sb extends along the second direction Y. A side of the plurality of first branch sources T10Sb away from the signal generation module 10 is connected to the first trunk source T10Sa. The plurality of first branch drains T10Db extend along the second direction Y, and the plurality of first branch drains T10Db are disposed between the plurality of first branch sources T10Sb.
In this embodiment, in the top view direction of the display panel 100, two first branch sources T10Sb on two sides of the plurality of first branch sources T10Sb are disposed on two sides of the first gate T10G. Among the plurality of first branch sources T10Sb, at least one first branch source T10Sb and the plurality of first branch drains T10Db are disposed between the plurality of first branch gates T10Gb. For example, in the structure of
In this embodiment, the second drain T9D includes a second trunk drain T9Da and a plurality of second branch drains T9Db arranged at intervals and in parallel. The second source T9S includes a plurality of second branch sources T9Sb. The second main drain T9Da extends along the first direction X. The second branch drain T9Db extends along the second direction Y. The plurality of second branch drains T9Db are connected to the second trunk drain T9Da on a side close to the signal generation module 10. The plurality of second branch sources T9Sb extends along the second direction Y. A plurality of second branch sources T9Sb are disposed between the plurality of second branch drains T9Db, and the first trunk source T10Sa is connected to the second trunk drain T9Da.
In this embodiment, in the top view direction of the display panel 100, two second branch drains T9Db on two sides of the plurality of second branch drains T9Db are disposed on two sides of the second gate T9G. The inner at least one second branch drain T9Db and the plurality of second branch sources T9Sb among the plurality of second branch drains T9Db are disposed between the plurality of second branch gates T9Gb. For example, in the structure of
In this embodiment, both the first trunk source T10Sa and the second trunk drain T9Da overlap with the first trunk gate T10Ga on the side away from the signal generation module 10. That is, the first trunk source T10Sa and the second trunk drain T9Da may share one trunk electrode.
In this embodiment, the mobility of the first output transistor T10 is relatively low. In order to improve the driving capability of the first output transistor T10, the present application increases the electron mobility in the first output transistor T10 by increasing the width of the channel in the first active part T10A. In order to enable the data signal to be transmitted from the source of the transistor to the drain of the transistor as soon as possible, the present application increases the electron mobility in the first output transistor T10 by increasing the width of the channel in the first active part T10A. In addition, the first branch source T10Sb is electrically connected to the source connection part in the first sub-active part T10Aa through a plurality of source contact holes. The first branch drain T10Db is electrically connected to the drain connection part in the first sub-active part T10Aa through a plurality of drain contact holes. Therefore, in the second direction Y, the length of the first branch source T10Sb is greater than the length of the second branch drain T9Db.
Referring to
In this embodiment, each first branch source T10Sb is electrically connected to the source connection part in the first sub-active part T10Aa through four contact holes of the first source T10S. Each first branch drain T10Db is electrically connected to the drain connection part in the first sub-active part T10Aa through four contact holes of the first drain T10D. Each second branch drain T9Db is electrically connected to the drain connection part in the first sub-active part T10Aa through three contact holes of the second drain T9D. Each first branch source T10Sb is electrically connected to the source connection part in the first sub-active part T10Aa through three contact holes of the second source T9S.
In this embodiment, the first source T10S contact hole and the first drain T10D contact hole penetrate through the first interlayer insulating layer 132 and the fourth gate insulating layer 130. The second source T9S contact hole and the second drain T9D contact hole penetrate the first interlayer insulating layer 132, the fourth gate insulating layer 130, the third gate insulating layer 128, the second gate insulating layer 126, and the first gate insulating layer 124.
The first gate T10G of the first output transistor T10 is electrically connected to the second gate T9G of the second output transistor T9. The first gate T10G is on the first gate layer 125, and the second gate T9G is on the second gate layer 127. Therefore, in order to electrically connect the first gate T10G and the second gate T9G, it is necessary to leave a certain distance between the end of the second branch source T9Sb close to the signal generation module 10 and the second trunk drain T9Da, so as to set the first connection section 151 connecting the first gate T10G and the second gate T9G.
Referring to
In this embodiment, referring to
In this embodiment, the first end of the first connection section 151 overlaps with the first protrusion part 141 and the second trunk gate T9Ga. The second end of the first connection section 151 overlaps with the second trunk gate T9Ga. The first end of the first connection section 151 is electrically connected to the first protrusion part 141 through the first via hole HL1. The second end of the first connection section 151 is electrically connected to the second trunk gate T9Ga through the second via hole HL2. That is, the first end of the first connection section 151 is electrically connected to the fifth gate T10H. The second end of the first connection section 151 is electrically connected to the second gate T9G. The first gate T10G is electrically connected to the fifth gate T10H, therefore, the second gate T9G is electrically connected to the first gate T10G through the fifth gate T10H.
In the structures of
In this embodiment, the first via hole HL1 penetrates through the first interlayer insulating layer 132, the second via hole HL2 penetrates through the first interlayer insulating layer 132, the fourth gate insulating layer 130, the third gate insulating layer 128, and the second gate insulating layer 126.
The first gate T10G and the fifth gate T10H in the first output transistor T10 are electrically connected. The first gate T10G is in the first gate layer 125, and the fifth gate T10H is in the third gate layer 131. Therefore, in order to electrically connect the first gate T10G and the fifth gate T10H, in the present application, a connection section connecting the first gate T10G and the fifth gate T10H may be provided on the side of the first branch drain T10Db close to the signal generation module 10.
Referring to
In this embodiment, a first end of the second connection section 152 overlaps with the second protrusion part 142. A second end of the second connection section 152 overlaps with the third protrusion part 143. The first end of the second connection section 152 is electrically connected to the third protrusion part 143 through the third via hole HL3. The second end of the second connection section 152 is electrically connected to the second protrusion part 142 through the fourth via hole HL4. That is, the first end of the second connection section 152 is electrically connected to the fifth gate T10H. The second end of the second connection section 152 is electrically connected to the first gate T10G. The arrangement of the first connection section 151 and the second connection section 152 electrically connects the first gate T10G, the second gate T9G, and the fifth gate T10H together.
In the display panel 100 of the present application, the plurality of first branch source electrodes T10Sb include the first bottom electrode T10Sc close to the next stage GOA unit 310. The plurality of second branch drains T9Db include a second bottom electrode T9Dc close to the next stage GOA unit 310. Both the first bottom electrode T10Sc and the second bottom electrode T9Dc are electrically connected to the first signal output terminal Nout.
Referring to
Referring to
In this embodiment, the third source T6S may include a third trunk source T6Sa and two third branch sources T6Sb arranged in parallel and spaced apart. One end of the two third branch sources T6Sb close to the signal generation module 10 is connected to the third trunk source T6Sa. The third drain T6D includes a third trunk drain T6Da and two third branch drains T6Db arranged in parallel and spaced apart. One end of the two third branch drains T6Db close to the signal generation module 10 is connected to the third trunk drain T6Da. The two third branch sources T6Sb and the two third branch drains T6Db are alternately arranged in the first direction X.
In this embodiment, the fourth source T7S and the fourth drain T7D extend along the second direction Y. The fourth drain T7D is disposed next to the third branch drain T6Db. The fourth source T7S is disposed on a side of the fourth drain T7D away from the third branch drain T6Db. The first end of the fourth source T7S is connected to the third trunk drain T6Da.
Referring to
In this embodiment, the tenth via hole HL10 penetrates through the first interlayer insulating layer 132, the fourth gate insulating layer 130, the third gate insulating layer 128, and the second gate insulating layer 126. The second signal output terminal Pout is configured to output the second gate driving signal.
Referring to
Referring to
Referring to
In this embodiment, the drain T3D of the first inverting transistor T3 and the source T1S of the second inverting transistor T1 extend along the second direction Y and are connected. The drain T2D of the pull-up transistor T2, the source T11S of the first filter transistor T11, the source T4S of the first feedback transistor T4 and the second connection section 152 are connected to each other.
In this embodiment, referring to
Referring to
In this embodiment, the array driving layer 120 further includes a second source-drain layer 135 disposed on a side of the first source-drain layer 133 away from the base substrate 110. The second source-drain layer 135 includes a first high potential line Nvgh. The first high potential line Nvgh extends in the first direction X. The first high potential line Nvgh overlaps with the plurality of second branch sources T9Sb and the plurality of second branch drains T9Db in each GOA unit 310. The first high potential line Nvgh is electrically connected to the plurality of second branch sources T9Sb in each GOA unit 310 through the fifth via hole HL5.
Referring to
Referring to
Referring to
In this embodiment, in order to avoid the voltage of the first high potential line Nvgh from interfering with the voltage of the signal lines in the display part 200, in this application, the first high potential line Nvgh may be overlapped with the second sub-active part T9Aa on the side close to the signal generation module 10. In addition, in order to leave enough space to arrange the reset signal line RST, the first low potential line Nvgl1 may overlap the first sub active part T10Aa on a side away from the signal generation module 10.
Referring to
In
Referring to
Referring to
In this embodiment, in the display panel 100 of the present application, the gate driving circuit 300 includes a plurality of repeating units. Each repeating unit includes at least four GOA units 310. Taking four GOA units 310 as an example below as a repeating unit, multiple repeating units are arranged in the first direction X.
Referring to
In this example, the repeating unit may include a first GOA unit 311, a second GOA unit 312, a third GOA unit 313, and a fourth GOA unit 314 arranged in sequence along the first direction X. The display panel 100 may include a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4 arranged along the second direction Y. Every two clock signal lines are connected to one GOA unit 310.
In this embodiment, the first clock signal line PCK1 and the second clock signal line PCK2 are connected to the first GOA unit 311. The first clock signal line PCK1 is the first clock signal line CK of the first GOA unit 311. The second clock signal line PCK2 is the second clock signal line XCK of the first GOA unit 311. That is, the first clock signal line PCK1 is connected to the gate of the third output transistor T6 in the first GOA unit 311. The second clock signal line PCK2 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.
In this embodiment, the second clock signal line PCK2 and the third clock signal line PCK3 are connected to the second GOA unit 312. The second clock signal line PCK2 is the first clock signal line CK of the first GOA unit 311. The third clock signal line PCK3 is the second clock signal line XCK of the first GOA unit 311. That is, the second clock signal line PCK2 is connected to the gate of the third output transistor T6 in the first GOA unit 311. The third clock signal line PCK3 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.
In this embodiment, the third clock signal line PCK3 and the fourth clock signal line PCK4 are connected to the third GOA unit 313. The third clock signal line PCK3 is the first clock signal line CK of the first GOA unit 311. The fourth clock signal line PCK4 is the second clock signal line XCK of the first GOA unit 311. That is, the third clock signal line PCK3 is connected to the gate of the third output transistor T6 in the first GOA unit 311. The fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.
In this embodiment, the fourth clock signal line PCK4, the first clock signal line PCK1, and the fourth GOA unit 314 are connected. The fourth clock signal line PCK4 is the first clock signal line CK of the first GOA unit 311. The first clock signal line PCK1 is the second clock signal line XCK of the first GOA unit 311. That is, the fourth clock signal line PCK4 is connected to the gate of the third output transistor T6 in the first GOA unit 311. The fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.
Referring to
In this embodiment, the third output transistors T6 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313, and the fourth GOA unit 314 are connected to different clock signal lines. Therefore, among the repeating units, the lengths of the first extension sections 161 in some GOA units 310 in the first direction X are different. That is, the lengths of the first extension sections 161 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313, and the fourth GOA unit 314 are different. For example, the lengths of the first extension sections 161 in the first GOA unit 311 and the second GOA unit 312 are equal. The lengths of the first extension sections 161 in the second GOA unit 312, the third GOA unit 313, and the fourth GOA unit 314 gradually increases.
In this embodiment, in the second GOA unit 312, both the gate of the first feedback transistor T4 and the third output transistor T6 are connected to the second clock signal line PCK2, and the positions of the two connections are close to each other. Therefore, in order to avoid interference between the two, the first source-drain layer 133 in the second GOA unit 312 further includes a third extension section 163. The third extension section 163 extends along the first direction X, and the second clock signal line PCK2 is electrically connected to the first extension section 161 through the third extension section 163.
In this embodiment, referring to
In
In
Referring to
Referring to
In this embodiment, the eighth transistor penetrates through the second interlayer insulating layer 134. The ninth transistor penetrates through the third via hole HL3 through the second interlayer insulating layer 134, the first interlayer insulating layer 132, the fourth gate insulating layer 130, the third gate insulating layer 128, and the second gate insulating layer 126.
Referring to
It should be noted that the source and drain of the above-mentioned transistors in this application are only different in name, as long as one of them is an input terminal and the other is an output terminal.
It should be noted that the film layer structure diagram provided in this application is not only applicable to the circuit structures in
The present application also provides a display terminal, which includes the above-mentioned display panel. The display terminal can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.
A display panel and a display terminal provided in the embodiments of the present application have been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application. The descriptions of the above embodiments are only used to help understand the technical solutions and core ideas of the present application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Number | Date | Country | Kind |
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202310929106.9 | Jul 2023 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2023/113780 | 8/18/2023 | WO |