1. Field of the Invention
The instant disclosure relates to a structure of a display panel, in particular, to a display panel having spacers.
2. Description of Related Art
At present, most thin film transistor liquid crystal displays (TFT-LCD) include an active element array substrate, a color filter and a backlight module. The active element array substrate includes a substrate and a plurality of thin film transistors formed on the substrate. The thin film transistors are used to control the voltage of sub-pixel to adjust the deflection angle of the liquid crystal molecule, so that the light amount passing through the polarizer can be controlled. As such, the grey scale of each sub-pixel can be determined by the thin film transistors. By adjusting the gray scale of each sub-pixel and the use of the color filter, a display image can be displayed when the backlight module or self-luminous element emits lights.
As the development of touch technology, the touch technology is widely implemented in most current display panels to replace conventional control devices, such as the mouse and keyboard, to control the cursor and schema. When a user uses a display panel by touching the surface of the display panel, an upper substrate of the display panel will slightly downward deform due to the pressure. In this situation, a portion of spacers arranged between the upper substrate and the lower substrate to separate the upper substrate from the lower substrate may also deform, deviate or slide as the upper substrate is being pressed. However, the deviations of the portion of the spacers may result in abnormal rotations of the liquid crystal molecules and the abnormal display images of the display panel.
The embodiment of the instant disclosure provides a display panel having an active element array layer to improve the deviation of spacer caused by pressure.
One of the embodiments of the instant disclosure provides a display panel which includes a first substrate, a second substrate, a scan line, a channel layer, a data line and a spacer. The scan line is disposed on the first substrate. The channel layer is disposed on the scan line. The data line is disposed on the first substrate and intersects with the scan line, and the data line has at least an overlapping region superimposing on the scan line. The overlapping region of the data line has a first region, and the first region is disposed on the channel layer and has a through hole. The spacer is disposed on the data line and has a first portion and a second portion, in which the first portion is disposed on the first region and the second portion is disposed outside of the first region.
Another embodiment of the instant disclosure provides a display panel. The display panel includes a first substrate, a scan line, a channel layer, a data line and a pixel electrode. The scan line disposed on the first substrate has a first side and a second side. The channel layer is disposed on the scan line, and the pixel electrode is disposed on the first substrate. The data line is disposed on the first substrate and intersects with the scan line. The data line has at least an overlapping region superimposing on the scan line. The overlapping region of the data line has a first region, and the first region is disposed on the channel layer and has a through hole. The first region has a fifth side adjacent to the first side and a sixth side adjacent to the second side. A first minimum distance between the first side and the fifth side is larger than a second minimum distance between the second side and the sixth side.
In summary, a display panel is provided in the instant disclosure. The data line has an overlapping region including the first region, the second region and the third region, in which the first region has a higher surface level than that of the second region and that of the third region because the first region is superimposed on the channel layer. Accordingly, the overlapping region has at least one step-difference structure formed between the first region and the second region (or the third region). The display panel further includes the spacer having a first portion disposed on the first region and a second portion disposed outside of the first region, i.e., the spacer is arranged on the data line in alignment with the step-difference structure. As such, when the second substrate of the display panel is deformed downward under a touch pressure provided by the user, the bottom portion of the spacer is forced to engage to the step-difference structure and the sliding friction force is produced and enhanced to resist the sliding movement of the spacer. Accordingly, the abnormal rotations of the liquid crystal molecules due to the deviation of the spacer can be avoided as possible.
In addition, the channel layer can be arranged relatively distant from the pixel electrode electrically connected to the channel layer and closer to another pixel electrode insulated from the channel layer. Additionally, the pixel electrode can be arranged to partially overlap with the channel layer and a first side of the scan line. As such, it is can be avoided that the protruding portion of the pixel electrode partially overlaps with the data line during the processing procedure, and further prevent the formation of the back channel and the parasitic capacitance from increasing.
Furthermore, the scan line can have a first recessed portion, so that the overlapping region has smaller area to reduce the parasitic capacitance between the data line and the scan line. Additionally, the first recessed portion of the scan line has a relatively gentle slope to assist in forming the data line.
In another embodiment, the scan line can further have a second recessed portion, and the second recessed portion and the first recessed portion are respectively formed on opposite two sides of the scan line and both located at a cross portion where the scan line and the data line are crossed such that the formation of the data line on the scan line having the first and second recessed portions becomes easier. In addition, the second region and the third region have smaller areas, which results in lower parasitic capacitance between the data line and the scan line.
In order to further understand the techniques, means and effects of the instant disclosure, the following detailed descriptions and appended drawings are hereby referred to, such that, and through which, the purposes, features and aspects of the instant disclosure can be thoroughly and concretely appreciated; however, the appended drawings are merely provided for reference and illustration, without any intention to be used for limiting the instant disclosure.
The accompanying drawings show some exemplary embodiments, and a more detailed description of various embodiments with reference to the accompanying drawings in accordance with the present disclosure is set forth below. The concept of the invention may be embodied in many different forms and should not be construed as limited to the embodiment set forth herein. To be more precise, the exemplary embodiments set forth herein are provided to a person of ordinary skill in the art to thoroughly and completely understand the contents disclosed herein and fully provide the spirit of the invention. In each of the drawings, the relative size, proportions, and depiction of the layers and regions in the drawings may be exaggerated for clarity and precision, and in which like numerals indicate like elements.
The channel layer 120 is a semiconductor layer whose materials can be selected from a group consisting of polysilicon, metal oxide semiconductor, amorphous silicon, and the combination thereof. In this embodiment, the material of the channel layer 120 can be selected from indium-gallium-zinc oxide, zinc oxide, stannous oxide, indium-zinc oxide, gallium-zinc oxide, zinc-tin oxide, indium-tin oxide or mixtures thereof. In this embodiment, the material of the channel layer 120 is indium-gallium-zinc oxide. However, the instant disclosure does not limit the material of the channel layer 120. Additionally, the channel layer 120 can be fabricated by magnetron sputtering, metal organic chemical-vapor deposition (MOCVD) or pulsed laser deposition (PLD).
The protection layer 140 is disposed on the channel layer 120 and can serve as an etch stop layer (ESL) in order to prevent the channel layer 120 from damage in subsequent processing procedures, which may result in electrical abnormality. The material of the protection layer 140 is silicon oxide (SiOx). The protection layer 140 can be patterned through the lithography etching process to form a through hole V1 and a through hole V2. The data line 130 is arranged on the protection layer 140 in a stacking manner and formed in the through hole V1 to connect the channel layer 120 and serve as a source electrode. During the formation of the data line 130 and the source electrode, the drain electrode 131 connected to the channel layer 120 also can be simultaneously formed in an inner wall of the through hole V2 by the same processing procedure. The drain electrode 131 is electrically isolated from the data line 130 and the source electrode.
The spacer PS is located between the data line 130 of the active element array layer T1 and the second substrate B2 to maintain the cell gap between the first substrate B1 and the second substrate B2. In this embodiment, the spacer PS is formed on the color filter layer CF and extends toward the active element array layer T1. Approximately, the spacer PS is located on a portion of the scan line 110 covered by the data line 130 and in contact with the alignment film PI located on the data line 130. In particular, the spacer PS can be designed to have a sphere shape, polygonal column, cone shape, pyramid shape, multi-layer shape or plate. The spacer PS can be made of photoresist materials with transparent or various colors, polymer materials or silicon-oxygen materials, and can be formed through lithography processes, sputtering process, chemical vapor deposition or spray. However, the instant disclosure does not limit the structure and process conditions of the spacer PS.
Specifically, the scan line 110 has a first side S1 and second side S2, and data line 130 has a third side S3 and fourth side S4. When looking toward the first substrate B1 from the spacer PS in plan-view, the data line 130 is disposed on the scan line 110 intersecting with the scan line 110. A part of the data line 130 is superimposed on the channel layer 120 and the scan line 110. Therefore, the data line 130 has at least one overlapping region AA which is superimposed on the scan line 110, and the data line 130 further has a first region A1 superimposed on the channel layer 120. The first region A1 is located substantially within the overlapping region AA. The overlapping region AA has the first side S1, the second side S2, the third side S3 and the fourth side S4. The boundary of the first region A1 has the third side S3, the fourth side S4, a fifth side S5, and a sixth side S6. That is, the third side S3, the fourth side S4, the fifth side S5 and the sixth side S6 are connected with one another to commonly define first region A1. The fifth side S5 is one of the sides of the first region A1 near the first side S1, and the sixth side S6 is one of the sides of the overlapping region AA near the second side S2. In practice, the fifth side S5 and the sixth side S6 are both parallel to an extension direction of the scan line 110.
When looking toward the first substrate S1 from the spacer PS in plan-view, the other part of the data line 130 is located on the scan line 110 without overlapping with the channel layer 120. Therefore, the another regions of the overlapping region AA located outside of the first region A1 further includes the second region A2 and the third region A3. The boundary of the second region A2 includes the first side S1, the third side S3, the fourth side S4 and the fifth side S4. The boundary of the third area A3 includes the second side S2, the third side S3, the fourth side S4 and the sixth side S6. The spacer PS has a first portion disposed on the first region A1, and a second portion disposed outside of the first region A1, such as on the second region A2 or the third region A3. Additionally, as illustrated in the
Since the spacer PS is partially superimposed on the first region A1 and the third area A3, the bottom portion of the spacer PS can engage with the step-difference structure of the active element array layer T1 to prevent from the deviation thereof under an external force.
In summary, a display panel is provided in the instant disclosure. The data line has an overlapping region including the first region, the second region and the third region, in which the first region has a higher surface level than that of the second region and that of the third region because the first region is superimposed on the channel layer. Accordingly, the overlapping region has at least one step-difference structure formed between the first region and the second region (or the third region). The display panel further includes the spacer having a first portion disposed on the first region and a second portion disposed on one of the second region or the third region, i.e., the spacer is arranged on the data line in alignment with the step-difference structure. As such, when the second substrate of the display panel is deformed downward under a touch pressure provided by the user, the bottom portion of the spacer is forced to engage to the step-difference structure and the sliding friction force is produced and enhanced to resist the sliding movement of the spacer. Accordingly, the abnormal rotations of the liquid crystal molecules due to the deviation of the spacer can be avoided as possible.
In addition, the channel layer can be arranged relatively distant from the pixel electrode electrically connected to the channel layer and closer to another pixel electrode insulated from the channel layer. Additionally, the pixel electrode can be arranged to partially overlap with the channel layer and a first side of the scan line. As such, it is can be avoided that the protruding portion of the pixel electrode partially overlaps with the data line during the processing procedure, and further prevent the formation of the back channel and the parasitic capacitance from increasing.
Furthermore, the scan line can have a first recessed portion, so that the overlapping region has smaller area to reduce the parasitic capacitance between the data line and the scan line. Additionally, the first recessed portion of the scan line has a relatively gentle slope to assist in forming the data line 130.
In another embodiment, the scan line can further have a second recessed portion, and the second recessed portion and the first recessed portion are respectively formed on opposite two sides of the scan line and both located at a portion of the scan line covered by the data line such that the formation of the data line on the scan line having the first and second recessed portions becomes easier. In addition, the second region and the third region have smaller areas, which results in lower parasitic capacitance between the data line 130 and the scan line.
In order to further understand the techniques, means and effects of the instant disclosure, the following detailed descriptions and appended drawings are hereby referred to, such that, and through which, the purposes, features and aspects of the instant disclosure can be thoroughly and concretely appreciated; however, the appended drawings are merely provided for reference and illustration, without any intention to be used for limiting the instant disclosure.
Number | Date | Country | Kind |
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104109335 | Mar 2015 | TW | national |