Patent Grant
12032251
The present application relates to the field of display panel technology, and in particular to a display panel.
The higher the resolution of a liquid crystal display (LCD), the more the clock signals (CK) of a gate driver on array (GOA) circuit are required. Meanwhile, there are differences in capacitance and resistance between different CK lines of 8K products, which is prone to produce horizontal line defects. In the prior art, the CK line routing design is configured to reduce the resistance difference. However, the CK line routing will increase a width of a bezel, which is not conducive to development of a narrow bezel of the liquid crystal display.
An embodiment of the present application provides a display panel, which can reduce a width of a bezel of the display panel while reducing resistance difference between clock signal traces.
An embodiment of the present application provides a display panel including a non-display area, the non-display area including a gate driver on array (GOA) unit area, a routing area, and a first wiring area arranged in a first direction; and the display panel including:
Optionally, an overlap area between each of the clock signal transfer lines and the DBS common electrode trace in the routing area is same.
Optionally, the closer the clock signal traces are to the GOA unit area, the greater a bending length of the clock signal transfer lines connected to the clock signal traces in the routing area is.
Optionally, an orthographic projection of the DBS common electrode trace on the routing area completely covers the routing area, and the DBS common electrode trace is provided with a hollow area; and
Optionally, the hollow area includes a plurality of hollow structures arranged along the second direction, and each of the clock signal transfer lines corresponds to at least one of the hollow structures; and
Optionally, the hollow area includes a plurality of hollow structures arranged along the second direction, and each of the clock signal transfer lines corresponds to one of the hollow structures; and
Optionally, the display panel further includes a color filter (CF) common electrode trace and a color filter (CF) common electrode feedback trace; and
Optionally, the non-display area further includes a second wiring area located between the GOA unit area and the routing area;
Optionally, the display panel further includes a positive signal trace, a positive signal transfer line, a negative signal trace, and a negative signal transfer line;
Optionally, the clock signal traces include a plurality of sub-lines that are cross-connected, and the plurality of sub-lines form a mesh structure.
Optionally, each of the CF common electrode trace and the CF common electrode feedback trace includes a plurality of sub-lines that are cross-connected, and the plurality of sub-lines form a mesh structure.
Optionally, the voltage trace includes a plurality of sub-lines that are cross-connected, and the plurality of sub-lines form a mesh structure.
Optionally, each of the positive signal trace and the negative signal trace includes a plurality of sub-lines that are cross-connected, and the plurality of sub-lines form a mesh structure.
Optionally, the DBS common electrode trace and the plurality of clock signal traces are arranged at a same layer.
Optionally, the CF common electrode trace, the CF common electrode feedback trace, and the clock signal trace are arranged at a same layer.
Optionally, the voltage trace and the clock signal trace are located at a same layer, and the voltage transfer line and the clock signal transfer lines are located at a same layer.
Optionally, the positive signal trace, the negative signal trace, and the clock signal traces are located at a same layer, and the positive signal transfer line, the negative signal transfer line, and the clock signal transfer lines are located at a same layer.
Beneficial effect of the present application is that a dataline black matrix less (DBS) common electrode trace is arranged in the routing area and extending along a second direction; a plurality of clock signal traces are arranged in the first wiring area along a first direction, wherein each of the clock signal traces extends along the second direction; and a plurality of clock signal transfer lines are connected to the plurality of clock signal traces in a one-to-one correspondence, wherein each of the clock signal transfer lines passes through the routing area and extends to the GOA unit area along the first direction, and at least one of the clock signal transfer lines is bent and arranged in the routing area, such that a difference in resistance between the clock signal traces is reduced through the bending of the clock signal transfer lines. Meanwhile, the DBS common electrode trace is located in the routing area to prevent disposing the DBS common electrode traces separately to increase routing space, thereby reducing a width of a bezel of a display panel.
The technical solutions and other beneficial effects of the present application will be made obvious by describing the specific implementation manners of the present application in detail below in conjunction with the accompanying drawings.
The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present application. However, the present application may be embodied in many alternative forms and should not be construed as limited to the embodiments set forth herein.
In the description of the present disclosure, it is to be understood that the terms “center”, “lateral”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside” and the like are based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the indicated devices or components must to be in particular orientations, or constructed and operated in a particular orientation, and thus are not to be construed as limiting the disclosure. Furthermore, the terms “first”, “second”, etc. in the specification and claims of the present disclosure and the above figures are used to distinguish similar objects, and are not necessarily used to describe a specific order or prioritization. It should be understood that the objects so described are interchangeable when it is appropriate. Moreover, the terms “including” and “having” and any variations thereof are intended to cover a non-exclusive “inclusion”.
In the description of this application, it should be noted that the terms “installation”, “connected”, and “connected” should be understood in a broad sense unless explicitly stated and limited otherwise. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can also be a mechanical connection or an electrical connection; it can be a direct connection; or it can be an indirect connection through an intermediate medium; or it can be a communication between two components.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments. The singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes,” “including,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, components and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
The present application will be further described below in conjunction with the drawings and embodiments.
Refer to
The display panel provided by the embodiment of the present disclosure includes a display area (not shown) and at least one non-display area 10. If the display panel adopts a single drive mode, the display panel includes one non-display area 10, and the non-display area 10 is located on one side of the display area; if the display panel adopts a dual drive mode, the display panel includes two non-display areas 10, and the two non-display areas 10 are located on opposite sides of the display area.
As shown in
The display panel includes a GOA unit (not shown), and the GOA unit is located in the GOA unit area 11. The display panel also includes a dataline black matrix less (DBS) common electrode trace 1, and the DBS common electrode trace 1 is located in the routing area 12 and extends along a second direction B. The display panel also includes a plurality of clock signal traces 2, the plurality of clock signal traces 2 are sequentially arranged in the first wiring area 13 along the first direction A, and each of the clock signal traces 2 extends along the second direction B. The DBS common electrode trace 1 and the plurality of clock signal traces 2 may be located at the same layer, that is, the DBS common electrode trace 1 and the plurality of clock signal traces 2 may be located at the first metal layer of the display panel.
The display panel also includes a plurality of clock signal transfer lines 3, a number of the plurality of clock signal transfer lines 3 and a number of the plurality of clock signal traces 2 are the same, and the plurality of clock signal transfer lines 3 and the plurality of clock signal traces 2 are in a one-to-one correspondence, wherein each of the clock signal transfer lines 3 is electrically connected to its corresponding clock signal trace 2. The plurality of clock signal transfer lines 3 and the plurality of clock signal traces 2 are located at different layers, and the plurality of clock signal transfer lines 3 may be located in the second metal layer of the display panel. An insulating layer can be arranged between the first metal layer and the second metal layer, the insulating layer is provided with via holes, the via holes are filled with conductive material, and each of the clock signal transfer lines 3 passes through the conductive material in the via hole to electrically connect to its corresponding clock signal trace 2.
After each of the clock signal transfer lines 3 is electrically connected to its corresponding clock signal trace 2, it extends in the first direction A through the routing area 12, and continues to extend to the GOA unit area 11 in the first direction A, so as to electrically connect to GOA units in the GOA unit area 11, so that each of the clock signal traces 2 is electrically connected to the GOA unit through its corresponding clock signal transfer line 3.
Since the plurality of clock signal traces 2 are arranged along the first direction A, distances between the plurality of clock signal traces 2 and the GOA unit area 11 are different, and if the plurality of clock signal transfer lines 3 are arranged in a straight line, it will cause a difference in length between the clock signal transfer lines 3, wherein the clock signal transfer line 3 connected to the clock signal trace 2 near the GOA unit area 11 is shorter, and the clock signal transfer line 3 connected to the clock signal trace 2 far away from the GOA unit area 11 is longer. That is, there is a large difference in lengths between the clock signal traces that transmit clock signals (including the clock signal traces 2 and the clock signal transfer lines 3 connected to the clock signal traces 2), which in turn leads to a difference in resistance between the clock signal traces, and this is prone to produce horizontal line defects. Therefore, in the present application, a routing area 12 is provided, and at least one clock signal transfer line 3 is bent and arranged in the routing area 12 to adjust the length of each of the clock signal transfer lines 3 and reduce the difference in resistance between the clock signal traces that transmit clock signals, thereby reducing the occurrence of defective horizontal lines.
Specifically, the clock signal transfer line 3 connected to the clock signal trace 2 farthest from the GOA unit area 11 may not be bent in the routing area 12, that is, the clock signal transfer line 3 may be linear, as shown in
If an additional routing area 12 is added to the non-display area 10, and a design of other traces remains unchanged, such as the DBS common electrode trace 1, the plurality of clock signal traces 2, and the routing area arranged side by side in the non-display area 10, this will cause a width of the non-display area 10 to increase, as shown in
Since each of the clock signal transfer lines 3 extends through the routing area 12 along the first direction A, and the DBS common electrode trace 1 is located in the routing area 12 and extends along the second direction B, each of the clock signal transfer lines 3 overlaps the DBS common electrode trace 1 in the routing area 12. This overlap means that an orthographic projection of each of the clock signal transfer lines 3 on the routing area 12 overlaps an orthographic projection of the DBS common electrode trace 1 on the routing area 12, and does not means that the clock signal transfer line 3 covers the DBS common electrode line 1. An overlap area of each of the clock signal transfer lines 3 and DBS common electrode line 1 in the routing area 12 is the same, that is, an overlap area of the orthographic projection of each of the clock signal transfer lines 3 on the routing area 12 and the orthographic projection of the DBS common electrode trace 1 on the routing area 12 is the same. The overlap portion of the clock signal transfer line 3 and the DBS common electrode trace 1 can form a capacitor. By adjusting the overlap area of the clock signal transfer line 3 and the DBS common electrode trace 1, the size of the capacitor can be adjusted to improve the difference in capacitance between the clock signal traces, thereby reducing occurrence of defective horizontal lines.
The orthographic projection of the DBS common electrode trace 1 on the routing area 12 can partially cover the routing area 12. The bending lengths of the different clock signal transition lines 3 in the routing area 12 can be different, but the overlap area between each of the clock signal transition lines 3 and the DBS common electrode trace 1 in the routing area 12 can be the same, as shown in
The orthographic projection of the DBS common electrode trace 1 on the routing area 12 can completely cover the routing area 12, and the DBS common electrode trace 1 is provided with a hollow area. The closer the clock signal traces 2 are to the GOA unit area 11, the larger an overlap area between the clock signal transfer lines 3 connected to the clock signal traces 2 and the hollow area is. Alternatively, the clock signal transfer line 3 connected to the clock signal trace 2 farthest from the GOA unit area 11 may not overlap with the hollow area, and the other clock signal transfer lines 3 are bent and arranged in the routing area 12 and can all overlap with the hollow area. Moreover, the longer the bending length of the clock signal transfer line 3 in the routing area 12, the larger the overlap area between the clock signal transfer line 3 and the hollow area is, so as to adjust the overlap area between each of the clock signal transfer lines 3 and the DBS common electrode trace 1, thereby reducing the difference in capacitance between the clock signal traces.
In one embodiment, as shown in
As shown in
In another embodiment, as shown in
Furthermore, as shown in
Furthermore, as shown in
Furthermore, as shown in
The negative signal trace 91 is connected to the at least one negative signal transfer line 92, and each negative signal transfer line 92 extends along the first direction A to the GOA unit area 11 to electrically connect to the GOA unit, so that the negative signal trace 91 is electrically connected to the GOA unit through at least one negative signal transfer line 92. The negative signal transfer line 92 and the negative signal trace 91 are located at different layers, and the negative signal trace 91 may be located at the same layer as the plurality of clock signal traces 2, that is, the negative signal trace 91 may be located at the first metal layer. The negative signal transfer line 92 may be located at the same layer as the plurality of clock signal transfer lines 3, that is, the negative signal transfer line 92 may be located in the second metal layer. The insulating layer between the first metal layer and the second metal layer may be provided with a plurality of via holes, the via holes are filled with conductive material, and the negative signal transfer line 92 can be electrically connected to the negative signal trace 91 through the conductive material in the via hole. The negative signal trace 91 and the negative signal transfer line 92 are configured to transmit negative signals to the GOA unit.
When the display panel is an 8K display panel, the display panel includes twelve clock signal traces 2, twelve clock signal transfer lines 3, twelve voltage transfer lines 72, six positive signal transfer lines 82, and six negative signal transfer line 92. The twelve clock signal traces 2 and twelve clock signal transfer lines 3 are electrically connected to each other in a one-to-one correspondence, and the twelve clock signal transfer lines 3 are respectively electrically connected to the GOA units. The twelve voltage transfer lines 72 are respectively electrically connected to the voltage trace 71, and the twelve voltage transfer lines 72 are also respectively electrically connected to the GOA units; the six positive signal transfer lines 82 are respectively electrically connected to the positive signal trace 81, and the six positive signal transfer lines 82 are also electrically connected to the GOA units; the six negative signal transfer lines 92 are respectively electrically connected to the negative signal traces 91, and the six negative signal transfer lines 92 are also respectively connected to the GOA units.
Further, each of the clock signal traces 2, the CF common electrode traces 5, the CF common electrode feedback traces 6, the voltage traces 71, the positive signal traces 81, and the negative signal traces 91 may be a solid line, as shown in
In summary, in an embodiment of the present application, a dataline black matrix less (DBS) common electrode trace is arranged in the routing area and extending along a second direction; a plurality of clock signal traces are arranged in the first wiring area along a first direction, wherein each of the clock signal traces extends along the second direction; and a plurality of clock signal transfer lines are connected to the plurality of clock signal traces in a one-to-one correspondence, wherein each of the clock signal transfer lines passes through the routing area and extends to the GOA unit area along the first direction, and at least one of the clock signal transfer lines is bent and arranged in the routing area, such that a difference in resistance between the clock signal traces is reduced through bending the clock signal transfer lines. Meanwhile, the DBS common electrode trace is located in the routing area to prevent disposing the DBS common electrode traces separately to increase routing space, thereby reducing a width of a bezel of a display panel.
While the disclosure has been described by way of example and in terms of the preferred embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110600442.X | May 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/103171 | 6/29/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/252323 | 12/8/2022 | WO | A |
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| Number | Date | Country | |
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| 20240012299 A1 | Jan 2024 | US |
