Patent Application
20250176263
This application claims priority to and the benefit of Chinese Patent Application No. 202311621711.6, filed on Nov. 28, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to display technologies, and in particular to display panels and manufacturing method of the display panels.
Oxide semiconductors have high mobility and can replace amorphous silicon (a-Si) for preparing high-performance (such as high refresh rate and high resolution) liquid crystal display (LCD) panels. Moreover, the oxide semiconductors have significant cost advantages compared to low temperature polysilicon (LTPS), and therefore the oxide semiconductors are widely used in the display panels.
However, a preparation of an oxide backplate requires more masks, especially in high transmission fringe field switching (HFS) display modes, the oxide backplate generally requires at least 6 mask processes, making the process complex and production costs high.
The embodiments of the present disclosure provide a display panel. The display panel includes a substrate, a first device layer, a second device layer, and a third device layer. The first device layer is disposed on the substrate and includes a gate. The second device layer is disposed on a side of the first device layer away from the substrate. The second device layer includes an active part and a pixel electrode. The active part and the pixel electrode are disposed on a side of the gate away from the substrate. A third device layer is disposed on a side of the second device layer away from the first device layer. The third device layer includes a source disposed on a side of the active part away from the gate. The source is connected to the active part. The display panel further includes a drain. The drain is electrically connected to the pixel electrode and the active part.
The embodiments of the present disclosure further provide a manufacturing method of the display panel, including the following steps.
A substrate is provided.
A first device layer is formed on the substrate. The first device layer includes a gate.
A second device layer is formed on a side of the first device layer away from the substrate, and a third device layer is formed on a side of the second device layer away from the first device layer. The second device layer includes an active part and a pixel electrode disposed on a side of the gate away from the substrate. The third device layer includes a source disposed on a side of the active part away from the gate, and the source is connected to the active part.
The manufacturing method further includes: forming a drain. The drain is electrically connected to the pixel electrode and the active part.
Based on the accompanying drawings, a detailed description of the specific implementation of the present disclosure will make the technical solution and other beneficial effects of the present disclosure obvious.
The technical solutions in the embodiments of the present disclosure will be described clearly and completely hereafter with reference to the accompanying drawings. Apparently, the described embodiments are only a part of but not all embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.
Various embodiments and examples are provided in the following description to implement different structures of the present disclosure. In order to simplify the present disclosure, certain elements and settings will be described. However, these elements and settings are only by way of example and are not intended to limit the present disclosure. In addition, reference numerals may be repeated in different examples in the present disclosure. This repeating is for the purpose of simplification and clarity and does not refer to relations between different embodiments and/or settings. Furthermore, examples of different processes and materials are provided in the present disclosure. However, it would be appreciated by those skilled in the art that other processes and/or materials may be also applied.
Referring to
The first device layer 20 is disposed on the substrate 10. The first device layer 20 includes a gate 21. The second device layer 30 is disposed on a side of the first device layer 20 away from the substrate 10. The second device layer 30 includes an active part 31 and a pixel electrode 32 disposed on a side of the gate 21 away from the substrate 10. The third device layer 40 is disposed on a side of the second device layer 30 away from the first device layer 20. The third device layer 40 includes a source 41 disposed on a side of the active part 31 away from the gate 21. The source 41 is connected to the active part 31.
Furthermore, the display panel further includes a drain 42. The drain is electrically connected to the pixel electrode 32 and the active part 31.
In the implementation and application process, the pixel electrodes 32 and the active parts 31 are formed in a same film layer in the embodiments of the present disclosure, which may reduce the number of photomasks and simplify the process, and thereby reducing production costs.
Continuing to refer to
Specifically, the array layer includes the first device layer 20, a gate insulation layer 61, the second device layer 30, the third device layer 40, an organic insulation layer 62, an inorganic insulation layer 63, and a fourth device layer. The gate insulation layer 61 is disposed on the side of the first device layer 20 away from the substrate 10 and covers the first device layer 20. The second device layer 30 is disposed on a side of the gate insulation layer 61 away from the first device layer 20. The third device layer 40 is disposed on the side of the second device layer 30 away from the gate insulation layer 61. The organic insulation layer 62 is disposed on a side of the third device layer 40 away from the second device layer 30. The inorganic insulation layer 63 is disposed on a side of both the organic insulation layer 62 and the third device layer 40 away from the substrate 10. The fourth device layer 50 is disposed on a side of the inorganic insulation layer 63 away from the organic insulation layer 62.
The first device layer 20 includes a gate 21 and a first signal line 22 disposed on the substrate 10. The gate 21 is used to form a thin film transistor, and the first signal line 22 may be used to transmit signals to the thin film transistor.
The gate insulation layer 61 covers the gate 21 and the first signal line 22.
The second device layer 30 includes an active part 31. The active part 31 is disposed on a side of the gate 21 away from the substrate 10. The third device layer 40 includes a source 41 and a drain 42, a data line 44, and a second signal line 43. The source 41 and the drain 42 are disposed on a side of the active part 31 away from the gate 21, and connected to opposite ends of the active part 31. The data line 44 is connected to the source 41. The organic insulation layer 62 covers a surface of the source 41 away from the substrate 10, and a surface of the data line 44 away from the substrate 10. The inorganic insulation layer 63 covers the active part 31, the organic insulation layer 62, and the drain 42. The gate 21, the active part 31, the source 41, and the drain 42 form the thin film transistor.
The fourth device layer 50 includes a common electrode 51 and an adapter part 52. The common electrode 51 and the adapter part 52 are disposed on a side of the inorganic insulation layer 63 away from the substrate 10. One end of the adapter part 52 is connected to a second signal line 43, and other end of the adapter part 52 passes through the inorganic insulation layer 63 and the gate insulation layer 61 and is connected to the first signal line 22. The display panel includes a display area, a non-display area adjacent to the display area, and a driving circuit unit disposed in the non-display area. One end of the second signal line 43 is connected to the driving circuit unit, and other end of the second signal line 43 is connected to the adapter part 52.
Materials of the first device layer 20 and the third device layer 40 may both be transparent conductive materials. A material of the fourth device layer 50 may be a transparent conductive material, such as indium tin oxide.
In an embodiment, the driving circuit unit is a gate driver on array (GOA) gate driving circuit unit. The second signal line 43 may be used to transmit a scanning signal from the GOA gate driving circuit unit to the display area and transmit the scanning signal to the gate 21 through the first signal line 22.
In the embodiment of the present disclosure, the second device layer 30 further includes a pixel electrode 32, that is, the active part 31 and the pixel electrode 32 belong to a same film layer. However, the active part 31 is a semiconductor, and the pixel electrode 32 is a conductor. For example, a semiconductor material may be used to prepare the second device layer 30, and an area corresponding to the pixel electrode 32 may be performed a conductive treatment to maintain the semiconductor characteristics of the active part 31 and maintain the conductor characteristics of the pixel electrode 32 to achieve conductivity function. One end of the drain 42 is connected to the active part 31, and other end of the drain 42 is connected to the pixel electrode 32 to transmit signals from the thin film transistor to the pixel electrode 32. Specifically, the active part 31 includes a channel. The source 41 and the drain 42 are respectively connected to the opposite ends of the channel, and the channel is disposed on a side of the gate 21 away from the substrate 10.
It should be noted that although the active part 31 is connected to the pixel electrode 32, a part between the channel of the active part 31 and the pixel electrode 32 is not directly conductive in the embodiments of the present disclosure to avoid the direct conduction between the pixel electrode 32 and the channel. This avoids the direct conductive treatment to the part between the channel of the active part 31 and the pixel electrode 32, which may affect the channel, and the difficulty of the process and the demand for process accuracy are reduced. Therefore, in the embodiments of the present disclosure, the source 41 and the drain 42 are formed in other film layers and are connected to both ends of the channel of the active part 31, which may achieve control signal on/off and ensure the yield of the active part 31.
In an embodiment, the active part 31 is an oxide semiconductor, and the pixel electrode 32 is an oxide conductor. Specifically, the material of the active part 31 includes indium gallium zinc oxide, and the pixel electrode 32 may be an oxide conductor formed by conductive treatment of indium gallium zinc oxide. After the conductive treatment, the pixel electrode 32 may reduce its resistance and improve its transmittance.
It can be understood that in the embodiment of the present disclosure, the pixel electrode 32 and the active part 31 are prepared in a same process, which may save one mask process, simplify the process, and reduce costs.
In an embodiment, the inorganic insulation layer 63 may be a stacked structure of multiple sublayers, and the inorganic insulation layer 63 includes an oxide sublayer close to the substrate 10. The oxide sublayer is in contact with the active part 31, and the active part 31 may be oxygenated to repair internal oxygen vacancies and improve the stability of the thin film transistor. A material of the oxide sublayer may include silicon oxide, and materials of other sublayers of the inorganic insulation layer 63 may include silicon oxide and/or silicon nitride.
In an embodiment, the source 41 is connected to the active part 31, and the drain 42 is connected between the active part 31 and the pixel electrode 32. Specifically, the drain 42 is disposed on a surface of the active part 31 away from the gate 21 and extends to a surface of the pixel electrode 32 away from the substrate 10 to achieve electrical connection between the active part 31 and the pixel electrode 32.
It should be noted that the display panel provided by the embodiments of the present disclosure may be a liquid crystal display panel. The display panel further includes a color film substrate (not shown in the figures) disposed on a side of the array layer away from the substrate 10, and a liquid crystal layer disposed between the array layer and the color film substrate. An electric field may be formed between the common electrode 51 and the pixel electrode 32 to drive the deflection of liquid crystal molecules in the liquid crystal layer.
In an embodiment, the common electrode 51 is disposed on the inorganic insulation layer 63. A plurality of openings are defined in an area of the common electrode 51 corresponding to the pixel electrode 32 to expose the pixel electrode 32. The common electrode 51 may cover areas other than the openings, thereby forming a horizontal electric field between the pixel electrode 32 and the common electrode 51.
An orthographic projection of the source 41 on the substrate 10 and an orthographic projection of the data line 44 on the substrate 10 both overlap an orthographic projection of the common electrode 51 on the substrate 10. Moreover, since the organic insulation layer 62 covers the data line 44 and the source 41, the organic insulation layer 62 is disposed between the common electrode 51 and the data line 44, and between the common electrode 51 and the source 41. The organic insulation layer 62 may increase a distance between the common electrode 51 and the data line 44, and a distance between the common electrode 51 and the source 41, thereby reducing a parasitic capacitance generated between the common electrode 51 and the data line 44, and a parasitic capacitance generated between the common electrode 51 and the source 41.
In an embodiment, a color of the organic insulation layer 62 is black. For example, black photoresist may be used to prepare the organic insulation layer 62, which may effectively reduce the reflection of light by the third device layer 40, thereby improving the contrast and display effect of the display panel.
Furthermore, an orthographic projection of the organic insulation layer 62 on the substrate 10 is in an orthographic projection of the source 41 and the data line 44 on the substrate 10. Therefore, the organic insulation layer 62 can be aligned or inward contracted on both sides of the source 41 and the data line 44, and will not form an eaves structure on both sides of the source 41 and the data line 44. As the inorganic insulation layer 63 is deposited on the side of the organic insulation layer 62 away from the substrate 10, the membrane continuity of the inorganic insulation layer 63 on both sides of the source 41 and data line 44 can be improved, avoiding the occurrence of fracture and discontinuity of the inorganic insulation layer 63 during the deposition process due to the generation of eaves structure.
In another embodiment of the present disclosure, referring to
One end of the connection electrode 53 is connected to the drain 42, and other end of the connection electrode 53 is connected to the pixel electrode 32 by passing through a via hole of the inorganic insulation layer 63. One end of the drain 42 is connected to the active part 31 by passing through a via hole of the inorganic insulation layer 63, and other end of the drain 42 is connected to the connection electrode 53.
In the embodiment, the connection electrode 53 is electrically insulated from the common electrode 51, that is, the connection electrode 53 is spaced apart from the common electrode 51, and the active part 31 is spaced apart from the pixel electrode 32.
Furthermore, the connection electrode 53 may be integrally formed with the drain 42, or the connection electrode 53 and the drain 42 may be prepared in two separate processes, respectively.
In another embodiment of the present disclosure, referring to
It can be understood that in the embodiment, the part between the connection between the active part 31 and the drain 42 and the pixel electrode 32 is a semiconductor, and has not been conductive. In addition, the channel of the active part 31 is connected to the pixel electrode 32 through the drain 42, to avoid the channel being conductive due to limitations such as process accuracy during the conductive processing of the part between the connection between the active part 31 and the drain 42 and the pixel electrode 32, Furthermore, the yield of the active part 31 can be improved.
In another embodiment of the present disclosure, referring to
The drain 42 may be a conductor obtained by conducting semiconductor materials.
Furthermore, in the embodiment of the present disclosure, the pixel electrode 32 and the active part 31 are formed in the same film layer, which may reduce the number of photomasks, simplify the process, and thus reduce production costs.
In addition, the embodiments of the present disclosure further provide a manufacturing method of the display panel. Referring to
At step S10, the substrate of 10 is provided.
At step S20, the first device layer 20 is formed on the substrate 10. The first device layer 20 includes the gate 21.
At step S30, the second device layer 30 is formed on the side of the first device layer 20 away from the substrate 10, and the third device layer 40 is formed on the side of the second device layer 30 away from the first device layer 20. The second device layer 30 includes the active part 31 and the pixel electrodes 32 disposed on the side of the gate 21 away from the substrate 10. The third device layer 40 includes the source 41 disposed on the side of the active part 31 away from the gate 21, and the source 41 is connected to the active part 31.
Furthermore, the manufacturing method of the display panel further includes: forming the drain 42. The drain 42 is electrically connected to the pixel electrode 32 and the active part 31.
Specifically, in an embodiment of the present disclosure, continuing to refer to
In step S20, a first conductive material layer is formed on the substrate 10. In an embodiment, the first conductive material layer may be made of a conductive metal material.
Then, the first conductive material layer is etched to obtain a patterned structure, resulting in the first device layer 20. The gate 21 and a first signal line 22 are formed in the first device layer 20.
Referring to
In an embodiment, the material of the gate insulation layer 61 includes at least one of silicon oxide and silicon nitride. The semiconductor material layer 301 may include an oxide semiconductor, such as indium gallium zinc oxide. The material of the second conductive material layer 401 may include a conductive metal.
In the embodiment of the present disclosure, a multi-tone mask may be used to pattern the semiconductor material layer 301 and the second conductive material layer 401 to form the second device layer 30 and the third device layer 40.
As shown in
In an embodiment, a material of the photoresist layer 70 includes a positive photoresist. In the multi-tone mask, a transmittance at a position corresponding to the second photoresist part 72 is greater than that at a position corresponding to the third photoresist part 73. The position corresponding to the second photoresist part 72 is a semi-transparent area. The position corresponding to the first photoresist part 71 is opaque. Other areas of the multi-tone mask not covering the photoresist layer 70 is fully transparent to remove the positive photoresist material corresponding to the other areas.
It should be noted that the first photoresist part 71 may cover an area used to form the source 41 and the data line 44. The second photoresist part 72 may cover an area used to form the active part 31 and the pixel electrode 32. The third photoresist part 73 may cover an area used to form the drain 42.
As shown in
As shown in
In an embodiment, the second photoresist part 72 may be removed by an O2 ashing process, while a part of the first photoresist part 71 and a part of the third photoresist part 73 are simultaneously removed.
As shown in
In an embodiment, the second conductive material layer 401 includes a conductive metal material, and Cu acid may be used to etch the second conductive material layer 401.
As shown in
It should be pointed out that the gate 21, the active part 31, the source 41, and the drain 42 form the thin film transistor. In the step shown in
As shown in
In an embodiment, the ashing process may be used to remove the first photoresist part 71 and a part of the first photoresist part 71.
In an embodiment, the photoresist layer 70 is a black photoresist. Therefore, when the organic insulation layer 62 covers the surface of the source 41 and the data line 44, the reflection of light by the third device layer 40 can be reduced, which can effectively improve the contrast and display effect of the display panel.
As shown in
It should be noted that due to the adjustment of the structure of the organic insulation layer 62 in the embodiment of the present disclosure, the eaves structure of the first photoresist part 71 on both sides of the source 41 and the data line 44 is removed, so that the oxide sublayer 631 can better cover the sides of the source 41 and data line 44, reducing the probability of fracture and discontinuity of the oxide sublayer 631 on the sides of the source 41 and the data line 44.
As shown in
In an embodiment, a material of the protective layer 80 may include photoresist.
As shown in
It should be noted that in the embodiment of the present disclosure, before conducting the conductive treatment on the intermediate electrode portion 321, the oxide sublayer 631 is first deposited, thereby avoiding the increase in resistance of the pixel electrode 32 caused by the deposition of oxide material after the conductive treatment, and improving the display effect of the display panel.
As shown in
As shown in
As shown in
In an embodiment, the driving circuit unit is the GOA gate driving circuit unit, and the second signal line 43 may be used to transmit the scanning signal from the GOA gate driving circuit unit to the display area and transmit it to the gate 21 through the first signal line 22.
It should be noted that an orthographic projection of the source 41 on substrate 10 and an orthographic projection of the data line 44 on the substrate 10 both overlap the orthographic projection of the common electrode 51 on the substrate 10. Additionally, due to the organic insulation layer 62 covering the data line 44 and the source 41, the organic insulation layer 62 is disposed between the common electrode 51 and the data line 44, as well as between common electrode 51 and source 41. Furthermore, the organic insulation layer 62 can increase the distance between the common electrode 51 and the data line 44, as well as the distance between the common electrode 51 and the source 41, thereby reducing the parasitic capacitance generated between the common electrode 51 and the data line 44, as well as the parasitic capacitance generated between the common electrode 51 and the source 41.
In the manufacturing method of the display panel provided in the embodiment of the present disclosure, the patterning of the first conductive material layer involves a first mask process. The patterning of the semiconductor material layer 301 and the second conductive material layer 401 involves a second mask process. The secondary patterning of the second conductive material layer 401 to form the source 41 and the drain 42 involves a third mask process. The patterning of the inorganic insulation layer 63 and the gate insulation layer 61 to define the openings involves a fourth mask process. The patterning of the third conductive material layer to obtain the fourth device layer 50 involves the fifth mask process. In the embodiment of the present disclosure, the array layer of the display panel is prepared by five mask processes, simplifying the process flow and reducing process costs.
In the embodiments of the present disclosure, the active part 31 and the pixel electrode 32 are prepared in the same film layer, which can save the number of photomasks. In additional, a multi-tone mask is used to pattern the semiconductor material layer 301 and the second conductive material layer 401, so that the remaining first photoresist part 71 may form the organic insulation layer 62. The organic insulation layer 62 is disposed between the source 41 and the common electrode 51, as well as between the data line 44 and the common electrode 51, to reduce the parasitic capacitance generated between the common electrode 51 and the data line 44, as well as the parasitic capacitance generated between the common electrode 51 and the source 41. Furthermore, the organic insulation layer 62 may be made of the black photoresist, which can reduce the reflection of light by the source 41 and the data line 44, thereby improving the contrast and display effect of the display panel.
In another embodiment of the present disclosure, referring to
In addition, in the embodiment, when patterning the semiconductor material layer 301, due to the lack of coverage of the drain 42, the connection part between the active part 31 and the pixel electrode 32 can be etched and removed, so that the active part 31 and the pixel electrode 32 are spaced apart.
In another embodiment of the present disclosure, referring to
In another embodiment of the present disclosure, referring to
In addition, the embodiments of the present disclosure further provide a display device, which includes the display panel as described in the above embodiments. Therefore, the display device provided in the embodiments of the present disclosure has the same beneficial effect as the display panel as described in the above embodiments, and will not be further described here.
In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not detailed in one embodiment, please refer to the relevant descriptions of other embodiments.
The display panel and the manufacturing method thereof provided in the embodiments of the present disclosure are described in detail above. The principle and implementations of the present disclosure are described in this specification by using specific examples. The description about the foregoing embodiments is merely provided to help understand the method and core ideas of the present disclosure. In addition, those skilled in the art can make modifications in terms of the specific implementations and application scopes according to the ideas of the present disclosure. Therefore, the content of this specification shall not be construed as a limit to the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311621711.6 | Nov 2023 | CN | national |
