Patent Grant
11900873
This application is a national stage of international PCT Application No. PCT/CN2021/076326, filed on Feb. 9, 2021, which claims priority to Chinese patent application No. 202010328502.2 entitled “DISPLAY PANELS, METHODS OF DRIVING THE SAME, AND DISPLAY DEVICES”, filed with the Chinese Patent Office on Apr. 23, 2020, the entire contents of which are incorporated herein by reference.
This application relates to the field of display technologies, and in particular, to display panels, methods for driving the same, and display devices.
LCD (Liquid Crystal Display) and active matrix OLED (Organic Light-Emitting Diode) are relatively mature in the field of display. The principle of an OLED display device is to excite spectra with various wavelengths by electron-hole recombination to form a graphic.
Generally, the OLED display device includes a display panel, a gate drive apparatus, a data driver, and a timing controller. The display panel includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels controlled by the two former ones. The usual working mode is in a case that a gate drive signal is provided to a gate line, a plurality of pixels in a same row are provided with data voltages, and then emit light of various brightness according to the magnitude of the data voltages.
A pixel may include a pixel circuit. If the pixel circuit has a complex structure, and occupies a relatively large area, a display resolution or a light-emitting area of the pixel will be affected.
The present application provides display panels, methods for driving the same, and display devices.
According to a first aspect of embodiments of the present application, a display panel is provided, including: a first pixel circuit, a first multiplexing signal line, and a demultiplexing circuit, where the first pixel circuit includes a first reset circuit, a first data writing circuit, a first storage circuit, and a first drive circuit, where a first terminal of the first reset circuit is connected to a first terminal of the first drive circuit, a second terminal of the first reset circuit is connected to the first multiplexing signal line, the first terminal of the first drive circuit is further connected to a first light-emitting element, a control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit, a second terminal of the first data writing circuit is connected to the first multiplexing signal line, a first terminal of the first storage circuit is connected to the control terminal of the first drive circuit, and a second terminal of the first storage circuit is connected to the first terminal of the first drive circuit; and the demultiplexing circuit includes a first control circuit and a second control circuit, where a first terminal of the first control circuit is connected to the first multiplexing signal line, a second terminal of the first control circuit is used for receiving a reset signal, a first terminal of the second control circuit is connected to the first multiplexing signal line, and a second terminal of the second control circuit is used for receiving a first data signal.
In an embodiment, the display panel further includes: a second pixel circuit and a second multiplexing signal line, where the second pixel circuit includes a second reset circuit, a second data writing circuit, a second storage circuit and a second drive circuit, where a first terminal of the second reset circuit is connected to a first terminal of the second drive circuit, a second terminal of the second reset circuit is connected to the second multiplexing signal line, the first terminal of the second drive circuit is further connected to a second light-emitting element, a control terminal of the second drive circuit is connected to a first terminal of the second data writing circuit, a second terminal of the second data writing circuit is connected to the second multiplexing signal line, a first terminal of the second storage circuit is connected to the control terminal of the second drive circuit, and a second terminal of the second storage circuit is connected to the first terminal of the second drive circuit; the demultiplexing circuit further includes a third control circuit and a fourth control circuit, where a first terminal of the third control circuit is connected to the second multiplexing signal line, a second terminal of the third control circuit is used for receiving the reset signal, a first terminal of the fourth control circuit is connected to the second multiplexing signal line, and a second terminal of the fourth control circuit is used for receiving a second data signal.
In an embodiment, the display panel further includes: a reset signal line and a data signal line, where the second terminal of the first control circuit and the second terminal of the third control circuit are connected in parallel, and further connected to the reset signal line; and the second terminal of the second control circuit and the second terminal of the fourth control circuit are connected in parallel, and further connected to the data signal line.
In an embodiment, the display panel further includes: a first control signal line, a second control signal line, and a third control signal line, where a control terminal of the first control circuit and a control terminal of the third control circuit are respectively connected to the first control signal line, a control terminal of the second control circuit is connected to the second control signal line, and a control terminal of the fourth control circuit is connected to the third control signal line.
In an embodiment, the first control circuit includes a first transistor, a first terminal of the first transistor is the first terminal of the first control circuit, a second terminal of the first transistor is the second terminal of the first control circuit, and a control terminal of the first transistor is the control terminal of the first control circuit; the second control circuit includes a second transistor, where a first terminal of the second transistor is the first terminal of the second control circuit, and a second terminal of the second transistor is the second terminal of the second control circuit, and a control terminal of the second transistor is the control terminal of the second control circuit; the third control circuit includes a third transistor, where a first terminal of the third transistor is the first terminal of the third control circuit, a second terminal of the third transistor is the second terminal of the third control circuit, and a control terminal of the third transistor is the control terminal of the third control circuit; the fourth control circuit includes a fourth transistor, where a first terminal of the fourth transistor is the first terminal of the fourth control circuit, a second terminal of the fourth transistor is the second terminal of the fourth control circuit, and a control terminal of the fourth transistor is the control terminal of the fourth control circuit.
In an embodiment, the first transistor is an N-type transistor, where the first terminal of the first transistor is a source electrode, the second terminal of the first transistor is a drain electrode, and the control terminal of the first transistor is a gate electrode; the second transistor is an N-type transistor, where the first terminal of the second transistor is a source electrode, the second terminal of the second transistor is a drain electrode, and the control terminal of the second transistor is a gate electrode; the third transistor is an N-type transistor, where the first terminal of the third transistor is a source electrode, the second terminal of the third transistor is a drain electrode, and the control terminal of the third transistor is a gate electrode; the fourth transistor is an N-type transistor, where the first terminal of the fourth transistor is a source electrode, the second terminal of the fourth transistor is a drain electrode, and the control terminal of the fourth transistor is a gate electrode.
In an embodiment, the display panel further includes: a first gate line and a second gate line, where a control terminal of the first reset circuit and a control terminal of the second reset circuit are respectively connected to the first gate line; a control terminal of the first data writing circuit and a control terminal of the second data writing circuit are respectively connected to the second gate line.
In an embodiment, the first pixel circuit further includes a first compensation circuit, a first terminal of the first compensation circuit is connected to the control terminal of the first drive circuit, a second terminal of the first compensation circuit is connected to a power signal line, and the power signal line is used for providing a reference voltage signal; the second pixel circuit further includes a second compensation circuit, a first terminal of the second compensation circuit is connected to the control terminal of the second drive circuit, and a second terminal of the second compensation circuit is connected to the power signal line.
In an embodiment, the display panel further includes: a third gate line, where a control terminal of the first compensation circuit and a control terminal of the second compensation circuit are respectively connected to the third gate line.
In an embodiment, the first reset circuit includes a fifth transistor, where a first terminal of the fifth transistor is the first terminal of the first reset circuit, a second terminal of the fifth transistor is the second terminal of the first reset circuit, and a control terminal of the fifth transistor is the control terminal of the first reset circuit; the first compensation circuit includes a sixth transistor, where a first terminal of the sixth transistor is the first terminal of the first compensation circuit, a second terminal of the sixth transistor is the second terminal of the first compensation circuit, and a control terminal of the sixth transistor is the control terminal of the first compensation circuit; the first data writing circuit includes a seventh transistor, where a first terminal of the seventh transistor is the first terminal of the first data writing circuit, a second terminal of the seventh transistor is the second terminal of the first data writing circuit, and a control terminal of the seventh transistor is the control terminal of the first data writing circuit; the first drive circuit includes an eighth transistor, where a first terminal of the eighth transistor is the first terminal of the first drive circuit, a second terminal of the eighth transistor is a second terminal of the first drive circuit, and a control terminal of the eighth transistor is the control terminal of the first drive circuit; the first storage circuit includes a first capacitor, a first terminal of the first capacitor is the first terminal of the first storage circuit, and a second terminal of the first capacitor is the second terminal of the first storage circuit; the second reset circuit includes a ninth transistor, where a first terminal of the ninth transistor is the first terminal of the second reset circuit, a second terminal of the ninth transistor is the second terminal of the second reset circuit, and a control terminal of the ninth transistor is the control terminal of the second reset circuit; the second compensation circuit includes a tenth transistor, where a first terminal of the tenth transistor is the first terminal of the second compensation circuit, a second terminal of the tenth transistor is the second terminal of the second compensation circuit, and a control terminal of the tenth transistor is the control terminal of the second compensation circuit; the second data writing circuit includes an eleventh transistor, where a first terminal of the eleventh transistor is the first terminal of the second data writing circuit, a second terminal of the eleventh transistor is the second terminal of the second data writing circuit, and a control terminal of the eleventh transistor is the control terminal of the second data writing circuit; the second drive circuit includes a twelfth transistor, where a first terminal of the twelfth transistor is the first terminal of the second drive circuit, a second terminal of the twelfth transistor is a second terminal of the second drive circuit, and a control terminal of the twelfth transistor is the control terminal of the second drive circuit; the second storage circuit includes a second capacitor, where a first terminal of the second capacitor is the first terminal of the second storage circuit, and a second terminal of the second capacitor is the second terminal of the second storage circuit.
In an embodiment, the fifth transistor is an N-type transistor, the first terminal of the fifth transistor is a source electrode, the second terminal of the fifth transistor is a drain electrode, and the control terminal of the fifth transistor is a gate electrode; the sixth transistor is an N-type transistor, the first terminal of the sixth transistor is a source electrode, the second terminal of the sixth transistor is a drain electrode, and the control terminal of the sixth transistor is a gate electrode; the seventh transistor is an N-type transistor, the first terminal of the seventh transistor is a source electrode, the second terminal of the seventh transistor is a drain electrode, and the control terminal of the seventh transistor is a gate electrode; the eighth transistor is an N-type transistor, the first terminal of the eighth transistor is a source electrode, the second terminal of the eighth transistor is a drain electrode, and the control terminal of the eighth transistor is a gate electrode; the ninth transistor is an N-type transistor, the first terminal of the ninth transistor is a source electrode, the second terminal of the ninth transistor is a drain electrode, and the control terminal of the ninth transistor is a gate electrode; the tenth transistor is an N-type transistor, the first terminal of the tenth transistor is a source electrode, the second terminal of the tenth transistor is a drain electrode, and the control terminal of the tenth transistor is a gate electrode; the eleventh transistor is an N-type transistor, the first terminal of the eleventh transistor is a source electrode, the second terminal of the eleventh transistor is a drain electrode, and the control terminal of the eleventh transistor is a gate electrode; the twelfth transistor is an N-type transistor, the first terminal of the twelfth transistor is a source electrode, the second terminal of the twelfth transistor is a drain electrode, and the control terminal of the twelfth transistor is a gate electrode.
In an embodiment, the display panel includes: a display region and a peripheral region, where the peripheral region is adjacent to the display region, the first pixel circuit is located in the display region, and the demultiplexing circuit is located in the peripheral region.
According to a second aspect of the embodiments of the present application, a display device is provided, including: a display panel as described above.
According to a third aspect of the embodiments of the present application, a method of driving a display panel is provided. The method is applied to the display panel as described above, and includes: during a reset time period, outputting, via a first control circuit, a reset signal to a first multiplexing signal line, and inputting, via the first multiplexing signal line and a first reset circuit, the reset signal to a first terminal of a first drive circuit to reset an electric potential of the first terminal of the first drive circuit; and during a first data writing time period, outputting, via a second control circuit, a received first data signal to the first multiplexing signal line, and inputting, via the first multiplexing signal line and the first data writing circuit, the first data signal to a control terminal of the first drive circuit.
As can be seen from the embodiments, by the demultiplexing circuit and the first multiplexing signal line, the reset signal can be output to the first reset circuit via the first multiplexing signal line; additionally, the first data signal can be output to the first data writing circuit via the first multiplexing signal line. In this way, for a pixel circuit, one signal line is reduced, so that a space can be saved, thereby optimizing pixel layout and increasing a display resolution or a pixel light-emitting area, while helping to reset a data signal line and increasing coherency of signal writing.
It should be understood that the above general description and the following detailed description are only exemplary and explanatory and are not limited to the present application.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the application.
Exemplary embodiments will be described in detail herein, with the illustrations thereof represented in the drawings. When the following descriptions involve the drawings, like numerals in different drawings refer to like or similar elements unless otherwise indicated. The embodiments described in the following examples do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.
There exists a pixel circuit as shown in
The gate drive signal G10, the gate drive signal G20, and the gate drive signal G30 are shown in
At least one embodiment of the present application provides a display panel. As shown in
As shown in
As shown in
In this embodiment, by the demultiplexing circuit and the first multiplexing signal line, the reset signal can be output to the first reset circuit via the first multiplexing signal line; additionally, the first data signal can also be output to the first data writing circuit via the first multiplexing signal line. In this way, for each pixel circuit, one signal line is reduced, so that a space can be saved, thereby optimizing pixel layout and increasing a display resolution or a pixel light-emitting area, while helping to reset a data signal line and increasing a coherency of signal writing.
A display panel provided by an embodiment of the present application is briefly introduced above. A display panel provided by an embodiment of the present application will be described in detail below.
At least one embodiment of the present application further provides a display panel. As shown in
In this embodiment, the display panel may include pixel circuits arranged in array. The pixel circuits arranged in array include the first pixel circuit 31 and the second pixel circuit 34 mentioned above. The first pixel circuit 31 can be located in an ith row and a jth column, and the second pixel circuit 34 can be located in the ith row and a (j+1)th column, where the i and j are positive integers respectively. The demultiplexing circuit 32 is connected to the first pixel circuit 31 via the first multiplexing signal line DL1, and the demultiplexing circuit 32 is further connected to the second pixel circuit 34 via the second multiplexing signal line DL2.
In this embodiment, as shown in
As shown in
In this embodiment, the first reset circuit 311 includes a fifth transistor M5. A first terminal of the fifth transistor M5 is the first terminal of the first reset circuit 311, a second terminal of the fifth transistor M5 is the second terminal of the first reset circuit 311, and a control terminal of the fifth transistor M5 is the control terminal of the first reset circuit 311. In this embodiment, the fifth transistor M5 is an N-type transistor. The first terminal of the fifth transistor M5 is a source electrode, the second terminal of the fifth transistor M5 is a drain electrode, and the control terminal of the fifth transistor M5 is a gate electrode. It should be noted that the specific structure of the first reset circuit 311 is not limited to the structure provided in the embodiment of the present application.
As shown in
In this embodiment, the first drive circuit 314 includes an eighth transistor M8. A first terminal of the eighth transistor M8 is the first terminal of the first drive circuit 314, a second terminal of the eighth transistor M8 is the second terminal of the first drive circuit 314, and a control terminal of the eighth transistor M8 is the control terminal of the first drive circuit 314. The eighth transistor M8 is an N-type transistor. The first terminal of the eighth transistor M8 is a source electrode, the second terminal of the eighth transistor M8 is a drain electrode, and the control terminal of the eighth transistor M8 is a gate electrode.
As shown in
In this embodiment, the first data writing circuit 312 includes a seventh transistor M7. A first terminal of the seventh transistor M7 is the first terminal of the first data writing circuit 312, a second terminal of the seventh transistor M7 is the second terminal of the first data writing circuit 312, and a control terminal of the seventh transistor M7 is the control terminal of the first data writing circuit 312. The seventh transistor M7 is an N-type transistor. The first terminal of the seventh transistor M7 is a source electrode, the second terminal of the seventh transistor M7 is a drain electrode, and the control terminal of the seventh transistor M7 is a gate electrode.
As shown in
In this embodiment, the first storage circuit 313 includes a first capacitor C1. A first terminal of the first capacitor C1 is the first terminal of the first storage circuit 313, and a second terminal of the first capacitor C1 is the second terminal of the first storage circuit 313.
As shown in
In this embodiment, the first compensation circuit 315 includes a sixth transistor M6. A first terminal of the sixth transistor M6 is the first terminal of the first compensation circuit 315, a second terminal of the sixth transistor M6 is the second terminal of the first compensation circuit 315, and a control terminal of the sixth transistor M6 is the control terminal of the first compensation circuit 315. The sixth transistor M6 is an N-type transistor. The first terminal of the sixth transistor M6 is a source electrode, the second terminal of the sixth transistor M6 is a drain electrode, and the control terminal of the sixth transistor M6 is a gate electrode.
In this embodiment, as shown in
As shown in
In this embodiment, the second reset circuit 341 includes a ninth transistor M9. A first terminal of the ninth transistor M9 is the first terminal of the second reset circuit 341, a second terminal of the ninth transistor M9 is the second terminal of the second reset circuit 341, and a control terminal of the ninth transistor M9 is the control terminal of the second reset circuit 341. The ninth transistor M9 is an N-type transistor. The first terminal of the ninth transistor M9 is a source electrode, the second terminal of the ninth transistor M9 is a drain electrode, and the control terminal of the ninth transistor M9 is a gate electrode.
As shown in
In this embodiment, the second drive circuit 344 includes a twelfth transistor M12. A first terminal of the twelfth transistor M12 is the first terminal of the second drive circuit 344, a second terminal of the twelfth transistor M12 is the second terminal of the second drive circuit 344, and a control terminal of the twelfth transistor M12 is the control terminal of the second drive circuit 344. The twelfth transistor M12 is an N-type transistor. The first terminal of the twelfth transistor M12 is a source electrode, the second terminal of the twelfth transistor M12 is a drain electrode, and the control terminal of the twelfth transistor M12 is a gate electrode.
As shown in
In this embodiment, the second data writing circuit 342 includes an eleventh transistor M11. A first terminal of the eleventh transistor M11 is the first terminal of the second data writing circuit 342, a second terminal of the eleventh transistor M11 is the second terminal of the second data writing circuit 342, and a control terminal of the eleventh transistor M11 is the control terminal of the second data writing circuit 342. The eleventh transistor M11 is an N-type transistor. The first terminal of the eleventh transistor M11 is a source electrode, the second terminal of the eleventh transistor M11 is a drain electrode, and the control terminal of the eleventh transistor M11 is a gate electrode.
As shown in
In this embodiment, the second storage circuit 343 includes a second capacitor C2. A first terminal of the second capacitor C2 is the first terminal of the second storage circuit 343, and a second terminal of the second capacitor C2 is the second terminal of the second storage circuit 343.
As shown in
In this embodiment, the second compensation circuit 345 includes a tenth transistor M10. A first terminal of the tenth transistor M10 is the first terminal of the second compensation circuit 345, a second terminal of the tenth transistor M10 is the second terminal of the second compensation circuit 345, and a control terminal of the tenth transistor M10 is the control terminal of the second compensation circuit 345. The tenth transistor M10 is an N-type transistor. The first terminal of the tenth transistor M10 is a source electrode, the second terminal of the tenth transistor M10 is a drain electrode, and the control terminal of the tenth transistor M10 is a gate electrode.
As shown in
As shown in
In this embodiment, the first control circuit 321 includes a first transistor M1. A first terminal of the first transistor M1 is the first terminal of the first control circuit 321, a second terminal of the first transistor M1 is the second terminal of the first control circuit 321, and a control terminal of the first transistor M1 is the control terminal of the first control circuit 321. The first transistor M1 is an N-type transistor. The first terminal of the first transistor M1 is a source electrode, the second terminal of the first transistor M1 is a drain electrode, and the control terminal of the first transistor M1 is a gate electrode.
As shown in
In this embodiment, the second control circuit 322 includes a second transistor M2. A first terminal of the second transistor M2 is the first terminal of the second control circuit 322, a second terminal of the second transistor M2 is the second terminal of the second control circuit 322, and a control terminal of the second transistor M2 is the control terminal of the second control circuit 322. The second transistor M2 is an N-type transistor. The first terminal of the second transistor M2 is a source electrode, the second terminal of the second transistor M2 is a drain electrode, and the control terminal of the second transistor M2 is a gate electrode.
As shown in
In this embodiment, the third control circuit 323 includes a third transistor M3. A first terminal of the third transistor M3 is the first terminal of the third control circuit 323, a second terminal of the third transistor M3 is the second terminal of the third control circuit 323, and a control terminal of the third transistor M3 is the control terminal of the third control circuit 323. The third transistor M3 is an N-type transistor. The first terminal of the third transistor M3 is a source electrode, the second terminal of the third transistor M3 is a drain electrode, and the control terminal of the third transistor M3 is a gate electrode.
As shown in
In this embodiment, the fourth control circuit 324 includes a fourth transistor M4. A first terminal of the fourth transistor M4 is the first terminal of the fourth control circuit 324, a second terminal of the fourth transistor M4 is the second terminal of the fourth control circuit 324, and a control terminal of the fourth transistor M4 is the control terminal of the fourth control circuit 324. The fourth transistor M4 is an N-type transistor. The first terminal of the fourth transistor M4 is a source electrode, the second terminal of the fourth transistor M4 is a drain electrode, and the control terminal of the fourth transistor M4 is a gate electrode.
In this embodiment, as shown in
When the display panel is driven to work by signals as shown in
In the first stage S1, the first gate drive signal G1 and the first switch signal SW1 are at a high level, and the first transistor M1, the third transistor M3, the fifth transistor M5, and the ninth transistor M9 are turned on. The reset signal VIN1 is transmitted to the source electrode of the eighth transistor M8 via the first multiplexing signal line DL1 to reset an electric potential of the source electrode of the eighth transistor M8; and the reset signal VIN1 is transmitted to the source electrode of the twelfth transistor M12 via the second multiplexing signal line DL2 to reset an electric potential of the source electrode of the twelfth transistor M12. Therefore, a time period of the first stage S1 can be referred to as a reset time period.
In the first stage S1, the third gate drive signal G3 is at a high level, the sixth transistor M6 and the tenth transistor M10 are turned on, and the reference voltage signal VIN2 is written into the gate electrode of the eighth transistor M8 and the gate electrode of the twelfth transistor M12 respectively. Therefore, a voltage Vgs1 between the gate electrode and the source electrode of the eighth transistor M8 equals to Vref (that is, Vgs1=Vref), and a voltage Vgs2 between the gate electrode and the source electrode of the twelfth transistor M12 equals to Vref (Vgs2=Vref). The eighth transistor M8 and the twelfth transistor M12 are respectively used for driving the first light-emitting element D1 and the second light-emitting element D2 to emit light. Therefore, the eighth transistor M8 and the twelfth transistor M12 can be referred to as drive transistors.
In the second stage S2, the second switch signal SW2 and the third switch signal SW3 regularly take turns to be at a high level to write a data signal DATA into pixel circuits in other rows; and the first switch signal SW1 regularly take turns to be at a high level to reset electric potentials of source electrodes of drive transistors in pixel circuits in other rows.
In the second stage S2, for pixel circuits in the ith row, since the first gate drive signal G1 is at a low level, the electric potentials of the source electrodes of the eighth transistor M8 and the twelfth transistor M12 are not affected by the reset signal VIN1.
In the second stage S2, the third gate drive signal G3 is at a high level, an electric potential of the gate electrode of the eighth transistor M8 keeps being affected by the reference voltage signal VIN2 and remains constant, and an electric potential Vs1 of the source electrode of the eighth transistor M8 is boosted. When Vref−Vs1=Vth1 is satisfied, the eighth transistor M8 is turned off, where Vth1 is a threshold voltage of the eighth transistor M8. In this way, detection of the threshold voltage Vth1 of the eighth transistor M8 is completed.
Similarly, in the second stage S2, G3 is at a high level, an electric potential of the gate electrode of the twelfth transistor M12 keeps being affected by the reference voltage signal VIN2 and remains constant, and an electric potential Vs2 of the source electrode of the twelfth transistor M12 is boosted. When Vref−Vs2=Vth2 is satisfied, the twelfth transistor M12 is turned off, where Vth2 is a threshold voltage of the twelfth transistor M12. In this way, detection of the threshold voltage Vth2 of the twelfth transistor M12 is completed.
In the third stage S3, when the second gate drive signal G2 and the second switch signal SW2 are at a high level, and the first switch signal SW1 and the third switch signal SW3 are at a low level, the second transistor M2 is turned on, and the first data signal DATA1 is written into the first pixel circuit 31 through the first multiplexing signal line DL1. When the second gate drive signal G2 and the third switch signal SW3 are at a high level, and the first switch signal SW1 and the second switch signal SW2 are at a low level, the fourth transistor M4 is turned on, and the second data signal DATA2 is written into the second pixel circuit 32 through the second multiplexing signal line DL2. In this way, writing the data signal DATA into the first pixel circuit 31 and the second pixel circuit 34 is completed. A time period during which the first multiplexing signal line DL1 writes the first data signal DATA1 into the first pixel circuit 31 can be referred to as a first data writing time period. A time period during which the second multiplexing signal line DL2 writes the second data signal DATA2 into the second pixel circuit 32 can be referred to as a second data writing time period.
For the eighth transistor M8, a voltage Vgs1 between the gate electrode and the source electrode of the eighth transistor M8 equals to VDATA1−Vref+Vth1 (that is, Vgs1=VDATA1−Vref+Vth1), where VDATA1 is a voltage value of the first data signal DATA1. Substituting Vgs1=VDATA1−Vref+Vth1 into a saturation area current formula of the eighth transistor M8, an expression of current I1 flowing through the source electrode and the drain electrode of the eighth transistor M8 can be obtained as follows:
Similarly, for the twelfth transistor M12, a voltage Vgs2 between the gate electrode and the source electrode of the twelfth transistor M12 equals to VDATA2−Vref+Vth2 (that is, Vgs2=VDATA2−Vref+Vth2), where VDATA2 is a voltage value of the second data signal DATA2. Substituting Vgs2=VDATA2−Vref+Vth2 into a saturation area current formula of the twelfth transistor M12, an expression of current I2 flowing through the source electrode and the drain electrode of the twelfth transistor M12 can be obtained as follows:
At the end of the third stage S3, an internal compensation of pixel circuits in the ith row is completed. The internal compensation of the pixel circuits can prevent the effect of a threshold drift of a drive transistor on display uniformity.
In this embodiment, by the demultiplexing circuit, the first multiplexing signal line, and the second multiplexing signal line, the reset signal can be output to the first reset circuit via the first multiplexing signal line, and the reset signal can be output to the second reset circuit via the second multiplexing signal line; additionally, the first data signal can be output to the first data writing circuit via the first multiplexing signal line, and the second data signal can be output to the second data writing circuit via the second multiplexing signal line. In this way, for each pixel circuit, one signal line is reduced, so that a space can be saved, thereby optimizing pixel layout and increasing a display resolution or a pixel light-emitting area, while helping to reset a data signal line and increasing coherency of signal writing.
At least one embodiment of the present application further provides a display panel. As shown in
In this embodiment, the display region 51 can include a plurality of pixel circuits arranged in array. As shown in
In this embodiment, the peripheral region 52 can include a plurality of demultiplexing circuits 32, one reset signal line Vin1, and a plurality of data signal lines Data. The demultiplexing circuits 32 each can be connected to the reset signal line Vin1, and each of the demultiplexing circuits 32 can be connected to only one of the data signal lines Data. For example, an mth demultiplexing circuit 32 can be connected to an mth data signal line Data<m>, and an (m+n)th demultiplexing circuit 32 can be connected to an (m+n)th data signal line Data<m+n>, where m and n are positive integers.
In this embodiment, each of the demultiplexing circuits 32 is connected to the first pixel circuit 31 via a first multiplexing signal line DL1, and to the second pixel circuit 34 via a second multiplexing signal line DL2. For example, for the mth demultiplexing circuit 32, the mth demultiplexing circuit 32 can be connected to the first pixel circuit 31 located in the ith row and the jth column via an mth first multiplexing signal line DL1, as well as to the second pixel circuit 34 located in the ith row and the j+1th column via an mth second multiplexing signal line DL2.
For a same demultiplexing circuit 32, during a reset time period, the demultiplexing circuit 32 receives a reset signal VIN1 provided via the reset signal line Vin1, and transmits the reset signal VIN1 to the first pixel circuit 31 via the first multiplexing signal line DL1, and to the second pixel circuit 34 via the second multiplexing signal line DL2. During a first data writing time period, the demultiplexing circuit 32 receives a first data signal DATA1 provided via a data signal line Data, and outputs the first data signal DATA1 to the first pixel circuit 31 via the first multiplexing signal line DL1. During a second data writing time period, the demultiplexing circuit 32 receives a second data signal DATA2 provided via a data signal line Data, and outputs the second data signal DATA2 to the second pixel circuit 34 via the second multiplexing signal line DL2.
For the first pixel circuit 31, the first multiplexing signal line DL1 is used for transmitting both the reset signal VIN1 and the first data signal DATA1, so that one signal line is saved. For the second pixel circuit 34, the second multiplexing signal line DL2 is used for transmitting both the reset signal VIN1 and the second data signal DATA2, so that one signal line is saved. Further, for each of the pixel circuits arranged in array, one signal line is reduced, so that a space can be saved, thereby optimizing pixel layout and increasing a display resolution or a pixel light-emitting area, while helping to reset a data signal line and increasing coherency of signal writing.
It should be noted that, in the embodiments of the present application, the first pixel circuit 31 being a 4T1C pixel circuit and the second pixel circuit 34 being a 4T1C pixel circuit are taken as an example for illustration. It will be understood that the first pixel circuit 31 and the second pixel circuit 34 can be other pixel circuits such as, but not limited to, 5T1C pixel circuits, 6T1C pixel circuits, or 7T1C pixel circuits.
At least one embodiment of the present application further provides a display device, including a display module, and a display panel according to any of the embodiments as described above.
In this embodiment, by a demultiplexing circuit and a first multiplexing signal line, a reset signal can be output to a first reset circuit via a first multiplexing signal line; additionally, a first data signal can be output to a first data writing circuit via the first multiplexing signal line. In this way, for a pixel circuit, one signal line is reduced, so that a space can be saved, thereby optimizing pixel layout and increasing a display resolution or a pixel light-emitting area, while helping to reset a data signal line and increasing coherency of signal writing.
At least one embodiment of the present application further provides a method of driving a display panel. The method of driving a display panel is applied to a display panel according to any of the embodiments as described above. As shown in
At step 601, during a reset time period, a reset signal is output via a first control circuit to a first multiplexing signal line, and then the reset signal is input to a first terminal of a first drive circuit via the first multiplexing signal line and a first reset circuit to reset an electric potential of the first terminal of the first drive circuit.
In an embodiment, the method further includes: during the reset time period, the reset signal is output via a third control circuit to a second multiplexing signal line, and then the reset signal is input to a first terminal of a second drive circuit via the second multiplexing signal line and a second reset circuit to reset an electric potential of the first terminal of the second drive circuit.
At step 602, during a first data writing time period, a received first data signal is output via a second control circuit to the first multiplexing signal line, and the first data signal is input to a control terminal of the first drive circuit via the first multiplexing signal line and a first data writing circuit.
In an embodiment, the method further includes: during a second data writing time period, a received second data signal is output via a fourth control circuit to the second multiplexing signal line, and the second data signal is input to a control terminal of the second drive circuit via the second multiplexing signal line and a second data writing circuit.
In this embodiment, via a demultiplexing circuit and the first multiplexing signal line, the reset signal can be output to the first reset circuit via the first multiplexing signal line; additionally, the first data signal can be output to the first data writing circuit via the first multiplexing signal line. In this way, for a pixel circuit, one signal line is reduced, so that a space can be saved, thereby optimizing pixel layout and increasing a display resolution or a pixel light-emitting area, while helping to reset a data signal line and increasing coherency of signal writing.
It should be noted that the display device in this embodiment can be any product or component having a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a laptop, a digital photo frame or a navigator.
It should be pointed out that in the drawings, sizes of layers and areas may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on the another element or layer, or an intermediate layer may be provided therebetween. In addition, it will be understood that when an element or layer is referred to as being “below” another element or layer, the element or layer can be directly below the another element, or one and more intermediate layers or elements may be provided therebetween. It will also be understood that when a layer or element is referred to as being “between” two layers or elements, it can be an only layer between the two layers or elements, or one or more intermediate layers or elements may be provided between the two layers or elements. Similar reference signs indicate similar elements throughout.
In the present invention, terms “first” and “second” are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance. A term “plurality” refers to two or more, unless specifically defined otherwise.
Other embodiments of the present application will be readily apparent to those skilled in the art after considering the specification and practicing the contents disclosed herein. The present application is intended to cover any variations, usage, or adaptations of the present application, which follow the general principle of the present application and involve common knowledge or conventional technical means in the art that are not disclosed in the present application. The specification and embodiments are to be regarded as illustrative only. The true scope and spirit of the present application are pointed out by the following claims.
It is to be understood that the present application is not limited to the specific structures that have been described and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the application is to be limited only by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202010328502.2 | Apr 2020 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/076326 | 2/9/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2021/212981 | 10/28/2021 | WO | A |
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