Patent Application
20240161691
The present disclosure relates to, but is not limited to, the field of display technology, in particular to a display substrate and a display apparatus.
An Organic Light Emitting Diode (OLED for short) and Quantum-dot Light Emitting Diodes (QLED for short) are active light emitting display devices and have advantages of self-illumination, a wide viewing angle, a high contrast, low power consumption, an extremely high reaction speed, lightness and thinness, bendability, a low cost, etc. With continuous development of display technologies, a display apparatus using the OLED or the QLED as a light emitting device and using a Thin Film Transistor (TFT) for signal control has become a mainstream product in the field of display at present.
The following is a summary of subject matters described herein in detail. This summary is not intended to limit the scope of protection of claims.
At least one embodiment of the present disclosure provides a display substrate and a display apparatus.
In one aspect, at least one embodiment of the present disclosure provides a display substrate, including an underlay substrate and a plurality of pixel unit groups. The underlay substrate includes a display region. The plurality of pixel unit groups are located in the display region. At least one pixel unit group includes a plurality of sub-pixel groups, wherein at least one sub-pixel group includes a pixel circuit. The pixel circuit includes a first sub-pixel circuit, a second sub-pixel circuit, and a light emitting control sub-circuit, wherein the first sub-pixel circuit and the second sub-pixel circuit are both electrically connected to the light emitting control sub-circuit. The light emitting control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light. The first sub-pixel circuit and the second sub-pixel circuit are substantially symmetrical with respect to a center line of the pixel circuit of the sub-pixel group in a first direction.
In some exemplary embodiments, the light emitting control sub-circuit of the pixel circuit is located between the first sub-pixel circuit and the second sub-pixel circuit in the first direction.
In some exemplary embodiments, the light emitting control sub-circuit is electrically connected to a light emitting control line, wherein the light emitting control line extends along a second direction and is located between the first sub-pixel circuit and the second sub-pixel circuit; the second direction crosses the first direction.
In some exemplary embodiments, the light emitting control sub-circuit includes: a light emitting control transistor; a control electrode of the light emitting control transistor is electrically connected to a light emitting control line, a first electrode of the light emitting control transistor is electrically connected to a first power line, and a second electrode of the light emitting control transistor is electrically connected to the first sub-pixel circuit and the second sub-pixel circuit.
In some exemplary embodiments, the at least one sub-pixel group further includes a first light emitting element electrically connected to the first sub-pixel circuit, and a second light emitting element electrically connected to the second sub-pixel circuit. A first electrode of the first light emitting element is electrically connected to the first sub-pixel circuit, and the first electrode of the second light emitting element is electrically connected to the second sub-pixel circuit. Second electrodes of the first light emitting element and the second light emitting element are both electrically connected to a second power line. The underlay substrate further includes a frame region located on a periphery of the display region. The display region is disposed with a plurality of first auxiliary power lines extending along the first direction, wherein at least one first auxiliary power line is electrically connected to the second electrodes of the first light emitting element and the second light emitting element in the frame region.
In some exemplary embodiments, at least one first auxiliary power line is located between adjacent sub-pixel groups within the at least one pixel unit group in the second direction crossing the first direction.
In some exemplary embodiments, the display region of the underlay substrate is further disposed with a plurality of first power lines extending along the first direction. At least one first power line is located between adjacent pixel unit groups.
In some exemplary embodiments, adjacent pixel unit groups share one first power line.
In some exemplary embodiments, each sub-pixel group of the at least one pixel unit group includes the pixel circuit, the at least one pixel unit group is substantially symmetrical with respect to the center line of a plurality of pixel circuits of the pixel unit group in the second direction, and the second direction crosses the first direction.
In some exemplary embodiments, the display region of the underlay substrate is further disposed with a plurality of sensing lines extending along the first direction. At least one sensing line is located between adjacent sub-pixel groups within the at least one pixel unit group.
In some exemplary embodiments, one sensing line and one first auxiliary power line are disposed between adjacent sub-pixel groups within the at least one pixel unit group; an orthographic projection of the sensing line on the underlay substrate is located on a side of the orthographic projection of the first auxiliary power line on the underlay substrate.
In some exemplary embodiments, one sensing line and two first auxiliary power lines are disposed between adjacent sub-pixel groups within the at least one pixel unit group. The orthographic projections of the two first auxiliary power lines on the underlay substrate are respectively located on both sides of the orthographic projection of the sensing line on the underlay substrate.
In some exemplary embodiments, the auxiliary power line and the sensing line are in a same layer.
In some exemplary embodiments, one first auxiliary power line, one sensing line, and one second auxiliary power line are disposed between adjacent sub-pixel groups within the at least one pixel unit group; the second auxiliary power line extends along the first direction and is electrically connected to the first power line. Overlapping between the orthographic projection of the first auxiliary power line on the underlay substrate and the orthographic projection of the sensing line on the underlay substrate exists, and the orthographic projection of the second auxiliary power line on the underlay substrate is located on a side of the orthographic projection of the sensing line on the underlay substrate.
In some exemplary embodiments, the first auxiliary power line is located on a side of the sensing line close to the underlay substrate in a plane perpendicular to the display substrate.
In some exemplary embodiments, the at least one pixel unit group includes: six sub-pixel groups arranged in sequence along the second direction, wherein the pixel circuits of the first sub-pixel group and the second sub-pixel group are substantially symmetrical with respect to the center line of the pixel circuits of the first sub-pixel group and the second sub-pixel group in the second direction, the second direction crossing the first direction.
In some exemplary embodiments, the display region of the underlay substrate is further disposed with a plurality of data lines extending along the first direction. Two data lines are arranged between the pixel circuits of the first sub-pixel group and the second sub-pixel group, and one data line is arranged between the pixel circuits of the second sub-pixel group and the third sub-pixel group.
In some exemplary embodiments, the first sub-pixel circuit includes a first transistor, a second transistor, a third transistor, and a first storage capacitor. The control electrode of the first transistor is electrically connected to an i-th first scanning line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor. The control electrode of the second transistor is electrically connected to an i-th second scanning line, the first electrode of the second transistor is electrically connected to the sensing line, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor. The first electrode of the third transistor is electrically connected to the light emitting control sub-circuit. The first electrode of the first storage capacitor is electrically connected to the control electrode of the third transistor, and the second electrode of the first storage capacitor is electrically connected to the second electrode of the third transistor. The second electrode of the third transistor is electrically connected to the first electrode of the first light emitting element. The second sub-pixel circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second storage capacitor. The control electrode of the fourth transistor is electrically connected to an (i+1)-th first scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the control electrode of the sixth transistor. The control electrode of the fifth transistor is electrically connected to an (i+1)-th second scanning line, the first electrode of the fifth transistor is electrically connected to the sensing line, and the second electrode of the fifth transistor is electrically connected to the second electrode of the sixth transistor. The first electrode of the sixth transistor is electrically connected to the light emitting control sub-circuit. The first electrode of the second storage capacitor is electrically connected to the control electrode of the sixth transistor, and the second electrode of the second storage capacitor is electrically connected to the second electrode of the sixth transistor. The second electrode of the sixth transistor is electrically connected to the first electrode of the second light emitting element. Herein, i is a natural number.
In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer which are disposed on the underlay substrate. The first conductive layer at least includes the second electrode of the first storage capacitor of the pixel circuit and the second electrode of the second storage capacitor. The semiconductor layer at least includes active layers of a plurality of transistors of the pixel circuit, the first electrode of the first storage capacitor, and the second electrode of the second storage capacitor. The second conductive layer at least includes the control electrodes of a plurality of transistors of the pixel circuit, the first scanning line, the second scanning line, and the light emitting control line. The third conductive layer at least includes the data line and the sensing line.
In some exemplary embodiments, the first auxiliary power line electrically connected to the second electrodes of the first light emitting element and the second light emitting element is located at the first conductive layer or the third conductive layer.
According to another aspect, an embodiment of the present disclosure further provides a display device, which includes the abovementioned display substrates.
After the accompanying drawings and detailed descriptions are read and understood, other aspects may be understood.
Accompanying drawings are used for providing further understanding for technical solutions of the present disclosure, constitute a part of the specification, and together with the embodiments of the present disclosure, are used for explaining the technical solutions of the present disclosure but not to constitute limitations on the technical solutions of the present disclosure. Shapes and sizes of one or more components in the accompanying drawings do not reflect actual scales and are only intended to illustrate the contents of the present disclosure.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Their implementations may be carried out in many different forms. Those of ordinary skill in the art may easily understand such a fact that manners and contents may be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents recorded in the following implementations only. The embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other if there are no conflicts.
In the accompanying drawings, a size of one or more constituent elements, a thickness of a layer or an area is sometimes exaggerated for clarity. Therefore, one implementation of the present disclosure is not necessarily limited to the dimension, and shapes and sizes of one or a plurality of components in the accompanying drawings do not reflect actual scales. In addition, the drawings schematically illustrate ideal examples, and an implementation of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.
Ordinal numerals such as “first”, “second”, and “third” in the specification are set to avoid confusion of constituent elements, but are not intended to limit in terms of quantity. “A plurality of” in the present disclosure means a quantity of two or more.
In the specification, for convenience, wordings indicating orientation or positional relationships, such as “center”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, and “outside”, are used for illustrating positional relationships between constituent elements with reference to the drawings, and are merely for facilitating the description of the specification and simplifying the description, rather than indicating or implying that a referred apparatus or element must have a particular orientation and be constructed and operated in the particular orientation. Therefore, they cannot be understood as limitations on the present disclosure. The positional relationships between the constituent elements may be changed as appropriate according to the direction where the constituent elements are described. Therefore, the positional relationships are not limited to the words and phrases used in the specification, and appropriate substitutions may be made according to situations.
In the specification, unless otherwise specified and defined explicitly, terms “mount”, “mutually connect”, and “connect” should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integrated connection, it may be a mechanical connection or a connection, and it may be a direct connection, an indirect connection through intermediate components, or communication inside two components. For those of ordinary skills in the art, meanings of the abovementioned terms in the present disclosure may be understood according to situations.
In this specification, a transistor refers to an element which at least includes three terminals, i.e., a gate electrode (gate electrode), a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to a region which the current mainly flows through.
In this specification, a first electrode may be a drain electrode and a second electrode may be a source electrode, or, a first electrode may be a source electrode and a second electrode may be a drain electrode. In addition, the gate electrode may alternatively be called a control electrode. In a case that transistors with opposite polarities are used, or in a case that a direction of a current changes during work of a circuit, or the like, functions of the “source electrode” and the “drain electrode” may sometimes be exchanged. Therefore, the “source electrode” and the “drain electrode” may be exchanged in this specification.
In the specification, “electrical connection” includes a case that constituent elements are connected together through an element with a certain electrical effect. There is no specific restriction on “the element with certain electrical effect” as long as it may transmit electrical signals between the connected constituent elements. Examples of “the element with the certain electric action” not only include an electrode and a wiring, but further include a switch element such as a transistor, a resistor, an inductor, a capacitor, other elements with various functions, etc.
In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above −10° and below 10°, and thus also includes a state in which the angle is above −5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.
“About”, or “more or less” in the present disclosure refers to a situation that a boundary is defined not strictly and numerical values within process and measurement error ranges are allowed.
An embodiment of the present disclosure provides a display substrate, including an underlay substrate and a plurality of pixel unit groups. The underlay substrate includes a display region, and the plurality of pixel unit groups are located in the display region. At least one pixel unit group includes a plurality of sub-pixel groups, wherein at least one sub-pixel group includes a pixel circuit. The pixel circuit of the at least one sub-pixel group includes a first sub-pixel circuit, a second sub-pixel circuit, and a light emitting control sub-circuit. The first sub-pixel circuit and the second sub-pixel circuit are both electrically connected to the light emitting control sub-circuit. The light emitting control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light. The first sub-pixel circuit and the second sub-pixel circuit are substantially symmetrical with respect to a center line of the pixel circuit of the sub-pixel group in a first direction.
The display substrate provided by the present embodiment may achieve high gray level grade and improve display effect by disposing the light emitting control sub-circuit in the pixel circuit; furthermore, by setting the first sub-pixel circuit and the second sub-pixel circuit substantially symmetrical with respect to a center line of the sub-pixel group in the first direction, space may be optimized, and resolution may be increased without affecting normal display.
In some exemplary embodiments, the light emitting control sub-circuit of the pixel circuit is located between the first sub-pixel circuit and the second sub-pixel circuit in the first direction. In the present example, the first sub-pixel circuit, the light emitting control sub-circuit, and the second sub-pixel circuit of the pixel circuit may be arranged in sequence along the first direction. In some examples, the first direction crosses a second direction, for example, they are perpendicular to each other. For example, the first direction is parallel to a sub-pixel column direction and the second direction is parallel to a sub-pixel row direction. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the light emitting control sub-circuit is electrically connected to a light emitting control line. The light emitting control line extends along the second direction crossing the first direction and is located between the first sub-pixel circuit and the second sub-pixel circuit.
In some exemplary embodiments, the light emitting control sub-circuit includes a light emitting control transistor. A control electrode of the light emitting control transistor is electrically connected to a light emitting control line, a first electrode of the light emitting control transistor is electrically connected to a first power line, and a second electrode of the light emitting control transistor is electrically connected to the first sub-pixel circuit and the second sub-pixel circuit. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the at least one sub-pixel group further includes a first light emitting element electrically connected to the first sub-pixel circuit, and a second light emitting element electrically connected to the second sub-pixel circuit. The first electrode of the first light emitting element is electrically connected to the first sub-pixel circuit, and the first electrode of the second light emitting element is electrically connected to the second sub-pixel circuit. Second electrodes of the first light emitting element and the second light emitting element are both electrically connected to a second power line. The underlay substrate further includes a frame region located on a periphery of the display region. The display region is disposed with a plurality of first auxiliary power lines extending along the first direction, wherein at least one first auxiliary power line is electrically connected to the second electrodes of the first light emitting element and the second light emitting element in the frame region. The present exemplary embodiment may reduce IR drop of the second power line by disposing the first auxiliary power line on the display substrate.
In some exemplary embodiments, the at least one first auxiliary power line is located between adjacent sub-pixel groups within the at least one pixel unit group in the second direction crossing the first direction. For example, the at least one pixel unit group includes six sub-pixel groups arranged along the second direction, and the at least one first auxiliary power line may be located between the third sub-pixel group and the fourth sub-pixel group. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the display region of the underlay substrate is further disposed with a plurality of first power lines extending along the first direction. At least one first power line is located between adjacent pixel unit groups. However, the present embodiment is not limited thereto.
In some exemplary embodiments, adjacent pixel unit groups share one first power line. In the present example, one first power line may be disposed between adjacent pixel unit groups, and all the adjacent pixel unit groups are electrically connected to the first power line. However, the present embodiment is not limited thereto. For example, two first power lines may be arranged between adjacent pixel unit groups, and one first power line is electrically connected to one pixel unit group.
In some exemplary embodiments, each sub-pixel group of the at least one pixel unit group includes the pixel circuit, the at least one pixel unit group is substantially symmetrical with respect to the center line of a plurality of pixel circuits of the pixel unit group in the second direction. Herein, the second direction crosses the first direction. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the display region of the underlay substrate is further disposed with a plurality of sensing lines extending along the first direction. At least one sensing line is located between adjacent sub-pixel groups within the at least one pixel unit group. In some examples, the pixel unit group includes six sub-pixel groups arranged along the second direction, one sensing line may be located between the third sub-pixel group and the fourth sub-pixel group, and the pixel circuits of the six sub-pixel groups are all electrically connected to the sensing line. However, the present embodiment is not limited thereto. For example, two sensing lines may be disposed between the third sub-pixel group and the fourth sub-pixel group included in the pixel unit group, and the pixel circuits of the first sub-pixel group to third sub-pixel group may be electrically connected to one of the sensing lines, and the pixel circuits of the fourth sub-pixel group to sixth sub-pixel group may be electrically connected to the other sensing line.
In some exemplary embodiments, one sensing line and one first auxiliary power line are disposed between adjacent sub-pixel groups within the at least one pixel unit group. An orthographic projection of the sensing line on the underlay substrate is located on a side of the orthographic projection of the first auxiliary power line on the underlay substrate. In the present example, the orthographic projection of the sensing line on the underlay substrate and the orthographic projection of the first auxiliary power line on the underlay substrate may not overlap. In some examples, the first auxiliary power line and the sensing line may be in a same layer. However, the present embodiment is not limited thereto.
In some exemplary embodiments, one sensing line and two first auxiliary power lines are disposed between adjacent sub-pixel groups within the at least one pixel unit group. The orthographic projections of the two first auxiliary power lines on the underlay substrate are respectively located on both sides of the orthographic projection of the sensing line on the underlay substrate. In the present example, the orthographic projection of the sensing line on the underlay substrate and the orthographic projections of the two first auxiliary power line on the underlay substrate may not overlap. In some examples, the first auxiliary power line and the sensing line may be in the same layer. However, the present embodiment is not limited thereto.
In some exemplary embodiments, one first auxiliary power line, one sensing line, and one second auxiliary power line may be disposed between adjacent sub-pixel groups within the at least one pixel unit group. The second auxiliary power line extends along the first direction and is electrically connected to the first power line. There is an overlapping between the orthographic projection of the first auxiliary power line on the underlay substrate and the orthographic projection of the sensing line on the underlay substrate, and the orthographic projection of the second auxiliary power line on the underlay substrate is located on a side of the orthographic projection of the sensing line on the underlay substrate. In some examples, the orthographic projection of the second auxiliary power line on the underlay substrate and the orthographic projections of the sensing line and the first auxiliary power line on the underlay substrate may not overlap. In some examples, the second auxiliary power line and the sensing line may be in the same layer. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the first auxiliary power line may be located on a side of the sensing line close to the underlay substrate in a plane perpendicular to the display substrate.
In some exemplary embodiments, the at least one pixel unit group includes: six sub-pixel groups arranged in sequence along the second direction, wherein the pixel circuits of the first sub-pixel group and the second sub-pixel group are substantially symmetrical with respect to the center line of the pixel circuits of the first sub-pixel group and the second sub-pixel group in the second direction, the second direction crossing the first direction. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the display region of the underlay substrate is further disposed with a plurality of data lines extending along the first direction. Two data lines may be arranged between the pixel circuits of the first sub-pixel group and the second sub-pixel group, and one data line may be arranged between the pixel circuits of the second sub-pixel group and the third sub-pixel group. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the first sub-pixel circuit may include a first transistor, a second transistor, a third transistor, and a first storage capacitor. The control electrode of the first transistor is electrically connected to an i-th first scanning line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor. The control electrode of the second transistor is electrically connected to an i-th second scanning line, the first electrode of the second transistor is electrically connected to the sensing line, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor. The first electrode of the third transistor is electrically connected to the light emitting control sub-circuit. The first electrode of the first storage capacitor is electrically connected to the control electrode of the third transistor, and the second electrode of the first storage capacitor is electrically connected to the second electrode of the third transistor. The second electrode of the third transistor is electrically connected to the first electrode of the first light emitting element. The second sub-pixel circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second storage capacitor. The control electrode of the fourth transistor is electrically connected to an (i+1)-th first scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the control electrode of the sixth transistor. The control electrode of the fifth transistor is electrically connected to an (i+1)-th second scanning line, the first electrode of the fifth transistor is electrically connected to the sensing line, and the second electrode of the fifth transistor is electrically connected to the second electrode of the sixth transistor. The first electrode of the sixth transistor is electrically connected to the light emitting control sub-circuit. The first electrode of the second storage capacitor is electrically connected to the control electrode of the sixth transistor, and the second electrode of the second storage capacitor is electrically connected to the second electrode of the sixth transistor. The second electrode of the sixth transistor is electrically connected to the first electrode of the second light emitting element. Herein, i is a natural number.
In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer which are disposed on the underlay substrate. The first conductive layer at least includes the second electrode of the first storage capacitor of the pixel circuit and the second electrode of the second storage capacitor. The semiconductor layer at least includes an active layer of a plurality of transistors of the pixel circuit, the first electrode of the first storage capacitor, and the second electrode of the second storage capacitor. The second conductive layer at least includes the control electrodes of a plurality of transistors of the pixel circuit, the first scanning line, the second scanning line, and the light emitting control line. The third conductive layer at least includes the data line and the sensing line.
In some exemplary embodiments, the first auxiliary power line electrically connected to the second electrodes of the first light emitting element and the second light emitting element may be located in the first conductive layer or the third conductive layer. However, the present embodiment is not limited thereto.
The display substrate of the present embodiment will now be described with some examples.
In some exemplary embodiments, the timing controller may provide a gray-scale value and control signal suitable for a specification of the data driver for the data driver, provide a clock signal, scanning starting signal, etc., suitable for a specification of the scanning driver for the scanning driver, and provide a clock signal, transmission stopping signal, etc., suitable for a specification of the light emitting driver for the light emitting driver. The data driver may generate a data voltage to be provided to the data lines D(1) to D(n) by using a gray-scale value and a control signal received from the timing controller, wherein n may be a natural number. For example, the data driver may sample the gray-scale value by using a clock signal, and apply the data voltage corresponding to the gray-scale value to the data lines D(1) to D(n) taking pixel row as the unit. The scanning driver may generate a scanning signal to be provided to the scanning lines G(1) to G(m) by receiving the clock signal, a scanning starting signal, etc., from the timing controller, wherein m may be a natural number. For example, the scanning driver may sequentially provide the scanning signals with on-level pulses to the scanning lines G(1) to G(m). For example, the scanning driver may be constructed in a form of a shift register and may generate the scanning signal by sequentially transmitting the scanning starting signal provided in a form of the on-level pulse to a next-stage circuit under the control of the clock signal. The light emitting driver may generate a transmitting signal to be provided to the light emitting control lines EM(1) to EM(m) by receiving the clock signal, the transmission stopping signal, etc., from the timing controller. For example, the light emitting driver may provide sequentially the transmitting signal with an off-level pulse to the light emitting control lines EM(1) to EM(m). For example, the light emitting driver may be constructed in a form of the shift register and generate a light emitting signal by sequentially transmitting emission stop signals provided in the form of the off-level pulse to the next-stage circuit under the control of the clock signal. The pixel array may include a plurality of pixel unit groups, wherein at least one pixel unit group may include a plurality of sub-pixel groups.
In some exemplary embodiments, the first sub-pixel circuit and the light emitting control sub-circuit are configured to receive the data voltage transmitted by the data line and output a corresponding current to the first light emitting element under the control of the scanning line and the light emitting control line. The second sub-pixel circuit and the light emitting control sub-circuit are configured to receive the data voltage transmitted by the data line and output a corresponding current to the second light emitting element under the control of the scanning line and the light emitting control line. The light emitting control sub-circuit is configured to control the first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control the second light emitting element electrically connected to the second sub-pixel circuit to emit light. The first light emitting element is configured to emit light of a corresponding brightness in response to the current outputted by the first sub-pixel circuit, and the second light emitting element is configured to emit light of a corresponding brightness in response to the current outputted by the second sub-pixel circuit. In the present example, the at least one sub-pixel group may include two sub-pixels sharing the light emitting control sub-circuit, for example, one sub-pixel thereof may include the first sub-pixel circuit and the first light emitting element, and the other sub-pixel may include the second sub-pixel circuit and the second light emitting element. However, the present embodiment is not limited thereto.
In some exemplary embodiments, one pixel unit in the at least one pixel unit group P may include a Red (R) sub-pixel, a Green (G) sub-pixel, and a Blue (B) sub-pixel, or may include the red sub-pixel, the green sub-pixel, the blue sub-pixel, and a white sub-pixel, which is not limited by the present disclosure herein. In some exemplary implementations, the shape of the sub-pixel in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in parallel in a horizontal direction, in parallel in a vertical direction, or in a Delta shape. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel in the horizontal direction, in parallel in the vertical direction, or in a square, which is not limited by the present disclosure herein.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, the first transistor T1 is configured to receive the data signal transmitted by the data line D under the control of the first scanning line G1(i) and cause the control electrode of the third transistor T3 to receive the data signal. The third transistor T3 is configured to generate a corresponding current at the second electrode by using a first power signal provided by the light emitting control sub-circuit 73 under the control of the data signal received at its control electrode. The first light emitting element EL is configured to emit light of a corresponding brightness in response to the current generated by the second electrode of the third transistor T3. The second transistor T2 is configured to extract a threshold voltage Vth and a mobility ratio of the third transistor T3 in response to compensation timing to compensate the threshold voltage Vth.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In the present exemplary embodiment, the first sub-pixel circuit and the second sub-pixel circuit within the sub-pixel group are both electrically connected to the same light emitting control sub-circuit. That is, adjacent sub-pixels within the sub-pixel group share one light emitting control sub-circuit. The pixel circuit of the present exemplary embodiment may realize high gray level grade display by disposing the light emitting control sub-circuit, thereby improving the display effect.
In some exemplary embodiments, the first power line PL1 may keep providing high-level signals, and the second power line PL2 may keep providing low-level signals. The first transistor T1 to the sixth transistor T6 and the light emitting control transistor T7 may be P-type transistors or N-type transistors. Use of the same type of transistors in a pixel driving circuit may simplify a process flow, reduce process difficulties of the display panel, and improve a yield of a product.
In an exemplary embodiments, the first transistor T1 to the sixth transistor T6 and the light emitting control transistor T7 may be made of low temperature poly-silicon thin film transistors, or may be made of oxide thin film transistors, or may be made of both the low temperature poly-silicon thin film transistors and the oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor is made of Low Temperature Poly-Silicon (LTPS), and the active layer of the oxide thin film transistor is made of an oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility, fast charging, and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In some exemplary embodiments, the low temperature poly-silicon thin film transistors and the oxide thin film transistors may be integrated on one display substrate to form a Low Temperature Polycrystalline Oxide (LTPO) display substrate. Advantages of the low temperature poly-silicon thin film transistor and the oxide thin film transistor may be used to achieve high Pixel Per Inch (PPI) and low frequency driving, so that power consumption may be reduced, and display quality may be improved.
In some exemplary embodiments, the first light emitting element EL and the second light emitting element EL′ may be an organic electroluminescent diode (such as OLED). The first light emitting element EL and the second light emitting element EL′ may each include the first electrode (anode), an organic light emitting layer, and the second electrode (cathode) which are stacked.
In some exemplary embodiments, the operation process of the pixel circuit of the present embodiment includes a display stage S1 and an idle stage S2. In the idle stage between every two frames of the display stages, a compensation operation for a row of sub-pixels may be completed, for example, the detection for the threshold voltage Vth and the mobility of the driving transistor of a row of sub-pixels may be completed, so that the detected data is used to obtain a compensation data signal to complete the display in the display stage.
In some exemplary embodiments, as shown in
At the data writing stage, the first scanning line G1(i) and the second scanning line G2(i) provide the high-level signal, and the first transistor T1 and the second transistor T2 of the first sub-pixel circuit are turned on. The first transistor T1 is turned on, the data signal provided by the data line D is written to the control electrode of the third transistor T3, and the first storage capacitor Cst1 is charged. The second transistor T2 is turned on, and a reset voltage provided by the sensing line SE is supplied to the first electrode of the first light emitting element EL to reset the first electrode of the first light emitting element EL. The light emitting control line EM(i) provides the low-level signal, and the light emitting control transistor T7 is turned off. At the present stage, the first light emitting element EL does not emit light.
In the light emitting stage, the first scanning line G1(i) and the second scanning line G2(i) provide the low-level signal, and the first transistor T1 and the second transistor T2 of the first sub-pixel circuit are turned off. The light emitting control line EM(i) provides the high-level signal, and the light emitting control transistor T7 is turned on. The high-level signal provided by the first power line PL1 is transmitted to the first electrode of the third transistor T3, and the third transistor T3 provides a driving current to the first light emitting element EL to drive the first light emitting element EL to emit light.
As shown in
In some exemplary embodiments, description is given by taking completing the compensation operation of the first sub-pixel circuit at the idle phase S2 as an example. At the idle stage S2, the first scanning line G1(i) and the second scanning line G2(i) provide the high-level signal, the first transistor T1 and the second transistor T2 of the first sub-pixel circuit are turned on, a test data voltage provided by the data line D is written into the control electrode of the third transistor T3, and the electrical signal at the second electrode of the third transistor T3 is read through the second transistor T2 and outputted through the sensing line SE, so that an external compensation circuit compensates the mobility of the third transistor T3 through the outputted electrical signal. At the idle phase S2, the light emitting control line EM(i) may keep providing the high-level signal, and the light emitting control transistor T7 is turned on, so that the third transistor T3 may generate the driving current.
In the present exemplary embodiment, the first sub-pixel circuit and the second sub-pixel circuit of a 3T1C structure are electrically connected to one light emitting control transistor, and the light emitting control transistor is controlled to be disconnected at the data writing stage, so as to avoid that the driving transistor generates a current in the data writing process, and ensure that the driving current is provided to the light emitting element at the light emitting stage, which may achieve the high gray level grade and improve the display effect.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, the active layer includes a channel region and a first doped region and a second doped region located on both sides of the channel region. The channel region of the active layer has semiconductor characteristics, and the first doped region and the second doped region have conductivity. The first doped region or second doped region of the active layer may be interpreted as a source electrode or drain electrode of the transistor. A part of the active layer between the transistors may be interpreted as a wiring doped with an impurity, and may be used for electrically connecting the transistors. In some examples, a material of the semiconductor layer may include metal oxide, e.g., IGZO. However, the present embodiment is not limited thereto. For example, the material of the semiconductor layer may include, for example, polysilicon.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, the structure of the fourth transistor T4 and the structure of the first transistor T1 are substantially symmetrical with respect to the center line OY, the structure of the fifth transistor T5 and the structure of the second transistor T2 are substantially symmetrical with respect to the center line OY, the structure of the sixth transistor T6 and the structure of the third transistor T3 are substantially symmetrical with respect to the center line OY, and the structure of the second storage capacitor Cst2 and the structure of the first storage capacitor Cst1 are substantially symmetrical with respect to the center line OY. Therefore, the structures of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the second storage capacitor Cst2 may be referred to the structures of the first transistor T1, the second transistor T2, the third transistor T3, and the first storage capacitor Cst1, and will not be repeated here.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
The display substrate provided by the present exemplary embodiment may reduce a quantity of the light emitting control lines by disposing the sub-pixel groups sharing the light emitting control sub-circuits, thereby optimizing spatial arrangement and effectively increasing resolution.
The structure of the display substrate will be described below through an example of a manufacturing process of the display substrate. The “patterning process” mentioned in the present disclosure includes processes, such as film layer deposition, photoresist coating, masking and exposure, development, etching, and photoresist stripping. Any one or more of sputtering, evaporation and chemical vapor deposition may be used for deposition, any one or more of spray coating and spin coating may be used for coating, and any one or more of dry etching and wet etching may be used for etching. A “thin film” refers to a layer of thin film manufactured with a certain material on an underlay substrate using a deposition or coating process. If the “thin film” does not need the patterning process in the entire manufacturing process, the “thin film” may also be called a “layer”. If the “thin film” needs the patterning process in the entire manufacturing process, the “thin film” is called a “thin film” before the patterning process is performed and is called a “layer” after the patterning process is performed. The “layer” after the patterning process includes at least one “pattern”.
“A and B are arranged in the same layer” mentioned in the present disclosure refers to that A and B are simultaneously formed by the same patterning process. The “thickness” of the film layer is a size of the film layer in a direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, “the projection of A includes the projection of B” refers to that a boundary of the projection of B falls within a range of a boundary of the projection of A or the boundary of the projection of A is overlapped with the boundary of the projection of B.
In some exemplary embodiments, a process for preparing the display substrate may include following operations, as shown in
(1) A pattern of a first conductive layer is formed.
In some exemplary embodiments, a first conductive thin film is deposited on the underlay substrate 60, and the first conductive thin film is patterned through a patterning process, forming the pattern of the first conductive layer. As shown in
In some exemplary embodiments, an underlay substrate 60 may be a rigid substrate or a flexible substrate. The rigid substrate may include one or more of glass and metal foil sheet. The flexible substrate may include one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fiber. However, the present embodiment is not limited thereto.
(2) A pattern of a semiconductor layer is formed.
In some exemplary embodiments, a first insulating thin film and a semiconductor thin film are deposited in sequence on the underlay substrate 60 on which the aforementioned pattern is formed, and the semiconductor thin film is patterned through the patterning process, forming the first insulating layer 61 and the pattern of the semiconductor layer formed on the first insulating layer 61. As shown in
(3) A pattern of a second conductive layer is formed.
In some exemplary embodiments, a second insulating thin film and a second conductive thin film are deposited in sequence on the underlay substrate 60 on which the aforementioned patterns are formed, and the second conductive thin film is patterned through the patterning process, forming the second insulating layer 62, and the second conductive layer formed on the second insulating layer 62. As shown in
(4) A pattern of a third conductive layer is formed.
In some exemplary embodiments, a third insulating thin film is deposited on the underlay substrate 60 on which the aforementioned patterns are formed, and the third insulating thin film is patterned through the patterning process, forming the pattern of the third insulating layer 63. A plurality of via hole patterns are opened on the third insulating layer. For example, the third insulating layer 63 and the second insulating layer 62 within the first via hole K1, the second via hole K2, the third via hole K3, the fourth via hole K4, the fifth via hole K5, the eighth via hole K8 to the eleventh via hole K11 are etched away to expose the surface of the semiconductor layer; the third insulating layer 63 and the second insulating layer 62 within the half region of the sixth via hole K6 are etched away to expose the surface of the semiconductor layer, and the third insulating layer 63 in the other half region is etched away to expose the surface of the second conductive layer; and the third insulating layer 63, the second insulating layer 62, and the first insulating layer 61 within the seventh via hole K7 are etched away to expose the surface of the first conductive layer. The orthographic projection of the plurality of via holes on the underlay substrate 60 may be rectangular or circular. However, the present embodiment is not limited thereto.
In some exemplary embodiments, a third conductive thin film is deposited on the underlay substrate 60 on which the aforementioned patterns are formed, and the third conductive thin film is patterned through the patterning process, forming the pattern of the third conductive layer on the third insulating layer 63. As shown in
In some exemplary embodiments, a fourth insulating thin film is deposited on the underlay substrate 60 on which the aforementioned patterns are formed, forming the fourth insulating layer. Then, a fifth insulating thin film is coated, and the pattern of the fifth insulating layer is formed by masking, exposuring and developing for the fifth insulating thin film. A plurality of via holes exposing the fourth insulating layer are opened on the fifth insulating layer. Then, the exposed fourth insulating layer is etched to form a plurality of via holes on the fourth insulating layer to expose the surface of the third conductive layer.
In some exemplary implementations, a fourth conductive thin film is deposited on the underlay substrate 60 on which the aforementioned patterns are formed, and the fourth conductive thin film is patterned through the patterning process, forming the pattern of the anode layer on the fifth insulating layer. The anode layer at least includes the first electrode of the first light emitting element of the sub-pixel group, and the first electrode of the second light emitting element. The first electrode of the first light emitting element may be electrically connected to the second electrode of the third transistor of the first sub-pixel circuit through the via hole on the fourth insulating layer and the fifth insulating layer. The first electrode of the second light emitting element may be electrically connected to the second electrode of the sixth transistor of the second sub-pixel circuit through the via hole on the fourth insulating layer and the fifth insulating layer. In some examples, the anode layer may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.
In some exemplary embodiments, a pixel define thin film is coated on the underlay substrate 60 on which the aforementioned patterns are formed, and the pattern of the pixel define layer is formed through masking, exposure, and development processes. The pixel define layer of each sub-pixel group is formed with a first pixel opening exposing the first electrode of the first light emitting element, and a second pixel opening exposing the second electrode of the second light emitting element.
In some exemplary embodiments, a first organic light emitting layer of the first light emitting element may be formed within the formed first pixel opening, wherein the first organic light emitting layer is electrically connected to the first electrode of the first light emitting element; and a second organic light emitting layer of the second light emitting element is formed within the formed second pixel opening, wherein the second organic light emitting layer is electrically connected to the first electrode of the second light emitting element. Afterwards, a transparent conductive thin film is deposited, and the transparent conductive thin film is patterned through the patterning process, forming the patterns of the second electrode of the first light emitting element and the second electrode of the second light emitting element. For example, the second electrodes of the first light emitting element and the second light emitting element may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Afterwards, an encapsulating layer may be formed on the second electrodes of the first light emitting element and the second light emitting element. The encapsulating layer may include a stacked structure of an inorganic material/organic material/inorganic material. However, the present embodiment is not limited thereto.
In some exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of metal materials, e.g., any one or more of Argentum (Ag), Copper (Cu), Aluminum (Al), and Molybdenum (Mo), or alloy materials of the aforementioned metals, e.g., an Aluminum-Neodymium alloy (AlNd) or a Molybdenum-Niobium alloy (MoNb), and may be single-layer structures, or multilayer composite structures such as Mo/Cu/Mo. In some examples, the light shielding performance of the metal material used by the first conductive layer may be stronger than that of the metal material used by the second conductive layer and the third conductive layer. The first insulating layer 61, the second insulating layer 62, the third insulating layer 63, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single layer, multi-layer, or composite layers. The fifth insulating layer and the pixel define layer may be made of the organic material, such as polyimide, acrylic, or polyethylene terephthalate, etc. The semiconductor layer may be made of metal oxide or polysilicon. However, the present embodiment is not limited thereto.
The shown structure and its preparing process in the present disclosure are only exemplary description. In some exemplary implementations, changes in corresponding structures and addition or deletion of the patterning process may be made as practically required. For example, the pixel circuit and the first electrode of the first light emitting element and the first electrode of the second light emitting element may be electrically connected through the connection electrode. However, the present disclosure is not limited thereto.
The preparing process according to the present disclosure may be implemented by using an existing mature preparing equipment, may be well compatible with the existing preparing process, and has advantages of simple process realization, easy practicing, high production efficiency, low production cost, and high yield rate.
In the present exemplary embodiment, by disposing two first auxiliary power lines between adjacent sub-pixel groups within the pixel unit group, the IR drop of the second power line may be further reduced.
For other structures of the display substrate of this embodiment, reference may be made to the description of the aforementioned embodiments, so it will not be repeated here.
In the present exemplary embodiment, the IR drop of the first power line may be reduced by disposing the second auxiliary power line between adjacent sub-pixel groups within the pixel unit group.
In some other exemplary embodiments, the pixel unit group includes six sub-pixel groups arranged in sequence along the second direction X, wherein one first auxiliary power line, one second auxiliary power line, and one sensing line may be located between the third sub-pixel group and the fourth sub-pixel group of the pixel unit group. The second auxiliary power line and the first auxiliary power line may be of the same layer structure, for example, both of them are located in the first conductive layer. The sensing line may be located in the third conductive layer. The second auxiliary power line may be electrically connected to the first doped region of the active layer of the light emitting control transistor through a via hole on the first insulating layer. In some examples, the orthographic projection of the sensing line on the underlay substrate may be located between the orthographic projections of the first auxiliary power line and the second auxiliary power line on the underlay substrate. The orthographic projections of the sensing line, the first auxiliary power line, and the second auxiliary power line on the underlay substrate may not overlap. However, the present embodiment is not limited thereto. For example, the sensing line, the first auxiliary power line and the second auxiliary power line may be located between the second sub-pixel group and the third sub-pixel group, or between the fourth sub-pixel group and the fifth sub-pixel group.
For other structures of the display substrate of this embodiment, reference may be made to the description of the aforementioned embodiments, so it will not be repeated here.
In some other exemplary embodiments, one sensing line and two first auxiliary power lines may be disposed between adjacent sub-pixel groups (e.g., between the third sub-pixel group and the fourth sub-pixel group) within the pixel unit group. The sensing line and the two first auxiliary power lines may both be located in the third conductive layer, and the two first auxiliary power lines may be located respectively on two sides of the sensing line opposite to each other in the second direction X.
In some other exemplary embodiments, one sensing line, one first auxiliary power line, and one second auxiliary power line may be disposed between adjacent sub-pixel groups (e.g., between the third sub-pixel group and the fourth sub-pixel group) within the pixel unit group. The sensing line, the first auxiliary power line, and the second auxiliary power line may all be located in the third conductive layer, and the first auxiliary power line and the second auxiliary power line may be located respectively on opposite two sides of the sensing line in the second direction. The second auxiliary power line may be electrically connected to the first doped region of the active layer of the light emitting control transistor.
For other structures of the display substrate of this embodiment, reference may be made to the description of the aforementioned embodiments, so it will not be repeated here.
The display substrate provided by the present exemplary embodiment may reduce the IR drop of the second power line by disposing a plurality of first auxiliary power lines. Furthermore, by disposing the second auxiliary power line, the IR drop of the first power line may be reduced.
The accompanying drawings in the present disclosure only relate to the structures related to the present disclosure, and other structures may refer to a general design. The embodiments in the present disclosure, i.e., features in the embodiments, may be combined with each other to obtain new embodiments if there is no conflict.
Those of ordinary skill in the art should understand that modification or equivalent replacement may be made to the technical solutions of the present disclosure without departing from the spirit and the scope of the technical solutions of the present disclosure, and should all fall within the scope of the claims of the present disclosure.
The present application is a U.S. National Phase Entry of International Application No. PCT/CN2021/107671 having an international filing date of Jul. 21, 2021. The above-identified application is hereby incorporated by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/107671 | 7/21/2021 | WO |
