Patent Application
20250143111
The present disclosure relates to, but is not limited to, the field of display technologies, in particular to a display substrate and a display apparatus.
Organic Light Emitting Diodes (OLED's) and Quantum-dot Light Emitting Diodes (QLED's) are active light emitting display devices and have advantages of self-illumination, a wide viewing angle, a high contrast ratio, low power consumption, an extremely high reaction speed, lightness and thinness, flexibility, and low cost, etc. A full display with camera technology is a novel technology proposed for increasing a screen-to-body ratio of a display apparatus.
The following is a summary of subject matter described herein in detail. The summary is not intended to limit the protection scope of the claims.
Embodiments of the present disclosure provide a display substrate and a display apparatus.
In one aspect, a display substrate is provided in an embodiment of the present disclosure, which includes a base substrate, a plurality of light emitting elements, and a plurality of pixel circuits. The base substrate includes a first display region and a second display region located on at least one side of the first display region. The plurality of light emitting elements are located in the first display region and the second display region, wherein the plurality of light emitting elements include a plurality of groups of light emitting elements, each group of light emitting elements is arranged along a first direction, the plurality of groups of light emitting elements are arranged along a second direction, at least one group of light emitting elements in the plurality of groups of light emitting elements includes a plurality of first region light emitting elements and a plurality of second region light emitting elements, the plurality of first region light emitting elements are located in the first display region, and the plurality of second region light emitting elements are located in the second display region. The plurality of pixel circuits are located in the second display region, wherein the plurality of pixel circuits include a plurality of groups of pixel circuits, each group of pixel circuits is arranged along the first direction, the plurality of groups of pixel circuits are arranged along the second direction, at least one group of pixel circuits in the plurality of groups of pixel circuits includes a plurality of first type pixel circuits and a plurality of second type pixel circuits, the plurality of first type pixel circuits are arranged at intervals between the plurality of second type pixel circuits. At least one first type pixel circuit in the plurality of first type pixel circuits is electrically connected to at least one first region light emitting element in the plurality of first region light emitting elements, and at least one second type pixel circuit in the plurality of second type pixel circuits is electrically connected to at least one second region light emitting element in the plurality of second region light emitting elements. The plurality of first region light emitting elements at least include a plurality of first light emitting elements emitting light in a first color and a plurality of second light emitting elements emitting light in a second color; the plurality of first type pixel circuits at least include a plurality of first pixel circuits and a plurality of second pixel circuits; the plurality of first light emitting elements are electrically connected to the plurality of first pixel circuits through a plurality of first conductive lines, and the plurality of second light emitting elements are electrically connected to the plurality of second pixel circuits through a plurality of second conductive lines. A plurality of first pixel circuits electrically connected to a plurality of first light emitting elements in the at least one group of light emitting elements and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the at least one group of light emitting elements are located in different groups of pixel circuits; the first direction intersects with the second direction.
In some exemplary implementations, the plurality of first pixel circuits electrically connected to the plurality of first light emitting elements in the at least one group of light emitting elements are located in a pixel circuit group adjacent to a pixel circuit group where the plurality of second pixel circuits electrically connected to the plurality of second light emitting elements in the at least one group of light emitting elements are located, in the second direction.
In some exemplary implementations, the plurality of first region light emitting elements further include a plurality of third light emitting elements emitting light in a third color; the plurality of first type pixel circuits further include a plurality of third pixel circuits, wherein the plurality of third light emitting elements are electrically connected to the plurality of third pixel circuits through a plurality of third conductive lines. A plurality of third pixel circuits electrically connected to a plurality of third light emitting elements in the at least one group of light emitting elements and a plurality of first pixel circuits electrically connected to a plurality of first light emitting elements in the at least one group of light emitting elements are located in a same group of pixel circuits; or, a plurality of third pixel circuits electrically connected to a plurality of third light emitting elements in the at least one group of light emitting elements and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the at least one group of light emitting elements are located in a same group of pixel circuits.
In some exemplary implementations, the first conductive lines, the second conductive lines, and the third conductive lines are of a same layer structure.
In some exemplary implementations, a plurality of third pixel circuits electrically connected to a plurality of third light emitting elements in the at least one group of light emitting elements are closer to the first display region than a plurality of first pixel circuits electrically connected to a plurality of first light emitting elements and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the at least one group of light emitting elements.
In some exemplary implementations, the at least one third pixel circuit is electrically connected to n1 third light emitting elements and configured to drive the n1 third light emitting elements to emit light, and the at least one third pixel circuit is electrically connected to n2 third light emitting elements and configured to drive the n2 third light emitting elements to emit light, where both n1 and n2 are integers greater than or equal to 2 and n1 is different from n2.
In some exemplary implementations, the n1 third light emitting elements serve as first light emitting units, and the n2 third light emitting elements serve as second light emitting units, the first light emitting units and the second light emitting units are arranged at intervals along the first direction or periodically in an order of a first light emitting unit, a second light emitting unit, a second light emitting unit and a first light emitting unit.
In some exemplary implementations, the display substrate further includes a plurality of third connection lines located in the first display region, and the n1 third light emitting elements or the n2 third light emitting elements are electrically connected by one third connection line.
In some exemplary implementations, the plurality of third conductive lines electrically connected to the plurality of third pixel circuits and the plurality of first conductive lines electrically connected to the plurality of first pixel circuits, which are located in a same group of pixel circuits, are located on opposite sides of the group of pixel circuits in the second direction; or, the plurality of third conductive lines electrically connected to the plurality of third pixel circuits and the plurality of second conductive lines electrically connected to the plurality of second pixel circuits, which are located in a same group of pixel circuits, are located on opposite sides of the group of pixel circuits in the second direction.
In some exemplary implementations, the light in the first color is red light, the light in the second color is blue light, and the light in the third color is green light.
In some exemplary implementations, at least one first pixel circuit of the plurality of first pixel circuits is electrically connected to m1 first light emitting elements and is configured to drive the m1 first light emitting elements to emit light; at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to m2 second light emitting elements and is configured to drive the m2 second light emitting elements to emit light, wherein both m1 and n2 are integers greater than or equal to 2.
In another aspect, a display substrate is provided in an embodiment of the present disclosure, which includes the aforementioned display substrate.
Other aspects of the present disclosure may be comprehended after the drawings and the detailed descriptions are read and understood.
Accompanying drawings are used for providing further understanding of technical solutions of the present disclosure, constitute a part of the specification, and are used for explaining the technical solutions of the present disclosure together with embodiments of the present disclosure, but do not constitute limitations on the technical solutions of the present disclosure. Shapes and sizes of one or more components in the drawings do not reflect actual scales, but are only intended to schematically describe contents of the present disclosure.
The embodiments of the present disclosure will be described below with reference to the drawings in detail. Implementations may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that modes and contents may be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to the contents recorded in the following implementations only. The embodiments and features in the embodiments of the present disclosure may be randomly combined with each other if there is no conflict.
In the drawings, a size of one or more constituent elements, a thickness of a layer, or a region is sometimes exaggerated for clarity. Therefore, one mode of the present disclosure is not necessarily limited to the size, and a shape and a size of one or more components in the drawings do not reflect an actual scale. In addition, the accompanying drawings schematically illustrate ideal examples, and a mode of the present disclosure is not limited to shapes, numerical values, or the like shown in the drawings.
Ordinal numerals “first”, “second”, “third”, etc., in the specification are set not to form limits in numbers but only to avoid confusion between composition elements. In the present disclosure, “a plurality of” represents two or more than two.
In the specification, for convenience, expressions “central”, “above”, “below”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, etc., indicating directional or positional relationships are used to illustrate positional relationships between the composition elements, not to indicate or imply that involved apparatuses or elements are required to have specific orientations and be structured and operated with the specific orientations but only to easily and simply describe the present specification, and thus should not be understood as limitations on the present disclosure. The positional relationships between the constituent elements are changed as appropriate according to a direction with which the constituent elements are described. Therefore, appropriate replacements based on situations are allowed, which is not limited to the expressions in the specification.
In the specification, unless otherwise specified and defined, terms “mounting”, “mutual connection”, and “connection” should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or a connection; it may be a direct connection, an indirect connection through a middleware, or internal communication inside two elements. Those of ordinary skills in the art may understand meanings of the aforementioned terms in the present disclosure according to situations.
In the specification, “electrical connection” includes connection of composition elements through an element with some electrical function. The “element having some electrical function” is not particularly limited as long as electrical signals between the connected constituent elements may be transmitted. Examples of the “element having some electrical function” not only include an electrode and a wiring, but also include a switching element such as a transistor, a resistor, an inductor, a capacitor, another element with multiple functions, etc.
In the specification, a transistor refers to an element which at least includes three terminals, i.e., a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and a current can flow through the drain, the channel region, and the source. In the specification, the channel region refers to a region through which a current mainly flows.
In the specification, a first electrode may be a drain and a second electrode may be a source, or, a first electrode may be a source and a second electrode may be a drain. In a case that transistors with opposite polarities are used, or in a case that a direction of a current is changed during operation of a circuit, or the like, functions of the “source” and the “drain” are sometimes interchangeable. Therefore, the “source” and the “drain” are interchangeable in the specification.
In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above −10° and below 10°, and thus may include a state in which the angle is above −5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80° and below 100°, and thus may include a state in which the angle is above 85° and below 95°.
A triangle, rectangle, trapezoid, pentagon, or hexagon, etc. in the specification is not strictly defined, and it may be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There may be some small deformations caused by tolerance, and there may be a chamfer, an arc edge, and deformation, etc.
A “light transmittance” in the present disclosure refers to an ability of light to pass through a medium, and is a percentage of luminous flux passing through a transparent or translucent body to its incident luminous flux.
In the present disclosure, “about” and “substantially” refer to that a boundary is not defined strictly and a case within a range of process and measurement errors is allowed. In the present disclosure, “substantially the same” refers to a case where numerical values differ by less than 10%.
A display substrate is provided in at least one embodiment of the present disclosure, which includes a base substrate, a plurality of light emitting elements and a plurality of pixel circuits. The base substrate includes a first display region and a second display region located on at least one side of the first display region. The plurality of light emitting elements are located in the first display region and the second display region. The plurality of light emitting elements include a plurality of groups of light emitting elements, each group of light emitting elements is arranged in a first direction, and the plurality of groups of light emitting elements are arranged in a second direction. At least one group of light emitting elements in the plurality of groups of light emitting elements includes a plurality of first region light emitting elements and a plurality of second region light emitting elements, the plurality of first region light emitting elements are located in the first display region, and the plurality of second region light emitting elements are located in the second display region. The plurality of pixel circuits are located in the second display region, wherein the plurality of pixel circuits include a plurality of groups of pixel circuits, each group of pixel circuits is arranged along the first direction, the plurality of groups of pixel circuits are arranged along the second direction. At least one group of pixel circuits in the plurality of groups of pixel circuits includes a plurality of first type pixel circuits and a plurality of second type pixel circuits, the plurality of first type pixel circuits are arranged at intervals between the plurality of second type pixel circuits. At least one first type pixel circuit in the plurality of first type pixel circuits is electrically connected to at least one first region light emitting element in the plurality of first region light emitting elements, and at least one second type pixel circuit in the plurality of second type pixel circuits is electrically connected to at least one second region light emitting element in the plurality of second region light emitting elements. The plurality of first region light emitting elements at least include a plurality of first light emitting elements emitting light in a first color and a plurality of second light emitting elements emitting light in a second color. The plurality of second type pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits. A plurality of first light emitting elements are electrically connected to the plurality of first pixel circuits through a plurality of first conductive lines. A plurality of second light emitting elements are electrically connected to the plurality of second pixel circuits through a plurality of second conductive lines. A plurality of first pixel circuits electrically connected to a plurality of first light emitting elements in the at least one group of light emitting elements and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the at least one group of light emitting elements are located in different groups of pixel circuits. The first direction intersects with the second direction. For example, the first direction may be perpendicular to the second direction.
In some examples a group of light emitting elements may be a row of light emitting elements, and a group of pixel circuits may be a row of pixel circuits. For example, a plurality of first pixel circuits electrically connected to a plurality of first light emitting elements in one row of light emitting elements and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the row of light emitting elements are located in different rows of pixel circuits.
According to the display substrate provided in this example, by disposing a plurality of first pixel circuits electrically connected to a plurality of first light emitting elements in the at least one group of light emitting elements and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the at least one group of light emitting elements being located in different groups of pixel circuits, lengths of the first conductive lines and the second conductive lines can be shortened, thereby reducing a difference between loads in different conductive lines, reducing a difference between brightness in the first display region and in the second display region, and improving a display effect of the display substrate.
In some exemplary implementations, the plurality of first pixel circuits electrically connected to the plurality of first light emitting elements in the at least one group of light emitting elements may be located in a pixel circuit group adjacent to a pixel circuit group where the plurality of second pixel circuits electrically connected to the plurality of second light emitting elements in the at least one group of light emitting elements are located, in the second direction. For example, one row of first region light emitting elements may correspond to two rows of first type pixel circuits. In this way, a length of a conductive line connecting a first region light emitting element with a first type pixel circuit can be shortened.
In some exemplary implementations, the plurality of first region light emitting elements may further include a plurality of third light emitting elements emitting light in a third color. The plurality of first type pixel circuits may further include a plurality of third pixel circuits, wherein the plurality of third light emitting elements are electrically connected to the plurality of third pixel circuits through a plurality of third conductive lines. A plurality of third pixel circuits electrically connected to a plurality of third light emitting elements in the at least one group of light emitting elements may be located in a same group of pixel circuits as a plurality of first pixel circuits electrically connected to a plurality of first light emitting elements in the at least one group of light emitting elements; or, a plurality of third pixel circuits electrically connected to a plurality of third light emitting elements in the at least one group of light emitting elements may be located in a same group of pixel circuits as a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements in the at least one group of light emitting elements. Arrangement of the pixel circuits in this example is beneficial to shortening the length of the conductive line connecting the first region light emitting element and the first type pixel circuit. However, the embodiment is not limited thereto. For example, a plurality of third pixel circuits electrically connected to a plurality of third light emitting elements of at least one group of light emitting elements may be located in different groups of pixel circuits from a plurality of first pixel circuits electrically connected to a plurality of first light emitting elements, and a plurality of second pixel circuits electrically connected to a plurality of second light emitting elements. For example, one row of first region light emitting elements may be electrically connected to three rows of first type pixel circuits, correspondingly.
In some exemplary implementations, the first conductive lines, the second conductive lines, and the third conductive lines may be of a same layer structure. For example, the first conductive lines, the second conductive lines and the third conductive lines may be fabricated with a transparent conductive material (e.g. Indium Tin Oxide (ITO)).
In some exemplary implementations, a plurality of third pixel circuits electrically connected with a plurality of third light emitting elements in the at least one group of light emitting elements may be closer to the first display region than a plurality of first pixel circuits electrically connected with a plurality of first light emitting elements and a plurality of second pixel circuits electrically connected with a plurality of second light emitting elements. For example, the light in the first color may be red light, the light in the second color may be blue light, and the light in the third color light may be green light. In this example, based on an arrangement order of the first type pixel circuits, green light emitting elements are preferred (i.e., the first type pixel circuits connected to the green light emitting elements are preferentially arranged close to the first display region), so that a display defect caused by large differences between the lengths of conductive lines can be alleviated or eliminated.
Solutions of the embodiments will be described below through some examples.
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In some examples, the display region AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light emitting element. The pixel circuit may be configured to drive a connected light emitting element. For example, the pixel circuit is configured to provide a drive current to drive the light emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be of a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin film transistor, C refers to a capacitor, a number before T represents a quantity of thin film transistors in the circuit, and a number before C represents a quantity of capacitors in the circuit.
In some examples, the plurality of transistors in the pixel circuit may be P type transistors or may be N type transistors. Same type of transistors in the pixel circuit may simplify a process flow, reduce a process difficulty of the display substrate, and improve a yield of a product. In some other examples, the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors.
In some examples, low temperature poly-silicon thin film transistors, or oxide thin film transistors, or low temperature poly-silicon thin film transistors and oxide thin film transistors may be used as the plurality of transistors in the pixel circuit. Low Temperature Poly Silicon (LTPS) is adopted for an active layer of a low temperature poly silicon thin film transistor and an oxide semiconductor (Oxide) is adopted for an active layer of an oxide thin film transistor. The low temperature poly silicon thin film transistor has advantages such as a high migration rate and fast charging, and the oxide thin film transistor has advantages such as a low leakage current. The low temperature poly silicon thin film transistor and the oxide thin film transistor are integrated on one display panel, that is, an LTPS+Oxide (LTPO for short) display panel, advantages of both the low temperature poly silicon thin film transistor and the oxide thin film transistor may be utilized, so that low-frequency drive may be achieved, power consumption may be reduced, and display quality may be improved.
In some examples, the light emitting element may be any one of a Light Emitting Diode (LED), an Organic Light emitting Diode (OLED), a Quantum dot Light emitting Diode (QLED), a Micro LED (including a mini-LED or a micro-LED) and the like. For example, the light emitting element may be an OLED, and the light emitting element may emit red light, green light, blue light, or white light, etc. under drive of a pixel circuit corresponding to the light emitting element. A color of light emitted by the light emitting element may be determined as required. In some examples, the light emitting element may include an anode, a cathode, and an organic emitting layer located between the anode and the cathode. The anode of the light emitting element may be electrically connected with a corresponding pixel circuit. However, the embodiment is not limited thereto.
In some examples, one pixel unit of the display region AA may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the embodiment is not limited thereto. In some examples, one pixel unit may include four sub-pixels, wherein the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.
In some examples, a shape of the light emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When one pixel unit includes three sub-pixels, light emitting elements of the three sub-pixels may be arranged in a manner to stand side by side horizontally, in a manner to stand side by side vertically, or in a manner like a Chinese character “”. When one pixel unit includes four sub-pixels, light emitting elements of the four sub-pixels may be arranged in a manner to stand side by side horizontally, in a manner to stand side by side vertically, or in a manner of a square. However, the embodiment is not limited thereto.
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In some examples, since the second display region A2 is not only provided with the second type pixel circuits 42 electrically connected to the second region light emitting elements, but also provided with the first type pixel circuits 41 electrically connected to the first region light emitting elements 10, a quantity of pixel circuits of the second display region A2 may be greater than a quantity of second region light emitting elements. In some examples, as shown in
In other examples, original b rows of pixel circuits may be compressed along a second direction D2, so that an arrangement space of one row of pixel circuits is added, and the space occupied by the b rows of pixel circuits before compression and the space occupied by b+1 rows of pixel circuits after compression are the same. Herein, b may be an integer greater than 1. Or, a region for disposing a newly-added pixel circuit may be obtained by reducing a dimension of a second type pixel circuit in the first direction D1 and the second direction D2.
In an embodiment of the present disclosure, a group of pixel circuits may include a plurality of pixel circuits sequentially arranged along the first direction. In this example, a group of pixel circuits is a row of pixel circuits, and the row of pixel circuits may all be adjacent to a same gate line (e.g. a scan line). A group of light emitting elements may include a plurality of first region light emitting elements and a plurality of second region light emitting elements arranged in the first direction.
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In this example, a light emitting region of a light emitting element refers to a stacked region of the anode, the organic light emitting layer and the cathode of the light emitting element, that is, a connection region between the anode exposed by a pixel opening of a pixel definition layer, and the organic light emitting layer as well as the cathode.
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In this example, the first type pixel circuits electrically connected to the light emitting elements emitting light in different colors in the first region light emitting elements in the same row may be located in different rows, which is beneficial to shortening a length of conductive lines (e.g. the first conductive line to the third conductive line) connecting the first region light emitting elements and the first type pixel circuits, thereby facilitating reducing a difference between loads of different conductive lines, reducing a difference between brightness in the first display region and in the second display region, and further improving the display effect of the display substrate. In other examples, pixel circuits electrically connected with the first, second, and third light emitting elements of first region light emitting elements in a same row may be located in different rows. For example, one row of first region light emitting elements may correspond to three rows of first type pixel circuits. Or, a first pixel circuit electrically connected with a first light emitting element and a first pixel circuit electrically connected with a third light emitting element, of first region light emitting elements in a same row may be located in a same row, while a second pixel circuit electrically connected with a second light emitting element and the first pixel circuit electrically connected with the first light emitting element may be located in different rows.
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In some examples, the first insulation layer 211 to the fourth insulation layer 214 may all be inorganic insulation layers, and the fifth insulation layer 215 to the seventh insulation layer 217 may all be organic insulation layers. The fifth insulation layer 215 to the seventh insulation layer 217 may also be referred to as planarization layers. However, the embodiment is not limited thereto. In some other examples, only the fifth insulation layer may be disposed between the first source-drain metal layer 204 and the second source-drain metal layer 205.
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Exemplary description is made below for a structure and a manufacturing process of a display substrate. A “patterning process” mentioned in the embodiments of the present disclosure includes a treatment such as photoresist coating, mask exposure, development, etching, and photoresist stripping for a metal material, an inorganic material, or a transparent conductive material, and includes a treatment such as organic material coating, mask exposure, and development for an organic material. Deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition, coating may be any one or more of spray coating, spin coating, and inkjet printing, and etching may be any one or more of dry etching and wet etching, the present disclosure is not limited thereto. A “thin film” refers to a layer of thin film made of a material on a base substrate by using deposition, coating, or other processes. If the “thin film” does not need to be processed through a patterning process in the entire manufacturing process, the “thin film” may also be called a “layer”. If the “thin film” needs to be processed through the patterning process in the entire manufacturing process, the “thin film” is called a “thin film” before the patterning process is performed and is called a “layer” after the patterning process is performed. At least one “pattern” is contained in the “layer” which has been processed through the patterning process. “A and B are of a same layer structure” or “A and B are disposed in a same layer” mentioned in the embodiments of the present disclosure means that A and B are formed simultaneously through a same patterning process, or surfaces of A and B close to a base substrate have basically a same distance from the base substrate, or the surfaces of A and B close to the base substrate are in direct contact with a same film layer. A “thickness” of a film layer is a dimension of the film layer in a direction perpendicular to the display substrate. In an exemplary implementation of the present disclosure, “an orthographic projection of B being within a range of an orthographic projection of A” or “an orthographic projection of A containing an orthographic projection of B” means that a boundary of the orthographic projection of B falls within a range of a boundary of the orthographic projection of A, or the boundary of the orthographic projection of A is overlapped with the boundary of the orthographic projection of B.
In some exemplary implementations, a manufacturing process of the display substrate may include following operations.
(1) A base substrate is provided. In some examples, the base substrate 100 may be a rigid substrate, or may be a flexible substrate. For example, the rigid base substrate may be made of, but not limited to, one or more of glass and quartz. The flexible base substrate may be made of, but not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible base may include a first flexible material layer, a first inorganic material layer, a second flexible material layer and a second inorganic material layer which are stacked. The first flexible material layer and the second flexible material layer may be made of a material such as polyimide (PI), polyethylene terephthalate (PET), or a polymer soft film on which surface treatment is performed, and a material of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., which are used to improve resistance to water and oxygen of the base.
(2) A semiconductor layer is formed. In some examples, a semiconductor thin film is deposited on the base substrate 100, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer 201 in a second region A2. In some examples, a material of the semiconductor layer 201 may be amorphous Silicon (a-Si), polycrystalline Silicon (p-Si), hexathiophene, polythiophene, or other materials.
In some examples, the semiconductor layer 201 of the second display region A2 may include active layers of a plurality of transistors of a plurality of pixel circuits (e.g. an active layer of a first transistor T1). An active layer of a transistor may include a first region, a second region, and a channel region located between the first region and the second region. In some examples, the first region and the second region of the active layer may be interpreted as a source electrode or a drain electrode of a transistor. A part of the active layer between the transistors may be interpreted as a trace doped with impurities, and may be used for electrically connecting the transistors. The channel region may not be doped with impurities, and has characteristics of a semiconductor. The first region and the second region located on two sides of the channel region may be doped with impurities and thus have electrical conductivity. The impurities may be changed according to a type of a transistor. However, the embodiment is not limited thereto.
(3) A first gate metal layer is formed. In some examples, a first insulation thin film and a first conductive thin film are sequentially deposited on the base substrate 100 where the aforementioned structure is formed, and the first conductive thin film is patterned through a patterning process to form a first insulation layer 211 covering the semiconductor layer 201, and a first gate metal layer 202 disposed on the first insulation layer 211 in the second display region A2. In some examples, the first gate metal layer 202 may include gate electrodes of transistors and one plate of each of storage capacitors of a plurality of pixel circuits (e.g., including a gate electrode of the first transistor T1, a first plate of a first capacitor C1).
(4) A second gate metal layer is formed. In some examples, a second insulation thin film and a second conductive thin film are sequentially deposited on the base substrate 100 where the aforementioned structures are formed, the second conductive thin film is patterned through a patterning process to form a second insulation layer 212, and a second gate metal layer 203 disposed on the second insulation layer 212 in the second display region A2. In some examples, the second gate metal layer 203 may include another plate of each of storage capacitors of a plurality of pixel circuits (e.g. including a second plate of the first capacitor C1).
(5) A first source-drain metal layer is formed. In some examples, a third insulation thin film is deposited on the base substrate 100 where the aforementioned patterns are formed, and the third insulation thin film is patterned through a patterning process to form a third insulation layer 213. The third insulation layer 213 of the second display region A2 may be provided with a plurality of vias, which may expose, for example, surfaces of the semiconductor layer 201, the first gate metal layer 202, and the second gate metal layer 203, respectively. Subsequently, a third conductive thin film is deposited and patterned through a patterning process to form a first source-drain metal layer 204 on the third insulation layer 213 of the second display region A2. In some examples, the first source-drain metal layer 204 may include first electrodes and second electrodes of transistors of a plurality of pixel circuits (e.g. including a first electrode and a second electrode of the first transistor T1).
(6) A second source-drain metal layer is formed. In some examples, a fourth insulation thin film is deposited on the base substrate 100 where the aforementioned patterns are formed to form a fourth insulation layer 214. Subsequently, a fifth insulation thin film is coated and patterned through a patterning process to form a fifth insulation layer 215. In some examples, after a via or groove is formed in the fifth insulation layer 215, the fourth insulation layer 214 may be etched to form a via or groove provided in the fourth insulation layer 214 to expose a surface of the first source-drain metal layer 204. Subsequently, a fourth conductive thin film is deposited and patterned through a patterning process to form a second source-drain metal layer 205 on the fifth insulation layer 215 of the second display region A2. In some examples, the second source-drain metal layer 205 may include a plurality of first anode connection electrodes. The first anode connection electrodes may be configured to be electrically connected to a first pixel circuits or a second pixel circuit.
(7) A second transparent conductive layer is formed. In some examples, a sixth insulation thin film is coated on the base substrate 100 where the aforementioned patterns are formed, and the sixth insulation thin film is patterned through a patterning process to form a sixth insulation layer 216. Subsequently, a second transparent conductive thin film is deposited and patterned through a patterning process to form a second transparent conductive layer 302. In some examples, the second transparent conductive layer 302 may include a plurality of second anode connection electrodes, and a plurality of first conductive lines 34, a plurality of second conductive lines, and a plurality of third conductive lines, which are located in the second display region A2. A second anode connection electrode may be electrically connected to a first anode connection electrode electrically connected to a second type pixel circuit. A first conductive line 31, a second conductive line, and a third conductive line may be electrically connected to a first anode connection electrode electrically connected to a first type pixel circuit. The first conductive line 31, the second conductive line, and the third conductive line may extend from the second display region A2 to the first display region A1.
(8) A first transparent conductive layer is formed. In some examples, a seventh insulation thin film is coated on the base substrate 100 where the aforementioned patterns are formed, and the seventh insulation thin film is patterned through a patterning process to form a seventh insulation layer 217. Subsequently, a first transparent conductive thin film is deposited and patterned through a patterning process to form a first transparent conductive layer 301 in the first display region A1. In some examples, the first transparent conductive layer 301 may include a plurality of first connection lines 31, a plurality of second connection lines, and a plurality of third connection lines.
(9) An anode layer, a pixel definition layer, an organic light emitting layer, a cathode layer and an encapsulation structure layer are formed in sequence. In some examples, an anode thin film is deposited on the base substrate 100 where the aforementioned patterns are formed, and the anode thin film is patterned through a patterning process to form an anode layer 401. For example, the anode layer 401 may include an anode 210 of a fourth light emitting element located in the second display region A2 and an anode 110 of a first light emitting element located in the first display region A1. There may be no insulation layer between the anode layer 210 and the first transparent conductive layer 301 of the first display region A1. The first connection line 31 of the first transparent conductive layer 301 may be in direct contact with the anode 110 of the first light emitting element. A first connection line 31 electrically connected with an anode 110 of a first light emitting element may be electrically connected to a first conductive line 34 through a via opened in the seventh insulation layer 217 to achieve an electrical connection with a first pixel circuit of the second display region A2. An anode 210 of a fourth light emitting element may be electrically connected to a second anode connection electrode through a via opened in the seventh insulation layer 217 to achieve an electrical connection with a second type pixel circuit. However, the embodiment is not limited thereto. In some other examples, an anode of a first light emitting element may be electrically connected to the first conductive line 34 through a via opened in the seventh insulation layer 217.
Subsequently, a pixel definition thin film is coated on the base substrate 100 where the aforementioned patterns are formed, and a pixel definition layer 402 is formed through mask, exposure, and development processes. The pixel definition layer may be formed with a plurality of pixel openings exposing the anode layer. Subsequently, an organic light emitting layer is formed within the pixel openings formed. For example, an organic light emitting layer 211 of a fourth light emitting element of the second display region A2 is connected to an anode 210, and an organic light emitting layer 111 of a first light emitting element of the first display region A1 is connected to an anode 110. Subsequently, a cathode thin film is deposited, the cathode thin film is patterned through a patterning process to form a cathode layer 403, and the cathode layer 403 is electrically connected to the organic emitting layer and a second power supply line, respectively. In some examples, an encapsulation structure layer 500 is formed on the cathode layer 403. The encapsulation structure layer 500 may include a stacked structure of inorganic material/organic material/inorganic material.
In some exemplary implementations, the first gate metal layer 202, the second gate metal layer 203, the first source-drain metal layer 204 and the second source-drain metal layer 205 may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Mo/Cu/Mo. The first insulation layer 211, the second insulation layer 212, the third insulation layer 213, and the fourth insulation layer 214 may be made of any one or more of Silicon Oxide (SiOx), Silicon Nitride (SiNx), and Silicon Oxynitride (SiON), and may be a single layer, a multiple-layer, or a composite layer. The first insulation layer 211 and the second insulation layer 212 may be referred to as Gate Insulation (GI) layers, the third insulation layer 213 may be referred to as an Interlayer Dielectric (ILD) layer, and the fourth insulation layer 214 may be referred to as a passivation layer. The fifth insulation 215, the sixth insulation layer 216, and the seventh insulation layer 217 may be made of an organic material, such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer 402 may be made of an organic material, such as polyimide, acrylic, or polyethylene terephthalate. The anode layer 401 may be made of a reflective material such as a metal, and the cathode layer 403 may be made of a transparent conductive material. However, the embodiment is not limited thereto.
The structure and the manufacturing process of the display substrate according to the embodiments of the present disclosure are described only as an example. In some exemplary implementations, a corresponding structure may be changed and a patterning process may be added or removed according to actual needs. For example, the display substrate may not include a second source-drain metal layer. However, the embodiments of the present disclosure are not limited thereto.
In the manufacturing process of the display substrate according to the embodiment, the first transparent conductive layer, the second transparent conductive layer and the seventh insulation layer are provided, which may achieve the electrical connection between the first type pixel circuits and the first region light emitting elements. Compared with a manufacturing solution by using three transparent conductive layers and three insulation layers, this example may simplify the manufacturing process, is easy to implement, has high production efficiency, low production cost and high yield.
According to the display substrate provided in the embodiment, first type pixel circuits electrically connected with light emitting elements emitting light in different colors in a row of first region light emitting elements may be located in at least two rows, which can be beneficial to shortening a length of a conductive line connecting a first region light emitting element with a first type pixel circuit, thereby reducing a difference between brightness in the first display region and in the second display region, and improving display effect of the display substrate.
In this example, a plurality of first region light emitting elements are driven by one first type pixel circuit, and the first type pixel circuits electrically connected to light emitting elements emitting light in different colors in a row of first region light emitting elements are located in at least two rows, which is beneficial to shortening a length of conductive lines, reducing a difference between brightness in the first display region and in the second display region, thereby ensuring the display image quality, and reducing the quantity of connection lines and the product cost.
A display apparatus is also provided in an embodiment of the present disclosure, which includes the aforementioned display substrate.
In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display apparatus may be any product or component with a display function such as an OLED display, a cell phone, a tablet, a television, a display, a laptop, a digital photo frame, and a navigator, which is not limited in the embodiments of the present disclosure.
The drawings of the present disclosure only involve structures involved in the present disclosure, and other structures may refer to conventional designs. The embodiments of the present disclosure, i.e., features in the embodiments, may be combined with each other to obtain new embodiments if there is no conflict. Those of ordinary skills in the art should understand that modifications or equivalent replacements may be made to the technical solutions of the present disclosure without departing from the essence and scope of the technical solutions of the present disclosure, and shall all fall within the scope of the claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211111570.9 | Sep 2022 | CN | national |
The present application is a U.S. National Phase Entry of International Application No. PCT/CN2023/112180 having an international filing date of Aug. 10, 2023, which claims the priority to the Chinese Patent Application No. 202211111570.9, entitled “DISPLAY SUBSTRATE AND DISPLAY APPARATUS”, filed on Sep. 13, 2022, to the CNIPA. The above-identified applications are incorporated herein by reference in their entireties.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/112180 | 8/10/2023 | WO |
