The present disclosure relates to the field of display technologies, in particular to a display substrate and a display device.
With the continuous development of display technology, display products have been widely used, display products with high resolution and high refresh rate are becoming more and more popular. However, medium-sized and large-sized display products are not able to realize the function of products with high refresh rate due to the limitation of large load.
The following is a summary of the subject matter described in detail herein. The summary is not intended to limit the scope of the claims.
In an aspect, the present disclosure provides a display substrate including:
The plurality of transistors include one or more active patterns, and an active pattern of each transistor includes a channel region and a conductive region. An active pattern of the first transistor includes a first channel region, an active pattern of the second transistor includes a second channel region, the first channel region is located on a side of the first scanning line away from the second scanning line, and the second channel region is located on a side of the second scanning line away from the first scanning line.
Optionally, the display substrate further includes a plurality of signal lines, and the plurality of signal lines includes a first signal line and a second signal line. The first signal line is coupled to a first electrode of the first transistor, the second signal line is coupled to a first electrode of the second transistor, and the first transistor T1 is configured to transmit a voltage signal of the first signal line to a second electrode of the first transistor under control of a first scanning line signal. The second transistor is configured to transmit a voltage signal of the second signal line to a second electrode of the second transistor under control of a second scanning line signal. The second electrode of the first transistor and the second electrode of the second transistor are coupled to a first node.
Optionally, the plurality of scanning lines further includes a third scanning line, and the plurality of signal lines further includes a power source line. The third scanning line includes a first branch scanning line extending along the first direction and a second branch scanning line extending along the second direction, the first branch scanning line is coupled to the second branch scanning line. The plurality of transistors further includes a third transistor and a driving transistor. The storage capacitor includes a first electrode plate and a second electrode plate. A second electrode of the third transistor, a gate electrode of the driving transistor and the first electrode plate of the storage capacitor are coupled to a second node, a gate electrode of the third transistor is coupled to the third scanning line, and a first electrode of the third transistor is coupled to the first node. The third transistor is configured to transmit a voltage of the first node to the second node under control of a third scanning line signal. For sub-pixels in a same row, the first branch scanning line is located on a side of the first scanning line away from the second scanning line.
Optionally, the plurality of transistors further includes a fourth transistor and a fifth transistor, the plurality of scanning lines further includes a light-emitting scanning line and a fourth scanning line, and the plurality of signal lines further includes a third signal line. The light-emitting scanning line extends along the first direction. A gate electrode of the fourth transistor is coupled to the light-emitting scanning line, a first electrode of the fourth transistor is coupled to the power source line, and a second electrode of the fourth transistor is coupled to a first electrode of the driving transistor. The fourth transistor is configured to transmit a voltage signal from the power source line to a second electrode of the driving transistor under control of a light-emitting scanning line signal. A gate electrode of the fifth transistor is coupled to the fourth scanning line, a first electrode of the fifth transistor is coupled to the third signal line, and a second electrode of the fifth transistor is coupled to the light-emitting element. The fifth transistor is configured to transmit a voltage signal of the third signal line to the light-emitting element under control of a fourth scanning line signal.
Optionally, the power source line includes a first power source line extending along the first direction and a second power source line extending along the second direction, and the first power source line is coupled to the second power source line. For the sub-pixels in the same row, the first power source line is located on a side of the light-emitting scanning line away from the first scanning line. The third signal line includes a first sub-line extending along the first direction and a second sub-line extending along the second direction, and the first sub-line is coupled to the second sub-line. The fourth scanning line extends along the first direction, and for the sub-pixels in the same row, the fourth scanning line is located on a side of the first power source line away from the light-emitting scanning line. The first sub-line is located on a side of the fourth scanning line away from the first scanning line.
Optionally, pixel driving circuits of the plurality of sub-pixels are arranged in M*N, where M and N are each a positive integer greater than or equal to 1, and at least two sub-pixels in a same column are coupled to a same first signal line.
Optionally, the display substrate further includes a plurality of control regions, and at least one control region includes at least one repeat unit. The third scanning line is coupled to a gate electrode of a third transistor in each repeat unit for controlling the turn-on or turn-off of the third transistor in each repeat unit in a corresponding control region. Along the first direction, in a same control region, first branch scanning lines coupled to sub-pixels respectively in the repeat unit are coupled to each other, and first branch scanning lines are disconnected from each other between the control regions.
Optionally, an orthographic projection of the second power source line onto the base substrate does not overlap an orthographic projection of the first branch scanning line onto the base substrate.
Optionally, an orthographic projection of the first power source line onto the base substrate overlaps an orthographic projection of the second branch scanning line onto the base substrate.
Optionally, in a direction perpendicular to the base substrate, the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are arranged sequentially on the base substrate. The active layer includes the active patterns of the plurality of transistors, and the active pattern includes the channel region and the conductive region. The first conductive layer includes gate electrodes of the plurality of transistors, the second branch scanning line and the second sub-line. The second conductive layer includes a second electrode plate of the storage capacitor. The third conductive layer includes the first scanning line, the second scanning line, the first branch scanning line, the light-emitting scanning line, the fourth scanning line, the second signal line, the first power source line and the first sub-line. The fourth conductive layer includes the first signal line and the second power source line.
Optionally, a spacing between the second signal line and the second scanning line is greater than or equal to a spacing between the first scanning line and the second scanning line.
Optionally, an interlayer insulation layer is arranged between the second conductive layer and the third conductive layer, the interlayer insulation layer includes a first via-hole structure, and the first via-hole structure includes a first via-hole and a second via-hole. An orthographic projection of a gate electrode of the first transistor onto the base substrate at least partially overlaps an orthographic projection of the first scanning line onto the base substrate at a first overlapping region, and an orthographic projection of the first via-hole onto the base substrate is in the first overlapping region. An orthographic projection of a gate electrode of the second transistor onto the base substrate at least partially overlaps an orthographic projection of the second scanning line onto the base substrate at a second overlapping region, and an orthographic projection of the second via-hole onto the base substrate is in the second overlapping region. A distance between the first via-hole and the second via-hole is greater than a distance between the first scanning line and the second scanning line.
Optionally, the first branch scanning line includes a first connection member, and for sub-pixels in a same row, the first connection member is located on a side of the first branch scanning line away from the light-emitting scanning line. The first via-hole structure includes a ninth via-hole, the second branch scanning line is coupled to the first branch scanning line through the ninth via-hole, and an orthographic projection of the ninth via-hole onto the base substrate is within an orthographic projection of the first connection member onto the base substrate.
Optionally, the first electrode plate of the storage capacitor includes a first electrode sub-plate and a second electrode sub-plate, the first electrode sub-plate is located in the first conductive layer, and the second electrode sub-plate is located in the third conductive layer. The third conductive layer includes a second connection member. The first via-hole structure includes a fifteenth via-hole and a sixteenth via-hole, the second electrode sub-plate is coupled to the first electrode sub-plate through the fifteenth via-hole, and the second electrode sub-plate is coupled to the second node through the sixteenth via-hole. Orthographic projections of the fifteenth via-hole and the sixteenth via-hole onto the base substrate are within an orthographic projection of the second connection member onto the base substrate.
Optionally, the display substrate further includes a first organic layer arranged on a side of the third conductive layer away from the base substrate, the first organic layer includes a second via-hole structure, the first via-hole structure includes a twelfth via-hole, and the second via-hole structure includes an eighteenth via-hole. The first signal line is coupled to a first electrode of the first transistor through the twelfth via-hole and the eighteenth via-hole, and there is an overlapping region in orthographic projections of the eighteenth via-hole and the twelfth via-hole onto the base substrate. The third conductive layer further includes a third connection member, and an orthographic projection of the third connection member onto the base substrate covers the orthographic projections of the eighteenth via-hole and the twelfth via-hole onto the base substrate.
Optionally, the second via-hole structure includes a twentieth via-hole, and the second power source line is coupled to the first power source line through the twentieth via-hole. The first power source line includes a fourth connection member, and for the sub-pixels in the same row, the fourth connection member is located on a side of the first power source line close to the fourth scanning line. An orthographic projection of the twentieth via-hole onto the base substrate partially overlaps an orthographic projection of the fourth connection member onto the base substrate.
Optionally, a width of the twentieth via-hole along the first direction is less than a width of the twentieth via-hole along the second direction.
Optionally, the display substrate includes a light-emitting element layer on a side of the fourth conductive layer away from the base substrate, the light-emitting element layer includes a first electrode layer, a pixel definition layer, a light-emitting functional layer and a second electrode layer, and the first electrode layer includes a plurality of first electrodes corresponding to the plurality of sub-pixels respectively.
Optionally, the display substrate further includes a second organic layer arranged on a side of the fourth conductive layer away from the base substrate, the second organic layer includes a fourth via-hole structure, the fourth via-hole structure includes a twenty-first via-hole, and the plurality of first electrodes are coupled to the seventh connection member through the twenty-first via-hole, to enable the second electrode plate of the storage capacitor to be coupled to a second electrode of the driving transistor.
Optionally, the fourth conductive layer further includes an auxiliary electrode, the auxiliary electrode includes an eighth connection member, and the eighth connection member is located on a left side of the auxiliary electrode from a top view of the display substrate.
Optionally, the pixel definition layer includes a first pixel definition layer and a second pixel definition layer, the first pixel definition layer is arranged in the first direction and extends along the second direction, the first pixel definition layer and the second pixel definition layer define an opening region of each sub-pixel, and a light-emitting region of each sub-pixel is located in the opening region. A height of the second pixel definition layer is greater than a height of the first pixel definition layer in the direction perpendicular to the base substrate.
Optionally, the plurality of sub-pixels are divided into a plurality of repeat units arranged in an array form, each repeat unit includes two sub-units arranged along the first direction, and each sub-unit includes a plurality of sub-pixels arranged along the first direction. Within the repeat unit, pixel definition structures of adjacent sub-pixels in two adjacent sub-units are an integral structure.
Optionally, within the plurality of repeat units, the first pixel definition layer includes a first pattern, and the second pixel definition layer includes a second pattern, and an orthographic projection of the second pattern onto the base substrate covers an orthographic projection of the first pattern onto the base substrate.
Optionally, the fourth via-hole structure includes a twenty-second via-hole, the second pattern includes a twenty-third via-hole, and the second electrode layer is coupled to the auxiliary electrode through the twenty-third via-hole and the twenty-second via-hole. An orthographic projection of the twenty-third via-hole onto the base substrate covers an orthographic projection of the twenty-second via-hole onto the base substrate.
Optionally, the first electrode layer includes a ninth connection member, and an orthographic projection of the eighth connection member onto the base substrate is within an orthographic projection of the ninth connection member onto the base substrate. An orthographic projection of the eighth connection member onto the base substrate covers the twenty-second via-hole.
Optionally, the twenty-third via-hole is located at a center of the second pattern.
Based on the above-mentioned technical solution of the display substrate, the present disclosure, in another aspect, provides a display device including the above-mentioned display substrate.
The following drawings are provided to facilitate the understanding of the present disclosure, and constitute a portion of the present disclosure. These drawings and the following embodiments are for illustrative purposes only, but shall not be construed as limiting the present disclosure. In the drawings:
In order to further explain the display substrate and the display device in the embodiments of the present disclosure, a detailed description will be given below with reference to the accompanying drawings.
In order that the objects, technical solutions and advantages of the embodiments of the present disclosure become more apparent, the present disclosure is described in a clear and complete manner in conjunction with the drawings and embodiments. The following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.
Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as “first”, “second”, “third” and “fourth” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance.
In the present disclosure, such words as “center”, “on/above”, “under/below”, “left”, “inner” may be used to indicate directions or positions of components as viewed in the drawings, and they are merely used to facilitate the description in the present disclosure, rather than to indicate or imply that a device or member must be arranged or operated at a specific position. A positional relationship of the components is appropriately changed according to a direction in which each component is described. Therefore, the words described in the specification are not limited and may be replaced as appropriate according to circumstances.
In the present disclosure, unless explicitly specified or defined otherwise, terms such as “connected”, “connection” and “coupled” should be to be construed in a broad sense. For example, the term “connected” or “coupled” are used when describing some embodiments, it may be a fixed connection, or a detachable connection, or integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, or an indirect connection via an intermediate medium, or an interior connection of two elements. Such words as “include” or “including” intends to indicate that an element or object before the word contains an element or object or equivalents thereof listed after the word, without excluding any other element or object. The meanings of these words may be understood by a person skilled in the art according to the practical need.
In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region or drain electrode) and a source electrode (source electrode terminal, source region or source electrode), and a current is capable of flowing through the drain electrode, the channel region and the source electrode. Note that, in the specification, the channel region refers to a region through which the current mainly flows.
In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. The functions of the “source electrode” and the “drain electrode” are sometimes interchanged in the case of transistors with opposite polarities or in the case of a change in a direction of current during operation of a circuit, etc. Thus, in the present specification, “source electrode” and “drain electrode” may be interchanged.
In the present disclosure, “electrically connected” includes a case where components are connected to each other through an element having some electrical effect. The “element having some electrical effect” is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the “element having some electrical effect” not only include electrodes and wiring, but also include switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, etc. A scale of the drawings in the present disclosure may be, but not limited to, taken as a reference in an actual process. For example, a width-to-length ratio of a channel, a thickness of each film layer and a spacing between film layers, and a width of a signal line and a spacing between signal lines may be adjusted according to actual needs. The quantity of pixels in the display substrate and the quantity of sub-pixels in each pixel is also not limited to the quantity shown in the drawings, and the drawings described in the present disclosure are only schematic.
In the present disclosure, “film” and “layer” are interchangeable. For example, sometimes a “conductive layer” may be exchanged for a “conductive film”. Also, sometimes, the “insulation film” may be replaced with an “insulation layer”. The expression “about” in the present disclosure refers to a value within a range that a limit thereof is not strictly defined and allows for process and measurement errors.
Some embodiments of the present disclosure provide a display device. It is noted that the display device includes any product or member having a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, and the display device further includes a flexible circuit board, a printed circuit board and a backplane, etc.
The display device may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, and a micro light-emitting diode (including miniLED or microLED) display panel, etc.
In an exemplary embodiment, the display substrate 10 may be of a rectangular, curved, or another irregular shape. For example, as shown in
The display device 01 may further include other components such as a display driver integrated circuit (DDIC) 20 and the like. The DDIC 20 is coupled to, e.g., may be bonded to, the display substrate 10 and is configured to apply a data signal to the display substrate 10.
In an exemplary embodiment, the display substrate 10 includes a plurality of pixel units P arranged in an array form, and at least one pixel unit P includes a plurality of sub-pixels. The plurality of sub-pixels may include a first sub-pixel SP1 for emitting light in a first color, a second sub-pixel SP2 for emitting light in a second color, a third sub-pixel SP3 for emitting light in a third color, and a fourth sub-pixel SP4 for emitting light in a fourth color. Illustratively, the first sub-pixel SP1 may be a red sub-pixel (R) that emits a red light, the second sub-pixel SP2 may be a blue sub-pixel (B) that emits a blue light, the third sub-pixel SP3 may be a green sub-pixel (G) that emits a green light, and the fourth sub-pixel SP4 may be a white sub-pixel (W) that emits a white light. In an exemplary embodiment, each pixel unit P may include three sub-pixels (e.g., including RGB) or four sub-pixels (e.g., RGBW), which will not be particularly defined herein. A case where each pixel unit includes three sub-pixels (RGB) is taken as an example for illustration in the present disclosure.
In an exemplary embodiment, the pixel driving circuits of the plurality of sub-pixels may be arranged in M*N, where M and N are each a positive integer greater than or equal to 1. For example, pixel driving circuits in a row arranged in a first direction are referred to as pixel driving circuits in a same row, and pixel driving circuits in a column arranged in a second direction are referred to as pixel driving circuits in a same column. In the present disclosure, the first direction is an extension direction of the sub-pixels in one row and the second direction is an extension direction of the sub-pixels in one column. Illustratively, the present disclosure gives an array arrangement of sub-pixels in adjacent rows and columns, i.e., an (m−1)-th row and an m-th row, an (n−1)-th column and an n-th column, where m is a positive integer greater than 1 and less than or equal to M, and n is a positive integer greater than 1 and less than or equal to N.
The pixel driving circuit Q includes a plurality of transistors and a storage capacitor. A transistor may be a Thin Film Transistor (TFT), a metal oxide semiconductor (MOS) or another switching element with the same characteristics, and the thin film transistor is taken as an example for illustration in the present disclosure. In an exemplary embodiment, the pixel driving circuit may include a structure of 2T1C, 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, etc. where T represents a thin film transistor and C represents a storage capacitor.
In the pixel driving circuit of the embodiments of the present disclosure, each transistor may be, but not limited to, an N-type transistor. For example, one or more transistors in the pixel driving circuit may also be P-type transistors, and it is merely necessary to connect each electrode of the P-type transistor through referring to a connection of each electrode of a corresponding N-type transistor in the embodiment of the present disclosure, and apply a corresponding high level or low level to a corresponding gate electrode.
In an exemplary embodiment, the display substrate includes a plurality of signal lines and a plurality of scanning lines coupled to the plurality of pixel driving circuits. Illustratively, the plurality of signal lines includes one or more first signal lines D, a power source line VDD. For example, pixel driving circuits of sub-pixels in an n-th column (representing any one column) are coupled to the first signal line D (n) and the power source line VDD, the first signal line D (n) is configured to apply a data signal to the pixel driving circuits of sub-pixels in the n-th column, and the power source line VDD is configured to apply a power voltage signal to the pixel driving circuits.
In the exemplary embodiment, the plurality of scanning lines includes a first scanning line G1 and a second scanning line G2. For example, pixel driving circuits in a (m−1)-th row are coupled to the first scanning line G1<m−1>, the first scanning line G1<m−1> is configured to apply the first scanning signal to the pixel driving circuits in the (m−1)-th row, to control the data signal to be written into the pixel driving circuit. The pixel driving circuit is configured to receive the data signal transmitted from the first signal line D and output a corresponding current to the light-emitting element under the control of the first scanning line G1. The number of rows corresponding to each scanning line is represented in parentheses in
In an exemplary embodiment, the display substrate 10 further includes a plurality of signal lines and a plurality of scanning lines coupled to the pixel driving circuit, the plurality of signal lines includes a first signal line D and a second signal line Vref. The plurality of scanning lines includes a first scanning line G1 and a second scanning line G2, both the first scanning line G1 and the second scanning line G2 extend in a first direction and are arranged sequentially in a second direction crossing the first direction, the first direction is an extension direction of sub-pixels in a row, and the second direction is an extension direction of sub-pixels in a column.
A gate electrode of the first transistor T1 is coupled to the first scanning line G1, a first electrode of the first transistor T1 is coupled to the first signal line D, and a second electrode of the first transistor T1 is coupled to the first node N1. When an on-level scanning signal is applied to the first scanning line G1, the first transistor T1 is configured to input a data voltage signal from the first signal line D to the first node N1 under control of a signal from the first scanning line G1.
A gate electrode of the second transistor T2 is coupled to the second scanning line G2, a first electrode of the second transistor T2 is coupled to the second signal line Vref, and a second electrode of the second transistor T2 is coupled to the first node N1. When an on-level scanning signal is applied to the second scanning line G2, the second transistor T2 is configured to input a reference voltage signal from the second signal line Vref to the first node N1 under the control of the second scanning line G2.
In the pixel driving circuit according to an embodiment of the present disclosure, the plurality of transistors further includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a driving transistor DT. The plurality of scanning lines further includes a third scanning line G3, a light-emitting scanning line EM and a fourth scanning line G4. The plurality of signal lines further includes a power source line VDD and a third signal line Vinit.
A gate electrode of the third transistor T3 is coupled to the third scanning line G3, a first electrode of the third transistor T3 is coupled to the first node N1, and a second electrode of the third transistor T3 is coupled to a second node N2. When an on-level scanning signal is applied to the third scanning line G3, the third transistor T3 is configured to input the voltage of the first node N1 to the second node N2 under the control of the third scanning line G3.
A gate electrode of the fourth transistor T4 is coupled to the light-emitting scanning line EM, a first electrode of the fourth transistor T4 is coupled to the power source line VDD, and a second electrode of the fourth transistor T4 is coupled to a first electrode of the driving transistor DT. When an on-level signal is applied to the light-emitting scanning line EM, the fourth transistor T4 is configured to input a voltage signal from the power source line to the first electrode of the driving transistor DT under the control of the light-emitting scanning line EM.
A gate electrode of the driving transistor DT is coupled to the second node N2, i.e., coupled to the second electrode of the third transistor T3, the first electrode of the driving transistor DT is coupled to the second electrode of the fourth transistor T4, and a second electrode of the driving transistor DT is coupled to a first electrode of the light-emitting element. The driving transistor DT determines a driving current value according to a potential difference between a gate electrode and a first electrode thereof, and applies the generated driving current to the light-emitting element, to drive the light-emitting element to emit light.
A gate electrode of the fifth transistor T5 is coupled to the fourth scanning line G4, a first electrode of the fifth transistor T5 is coupled to the first electrode of the light-emitting element, and a second electrode of the fifth transistor T5 is coupled to the third signal line Vinit. When an on-level signal is applied to the fourth scanning line G4, the fifth transistor T5 is configured to transmit a voltage signal from the third signal line Vinit to the first electrode of the light-emitting element, so as to reset the first electrode of the light-emitting element.
The storage capacitor C has a first electrode plate C1 and a second electrode plate C2, the first electrode plate is coupled to the second node N2, namely, the first electrode plate C1 of the storage capacitor C is connected to the gate electrode of the driving transistor T3, and the second electrode plate C2 is coupled to the first electrode of the light-emitting element.
In an exemplary embodiment, the transistors in the pixel driving circuit may be low-temperature polysilicon thin film transistors, or oxide thin film transistors, or low-temperature polysilicon thin film transistors and oxide thin film transistors. An active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and an active layer of the oxide thin film transistor is made of oxide semiconductor. The low-temperature polysilicon thin film transistor has such advantages as high mobility and fast charging, and the oxide thin film transistor has such advantages as low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on one display substrate to form a display substrate containing both the low-temperature polysilicon thin film transistor and the oxide transistor (Low Temperature Poly-Silicon+Oxide, referred to as LTPO), thereby, through the advantages of the two, to realize the low-frequency driving, reduce the power consumption, and improve the display quality.
In an exemplary embodiment, a gate electrode of at least one thin film transistor is of a double-gate electrode structure, so as to avoid current leakage of the transistor in a better manner. As shown in
As shown in
In an exemplary embodiment, both the power source line VDD and the third signal line Vinit may be designed as of a grid-like shape. The power source line VDD includes a first power source line VDD-1 extending in the first direction and a second power source line VDD-2 extending in the second direction, the first power source line VDD-1 is coupled to the second power source line VDD-2, and the first power source line VDD-1 is located on a side of the light-emitting scanning line EM away from the first scanning line G1. The fourth scanning line G4 extends in the first direction and is located on a side of the first power source line VDD-1 away from the light-emitting scanning line EM. The third signal line Vinit includes a first sub-line Vinit-1 extending in the first direction and a second sub-line Vinit-2 extending in the second direction, and the first sub-line Vinit-1 is located at a side of the fourth scanning line G4 away from the first scanning line G1. Through a grid-like arrangement structure, it is able to significantly reduce the voltage drop of signal transmission and improve image uniformity.
In an exemplary embodiment, in the second direction, a first branch scanning line G3-1 is located on a side of the first scanning line G1 away from the second scanning line G2, and the light-emitting scanning line EM is located on a side of the first branch scanning line G3-1 away from the first scanning line G1.
In an exemplary embodiment, as shown in
According to the above-mentioned specific structure of the display substrate, it is derived that the display substrate in the embodiments of the present disclosure includes a plurality of control regions, and each third scanning line G3 can control whether all third transistors T3 in the corresponding control region are turned on, so as to control whether to realize a high refresh rate in the region.
In an exemplary embodiment, the third scanning lines G3 in a same control region are coupled to a control bus G30 to form an integral structure.
In an exemplary embodiment, the display substrate further includes a driving chip, the control bus G30 is located on a same side of the display substrate as the driving chip, the control bus is coupled to the driving chip, receives a control signal applied by the driving chip, and transmits the received control signal to the third scanning line G3 coupled thereto, thereby controlling whether the third transistors T3 in the corresponding control region are turned on.
In an exemplary embodiment, first branch scanning lines G3-1 are arranged in the second direction, and extend in the first direction. Second branch scanning lines G3-2 are arranged in the first direction and extend in the second direction. The second branch scanning line G3-2 is coupled to a plurality of first branch scanning lines G3-1. The second branch scanning lines G3-2 are coupled to the control bus G30. The first branch scanning line G3-1 is coupled to a gate electrode of each written-in control transistor T3 in a corresponding repeat unit.
In an exemplary embodiment, as shown in
In a displaying time period of an Nth frame, control signals transmitted by a first one G3<1> of third scanning lines and a H-th one G3<H> of third scanning lines are each an active level VGH, all third transistors T3 included in a first control region corresponding to the first one G3<1> of the third scanning lines are turned on, and all third transistors T3 included in a H-th control region corresponding to the H-th one G3<H> of the third scanning lines are turned on, so it is able to ensure that the first control region and the H-th control region are each a region capable of realizing normal refresh, thereby to realize a high refresh operation for the first control region and the H-th control region when scanning the display substrate row by row. A control signal transmitted by an I-th third scanning line G3<I> is an inactive level VGL, all third transistors T3 included in an I-th control region corresponding to a corresponding I-th one G3<I> of the third scanning lines are turned off. When scanning the display substrate row by row, a high refresh operation is not realized in the I-th control region, so that the I-th control region is not refreshed within an N-th frame, and a display image thereof is not updated within the N-th frame, thereby to achieve the effect of high refresh operations performed in a region-division manner through applying saved data amount to high refresh regions. H and I are each a positive integer greater than 1 and less than or equal to X.
In a blanking time period, region division is performed for a (N+1)-th frame by controlling the control signal transmitted from the third scanning line G3. The blanking time period is located at the beginning or the end of each frame displaying time period.
In a displaying time period of a (N+1)-th frame, the control signals transmitted by the first one G3<1> of the third scanning line and the I-th one G3<I> of the third scanning lines are each an active level VGH, all the written-in control transistors T3 included in the first control region corresponding to the first one G3<1> of the third scanning lines are turned on, and all the written-in control transistors T3 included in the I-th control region corresponding to the I-th one G3<I> of the third scanning lines are turned on. In this way, it is able to ensure that the first control region and the I-th control region are each a region capable of realizing normal refresh, thereby to realize a high refresh operation for the first control region and the I-th control region when scanning the display substrate row by row. The control signal transmitted by the H-th one G3<H> of the third scanning lines is an inactive level VGL, all the written-in control transistors T3 included in the H-th control region corresponding to the H-th one G3<H> of the third scanning lines are turned off. When scanning the display substrate row by row, realize a high refresh operation is not realized in the H-th control region, so that the H-th control region is not refreshed within an H-th frame, and a display image thereof is not updated within the H-th frame, thereby to achieve the effect of high refresh operations performed in a region-division manner through applying saved data amount to high refresh regions.
In an exemplary embodiment, considering that the load of the third scanning line G3 is relatively large, the control signal transmitted by the third scanning line G3 may be adjusted immediately in response to entering the blanking time period at the end of the N-th frame.
In the display substrate of the embodiments of the present disclosure, by arranging the control region and the third scanning line G3, the display substrate can well realize the high refresh rate function of the display substrate.
In the display substrate of the above-mentioned embodiments, through the first branch scanning lines G3-1 and the second branch scanning lines G3-2, it is able to not only achieve the transmission of the control signal in a better manner, but also reduce the difficulty in the layout of the third scanning line, and ensure the reliability that the third scanning line is coupled to the gate electrode of the third transistor T3.
In an exemplary embodiment, in the same control region, the first branch scanning lines in the same row along the first direction are connected to each other in an end-to-end manner. Illustratively, in the same control region, the first branch scanning lines in the same row in the first direction are formed as an integral structure.
In an exemplary embodiment, adjacent first branch scanning lines in the first direction in adjacent control regions respectively are disconnected from each other.
In the display substrate of the above-mentioned embodiments, when the adjacent first branch scanning lines in the first direction in the same control region are coupled to each other, so that in the same control region, the third scanning lines form a grid-like structure, so as to reduce the overall load of the third scanning line G3 and reduce the voltage drop of the third scanning line G3.
In an exemplary embodiment, in the same control region, the adjacent first branch scanning lines in the first direction may also be arranged independently of each other.
In an exemplary embodiment, the power source line VDD includes a first power source line VDD-1 extending in the first direction and a second power source line VDD-2 extending in the second direction, the first power source line VDD-1 is coupled to the second power source line VDD-2. In the first direction, the second power source line VDD-2 is arranged alternately with the repeat unit, and an orthographic projection of the first branch scanning line G3-1 onto the base substrate does not overlap an orthographic projection of the second power source line VDD-2 onto the base substrate.
In an exemplary embodiment, as shown in
Please continue to refer to
In an exemplary embodiment, the active layer may be formed by one or more of amorphous silicon, polysilicon, oxide semiconductor materials.
In an exemplary embodiment, the first electrode plate of the storage capacitor includes a first electrode sub-plate C1 and a second electrode sub-plate C12, and the first electrode sub-plate is located at the first conductive layer.
In an exemplary embodiment, referring to
As shown in
In an exemplary embodiment, the third conductive layer includes a second connection member K2, and the second connection member K2 and the second sub-electrode plate form an integral structure. The third conductive layer further includes a third connection member K3, which is located at a left side of the second connection member as viewed from the top of the display substrate within sub-pixels in a same row.
In an exemplary embodiment, the first power source line VDD-1 includes a fourth connection member K4 which is located on a side of the first power source line VDD-1 close to the fourth scanning line G4 within the sub-pixels in the same row.
In an exemplary embodiment, the third conductive layer includes a fifth connection member K5 and a sixth connection member K6, and within the sub-pixels in the same row, the second connection member K2, the third connection member K3, the fifth connection member K5 and the sixth connection member K6 are all located between the first branch scanning line G3-1 and the light-emitting scanning line EM.
In an exemplary embodiment of the present disclosure, respective connection members, including the first connection member K1, the second connection member K2, the third connection member K3, the fourth connection member K4, the fifth connection member K5, and the sixth connection member K6, are used for electrical connection of respective conductive layer structures.
Referring to
In an exemplary embodiment, an orthographic projection of the gate electrode T1g of the first transistor T1 onto the base substrate at least partially overlaps an orthographic projection of the first scanning line G1 onto the base substrate at a first overlapping region A1, and an orthographic projection of the first via-hole V1 onto the base substrate is located in the first overlap region A1. An orthographic projection of the gate electrode T2g of the second transistor onto the base substrate at least partially overlaps an orthographic projection of the second scanning line G2 onto the base substrate at a second overlapping region A2, and an orthographic projection of the second via-hole V2 onto the base substrate is located in the second overlap region A2. A distance between the first via-hole V1 and the second via-hole V2 is greater than a distance between the first scanning line G1 and the second scanning line G2. Within the sub-pixels in same row, the fifth channel region T5p is located on a side of the fourth scanning line G4 close to the second scanning line G2. The channel region of the driving transistor may be of a U-like type, including an opening structure T which, within sub-pixels in an n-th column, faces sub-pixels in a (n−1)-th column.
With continuing reference to
In an exemplary embodiment, the third connection member K3 is coupled to the first electrode T11 of the first transistor T1 through the first via-hole structure, e.g., a twelfth via-hole V12. The fifth connection member K5 is coupled to the second electrode plate C2 of the storage capacitor through the first via-hole structure, e.g., a tenth via-hole V10, and coupled to the second electrode of the driving transistor through an eleventh via-hole V11. Illustratively, the tenth via-hole V10 and the eleventh via-hole V1 are arranged in the first direction and do not overlap each other in a direction perpendicular to the base substrate.
The sixth connection member K6 is coupled to the second electrode plate C2 of the storage capacitor through the first via-hole structure, e.g., a thirteenth via-hole V13, and coupled to the first electrode of the fifth transistor through the fourteenth via-hole V14. The second electrode sub-plate C12 is coupled to the first electrode sub-plate C11 of the storage capacitor and the second node N2 through the first via-hole structure, e.g., a fifteenth via-hole V15 and a sixteenth via-hole V16, respectively. Within the sub-pixels in the same column, the fifteenth via-hole V1 and the sixteenth via-hole V16 are arranged along the second direction, and the thirteenth via-hole V13 and the fourteenth via-hole V14 are arranged in the second direction. Illustratively, an orthographic projection of the sixth connection member K6 onto the base substrate covers orthographic projections of the thirteenth via-hole V13 and the fourteenth via-hole V14 onto the base substrate.
The first sub-line Vinit-1 is coupled to the second sub-line Vinit-2 through the first via-hole structure, e.g., a seventeenth via-hole V17.
In the display substrate of the embodiments of the present disclosure, it is able to improve electrical connection performance and reduce connection resistance through multiple via-holes. A person skilled in the art would have been able to select the quantity of via-holes used when connecting different conductive layers according to actual needs.
As shown in
In an exemplary embodiment, as shown in
In an exemplary embodiment, the fourth conductive layer 11 further includes an auxiliary electrode Aux, the auxiliary electrode Aux includes an eighth connection member K8 located on a left side of the auxiliary electrode line Aux as viewed from the top. In the first direction, the auxiliary electrode Aux is disposed adjacent to the second branch scanning line G3-2 as viewed from the top.
In an exemplary embodiment, an orthographic projection of the auxiliary electrode Aux onto the base substrate overlaps the orthographic projection of the first branch scanning line G3-1 onto the base substrate. The seventh connection member K7 is coupled to the seventh connection member K5 through the second via-hole structure, e.g., a nineteenth via-hole V19, so that the seventh connection member K7 is coupled to the second electrode plate C2 of the storage capacitor and the second electrode of the driving transistor. An orthographic projection of the seventh connection member K7 onto the base substrate covers an orthographic projection of the nineteenth via-hole V19 onto the base substrate. Illustratively, from a top view, within the sub-pixels in the same row, the nineteenth via-hole V19 is located on a side of the tenth via-hole V10 close to the first scanning line G1.
In an exemplary embodiment, an orthographic projection of the fifth connection member K5 onto the base substrate overlaps the orthographic projection of the seventh connection member K7 onto the base substrate. The fifth connection member covers orthographic projections of the tenth, eleventh, and nineteenth via-holes onto the base substrate.
In an exemplary embodiment, the second power source line VDD-2 is connected to the first power source line VDD-1 through the second via-hole structure, e.g., a twentieth via-hole V20. An orthographic projection of the twentieth via-hole V20 onto the base substrate partially overlaps an orthographic projection of the fourth connection member K4 onto the base substrate. Illustratively, a width of the twentieth via-hole V20 in the first direction is less than a width of the twentieth via-hole in the second direction.
In an exemplary embodiment, a second organic layer 114 is provided on a side of the fourth conductive layer 112 away from the base substrate, a fourth via-hole structure V400 is formed penetrating the second organic layer 114, and through the fourth via-hole structure V400, structures above and below the second organic layer 114 are connected to each other. The fourth via-hole structure V400 includes a plurality of via-holes.
In an exemplary embodiment, a second passivation layer 113 may be further provided between the second organic layer 114 and the fourth conductive layer 112, and the second passivation layer 113 includes a fifth via-hole structure V500 including a plurality of via-holes.
The display substrate in the embodiments of the present disclosure includes the first passivation layer and the second passivation layer, and in other embodiments, the display substrate may not include a passivation layer or include only one passivation layer. Illustratively, when the display substrate includes the first passivation layer 111, since there are the first organic layer and the first passivation layer between the third conductive layer 109 and the fourth conductive layer 112, the third conductive layer 109 is relatively far away from the fourth conductive layer 112, so it is able to effectively reduce the parasitic capacitance between a conductive line formed by the fourth conductive layer 112 and a conductive line formed by the third conductive layer 109, thereby satisfying the load requirements of medium-sized and large-sized display products and providing support for a high refresh rate. Same principle applies to the arrangement of the second passivation layer 113 and the second organic layer 114.
As shown in
In the exemplary embodiment, the nineteenth via-hole V19 and the twenty-first via-hole V21 are arranged along the first direction within the sub-pixels in same row.
In an exemplary embodiment, the light-emitting functional layer 116 may include a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL) laminated one on another. Illustratively, hole injection layers and electron injection layers of all sub-pixels may be connected together to form a common layer, hole transport layers and electron transport layers of all the sub-pixels may be connected together to form a common layer, hole-blocking layers of all the sub-pixels may be connected together to form a common layer, emitting layers and electron blocking layers of adjacent sub-pixels may have a small amount of overlapping, or may be separate from each other.
In an exemplary embodiment, referring to
During a manufacturing process, ink with a light emitting function is dropped into the opening region by using an ink jet printing process, to form an organic film layer of the light-emitting functional layer in the opening region. Since the height of the second pixel definition layer 119 is greater than the height of the first pixel definition layer 118, the ink may flow in opening regions in a column in the second direction during the ink jet printing process, thereby enhancing the fluidity of the ink, averaging the ink content in each opening region, and improving the film formation uniformity of the ink. Also, since the opening regions in the same column in the second direction communicate with each other, sub-pixel units in the same column having a same color may be formed by using the ink-jet printing process.
In an exemplary embodiment, the plurality of sub-pixels is divided into a plurality of repeat units arranged in an array form, each repeat unit includes two sub-units arranged in the first direction, and each sub-unit includes a plurality of sub-pixels arranged in the first direction. For example, the repeat unit includes six sub-pixels arranged in the first direction, and the six sub-pixels include BRGBRG arranged in the first direction, where a group of BRG represents one sub-unit.
In an exemplary embodiment, within the plurality of repeat units, the first pixel-defining layer includes a first pattern H1, the second pixel-defining layer includes a second pattern H2, and an orthographic projection of the second pattern H2 onto the base substrate covers an orthographic projection of the first pattern H1 onto the base substrate.
Based on the above-mentioned arrangement, referring to
Based on the above-mentioned arrangement, referring to
In an exemplary embodiment, the second electrode layer may be connected to the ninth connection member K9 through the twenty-third via-hole V23, so as to realize that the second electrode layer is in contact with the auxiliary electrode Aux. An orthographic projection of the twenty-third via-hole V23 onto the base substrate covers the orthographic projection of the twenty-second via-hole V22 onto the base substrate as viewed from the top. The term “equal to” mentioned in the present disclosure allows for a range of errors, taking into account process error reasons.
An embodiment of the present disclosure further provides a display device including the above-mentioned display substrate. The display means may be any product or member having a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, and the display device further includes a flexible circuit board, a printed circuit board and a backplane, etc.
It should be appreciated that, the expression “at a same layer” refers to that the film layers are arranged on a same structural layer. Alternatively, for example, the film layers on a same layer may be layer structures formed through forming thin layers for forming specific patterns through a single film-forming process and then patterning the film layers with a same mask through a single patterning process. Depending on different specific patterns, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the layer structures may be continuous or discontinuous. These specific patterns may also be arranged at different levels or have different thicknesses.
It should be further appreciated that, the above embodiments have been described in a progressive manner, and the same or similar contents in the embodiments have not been repeated, i.e., each embodiment has merely focused on the difference from the others. Especially, the product embodiments are substantially similar to the method embodiments, and thus have been described in a simple manner.
Although the embodiments disclosed in the present disclosure are as above, the described contents thereof are only used to facilitate the understanding of the present disclosure and are not intended to limit the present invention. Any person skilled in the art can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of the present disclosure shall be subject to the scope defined by the appended claims.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2022/128272 | 10/28/2022 | WO |