Patent Application
20240298482
The present disclosure belongs to the technical field of display, and particularly relates to a display substrate and an electronic apparatus.
With the advancement of technology, a special-shaped screen and a full screen have gradually entered people's field of vision in recent years. Both the special-shaped screen and the full screen are designed to improve a screen proportion of the display device. Then, in order to achieve a higher screen proportion, it is necessary to reserve some opening regions (e.g., holes) for some additional components (e.g., a camera, a sensor, etc.) at some positions of the display screen.
With the development and updating of display technology, an organic electroluminescent display (OLED) device has become a mainstream product in the display field due to its characteristics of self-luminescence, high brightness, high contrast, low operating voltage, and capability of manufacturing a flexible display.
The present disclosure aims to solve at least one technical problem in the prior art and provides a display substrate and an electronic apparatus.
In a first aspect, an embodiment of the present disclosure provides a display substrate having a display region, where the display region includes a functional region and a main display region surrounding the functional region; the functional region has at least one functional unit; each of the at least one functional unit has a blank region, a winding region and a circuit region; the display substrate includes a base substrate, and a plurality of conductive layers on the base substrate; the plurality of conductive layers form at least one hollow pattern, and each of the at least one hollow pattern is in the blank region;
In the functional unit, the winding region surrounds the blank region, and the circuit region surrounds the winding region; and the first line segment, the second line segment and the third line segment of the first signal line are directly and electrically connected together.
The plurality of conductive layers include a first conductive layer and a second conductive layer on the base substrate;
The third line segment includes a first line sub-segment extending in the first direction and a second line sub-segment extending in the second direction.
The first line sub-segment and the second line sub-segment of the third line segment are directly electrically connected together.
The first conductive layer includes the first line sub-segment, the second conductive layer includes the second line sub-segment, and the first line sub-segment and the second line sub-segment of the third line segment are electrically connected together through a via penetrating through an interlayer insulating layer.
The first signal line is the second sub-type signal line, and the second sub-type signal line is arranged in mirror symmetry, taking a straight line passing through a center of the functional region and extending in the first direction as a symmetry axis; or the first signal line is the fourth sub-signal line, and the fourth sub-signal line is arranged in mirror symmetry, taking a straight line passing through the center of the functional region and extending in the second direction as a symmetry axis.
The first type signal lines include at least one of a gate line, a reset signal line, and a light emitting control line.
The second type signal lines include at least one of a data line, an initial signal line, and a power supply signal line.
A spacing between the third signal lines is less than a spacing between the first signal line segments.
The display substrate further includes pixel driving circuits in the main display region and the circuit region, where a distribution density of the pixel driving circuits in the main display region is the same as a distribution density of the pixel driving circuits in the circuit region.
The display substrate further includes light emitting devices in the main display region and the functional region, where the light emitting devices each include an anode on the base substrate; for the light emitting devices of a same emission color, an area of the anode of the light emitting device in the main display region is less than an area of the anode of the light emitting device in the functional region.
A part of the anodes of the light emitting devices partially cover the blank region.
In a second aspect, an embodiment of the present disclosure provides an electronic apparatus, including a display substrate and a functional component, where the functional component is on a side of the display substrate away from a light emitting surface; the display substrate has a display region, and the display region includes a functional region and a main display region surrounding the functional region; the functional region has at least one functional unit; each of the at least one functional unit has a blank region, a winding region and a circuit region; the display substrate includes a base substrate, and a plurality of conductive layers on the base substrate; the plurality of conductive layers form at least one hollow pattern, and each of the at least one hollow pattern is in the blank region;
In the functional unit, the winding region surrounds the blank region, and the circuit region surrounds the winding region; and the first line segment, the second line segment and the third line segment of the first signal line are directly and electrically connected together.
The plurality of conductive layers include a first conductive layer and a second conductive layer on the base substrate;
The third line segment includes a first line sub-segment extending in the first direction and a second line sub-segment extending in the second direction.
The first line sub-segment and the second line sub-segment of the third line segment are directly electrically connected together.
The first conductive layer includes the first line sub-segment, the second conductive layer includes the second line sub-segment, and the first line sub-segment and the second line sub-segment of the third line segment are electrically connected together through a via penetrating through an interlayer insulating layer.
The first signal line is the second sub-type signal line, and the second sub-type signal line is arranged in mirror symmetry, taking a straight line passing through a center of the functional region and extending in the first direction as a symmetry axis; or
The first signal line includes at least one of a gate line, a reset signal line, and a light emitting control line.
The second type signal line includes at least one of a data line, an initial signal line and a power supply signal line.
A spacing between the third signal lines is less than a spacing between the first signal line segments.
The display substrate further includes pixel driving circuits in the main display region and the circuit region, where a distribution density of the pixel driving circuits in the main display region is the same as a distribution density of the pixel driving circuits in the circuit region.
The display substrate further includes light emitting devices in the main display region and the functional region, where a distribution density of the light emitting devices in the main display region is greater than a distribution density of the light emitting devices in the functional region.
The display substrate further includes light emitting devices in the main display region and the functional region, where the light emitting devices each include an anode on the base substrate; for the light emitting devices of a same emission color, an area of the anode of the light emitting device in the main display region is less than an area of the anode of the light emitting device in the functional region.
A part of the anodes of the light emitting devices partially cover the blank region; and orthographic projections of the functional component and the anode on the base substrate do not overlap each other.
In order to enable one of ordinary skill in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of “first”, “second”, and the like in the present disclosure is not intended to indicate any order, quantity, or importance, but rather serves to distinguish one element from another. Also, the term “a”, “an”, “the” or the like does not denote a limitation of quantity, but rather denotes the presence of at least one. The word “comprising”, “comprises”, or the like means that the element or item preceding the word includes the element or item listed after the word and its equivalent, but does not exclude other elements or items. The term “connected”, “coupled” or the like is not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right”, and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
With the development of display technology, users have more and more functional requirements on a display panel, such as integrating a series of functional elements in a display region of the display panel, that is, presetting a functional region in the original display panel, so as to form the functional elements later, as shown in
However, in order to ensure that the display uniformity of the display panel is not affected with the functional elements in the display region, display elements, such as pixel driving circuits, light emitting devices, or the like, are still arranged in the functional region. It should be understood, however, that the display elements arranged in the functional region should not affect an operation of the functional elements. That is, the spacing between the pixel driving circuits, the light emitting devices, or the like, in the functional region will define a blank region where the functional elements are located. Due to the arrangement of the blank region in the functional region, the pixel driving circuit and the light emitting device cannot be arranged at this position, so that signal lines on two opposite sides of the blank region cannot pass through the blank region to be connected, and the display elements in the functional region cannot work normally.
In view of the above problem, a structure of a display substrate is provided in an embodiment of the present disclosure. In order to make the structure of the display substrate clearer, a pixel driving circuit and a light emitting device adopted in the display substrate, and a relationship between film layers of the pixel driving circuit and the light emitting device are first described.
In some examples, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may each be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon. In an exemplary embodiment, the four sub-pixels may be arranged in a square format to form a GGRB pixel arrangement, as shown in
In some examples, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as a pixel row, a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as a pixel column, and a plurality of pixel rows and a plurality of pixel columns constitute a pixel array arranged in an array.
In an exemplary embodiment, the base substrate 101 may be a flexible substrate, or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit. The pixel driving circuit may include a plurality of transistors and a storage capacitor, which are illustrated in
In an exemplary embodiment, the organic light emitting layer 303 may include a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emission layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL), which are stacked together. In an exemplary embodiment, the hole injection layers and the electron injection layers of all the sub-pixels may each be an inter-connected common layer, the hole transport layers and the electron transport layers of all the sub-pixels may each be an inter-connected common layer, the hole blocking layers of all the sub-pixels may be an inter-connected common layer, and the emission layers of two adjacent sub-pixels may overlap slightly, or may be isolated from each other, and the electron blocking layers of two adjacent sub-pixels may overlap slightly, or may be isolated from each other.
In some examples, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to a first electrode of the third transistor T3, a second electrode of the fourth transistor T4 and a second electrode of the fifth transistor T5. The second node N2 is connected to a second electrode of the first transistor T1, a first electrode of the second transistor T2, a control electrode of the third transistor T3 and a second terminal of the storage capacitor C. The third node N3 is connected to a second electrode of the second transistor T2, a second electrode of the third transistor T3 and a first electrode of the sixth transistor T6.
In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first power supply line VDD, and the second terminal of the storage capacitor C is connected to the second node N2, that is, the second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.
A control electrode of the first transistor T1 is connected to the second scanning signal line S2, a first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the second node N2. When a scanning signal of a turn-on level is applied to the second scanning signal line S2, the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize charges at the control electrode of the third transistor T3.
A control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a scanning signal of a turn-on level is applied to the first scanning signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines a magnitude of a driving current flowing between the first power supply line VDD and a second power supply line VSS according to a potential difference between the control electrode and the first electrode of third transistor T3.
A control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may be referred to as a switch transistor, a scanning transistor, or the like. When a scanning signal of a turn-on level is applied to the first scanning signal line S1, the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit.
A control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to a first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When a light emitting signal of a turn-on level is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
A control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When a scanning signal of a turn-on level is applied to the second scanning signal line S2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light emitting device to initialize or release the accumulated charges at the first electrode of the light emitting device.
In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked together, or may be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked together.
In an exemplary embodiment, a second electrode of the light emitting device is connected to the second power supply line VSS. The signal of the second power supply line VSS is a low level signal, and the signal of the first power supply line VDD is a high level signal. The first scanning signal line S1 is a scanning signal line of the pixel driving circuits in the present display row, and the second scanning signal line S2 is a scanning signal line of the pixel driving circuits in the previous display row. That is, for an nth display row, the first scanning signal line S1 is S(n), the second scanning signal line S2 is S(n−1). The second scanning signal line S2 in the present display row and the first scanning signal line S1 of the pixel driving circuits in the previous display row are the same signal line, which can reduce the number of the signal lines of the display panel and realize the narrow bezel of the display panel.
In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty for manufacturing the display panel can be reduced, and the yield of product can be improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
In exemplary embodiments, the first to seventh transistors T1 to T7 each may adopt a low temperature poly-silicon thin film transistor, or may adopt an oxide thin film transistor, or the first to seventh transistors T1 to T7 may adopt both a low temperature poly-silicon thin film transistor and an oxide thin film transistor. An active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility, high charging speed and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. The low temperature poly-silicon thin film transistor and the oxide thin film transistor may be integrated in one display substrate to form a low temperature polycrystalline oxide (LTPO) display substrate, the advantages of both the low temperature poly-silicon thin film transistor and the oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.
An exemplary description will be given below through a manufacturing process of a display substrate. The term “patterning process” in the present disclosure, for a metal material, an inorganic material, or a transparent conductive material, includes processes of coating a photoresist, exposing with a mask plate, developing, etching, and stripping the photoresist, and for an organic material, includes processes of coating the organic material, exposing with a mask plate, and developing the organic material. A deposition process may adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating process may adopt any one or more of spray coating, spin coating, and inkjet printing, and the etching process may adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The term “film” is referred to as a layer of a material deposited, coated, or otherwise formed on a base substrate. A “film” may alternatively be referred to as a “layer” if it does not require a patterning process throughout the manufacturing procedure. If a “film” requires a patterning process during the entire manufacturing procedure, the “film” is referred to as a “film” before the patterning process, and referred to as a “layer” after the patterning process. The “layer” after the patterning process includes at least one “pattern”. The term “A and B are in a same layer” in the present disclosure means that A and B are formed simultaneously by a same patterning process, and a “thickness” of the film or layer is a dimension of the film or layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, the term “an orthographic projection of B is within an orthographic projection of A” or the term “an orthographic projection of A includes an orthographic projection of B” means that a boundary of the orthographic projection of B falls within a boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
In some examples, taking eight pixel driving circuits (in two unit rows and four unit columns) as an example, the manufacturing procedure of the driving circuit layer may include the following operations.
(1) Forming a pattern of a semiconductor layer. In some examples, the forming a pattern of a semiconductor layer may include: sequentially depositing a first insulating film and a semiconductor film on a base substrate, and patterning the semiconductor film through a patterning process, to form a first insulating layer covering the base substrate and a semiconductor layer arranged on the first insulating layer, as shown in
In some examples, the semiconductor layer of each pixel driving circuit may include a first active layer 11 of the first transistor T1, a second active layer 12 of the second transistor T2, a third active layer 13 of the third transistor T3, a fourth active layer 14 of the fourth transistor T4, a fifth active layer 15 of the fifth transistor T5, a sixth active layer 16 of the sixth transistor T6, and a seventh active layer 17 of the seventh transistor T7, which are of an inter-connected one-piece structure. In each unit column, the sixth active layer 16 of the pixel driving circuit in an Mth row and the seventh active layer 17 of the pixel driving circuit in an (M+1)th row are connected to each other. That is, the semiconductor layers of the adjacent pixel driving circuits in each unit column are of an inter-connected one-piece structure.
(2) Forming a pattern of a first conductive layer. In some examples, the forming a pattern of a first conductive layer may include: sequentially depositing a second insulating film and a first conductive film on the base substrate with the above described pattern formed thereon, and patterning the first conductive film through a patterning process, to form a second insulating layer covering the pattern of the semiconductor layer and the pattern of the first conductive layer arranged on the second insulating layer. The pattern of the first conductive layer includes, as shown in
In conjunction with
In some examples, the first plate 24 may have a rectangular shape, corners of the rectangular shape may be chamfered, and an overlapping region exists between an orthographic projection of the first plate 24 on the base substrate and an orthographic projection of the third active layer of the third transistor T3 on the base substrate. In an exemplary embodiment, the first plate 24 may serve as both one plate of the storage capacitor and the gate electrode of the third transistor T3.
In some examples, a region of the first scanning signal line 21 overlapping the second active layer 12 serves as a gate electrode of the second transistor T2. The first scanning signal line 21 is provided with a gate block 21-1 protruding toward the second scanning signal line 22, and an overlapping region exists between an orthographic projection of the gate block 21-1 on the base substrate and an orthographic projection of the second active layer 12 on the base substrate, thereby forming a double gate structure of the second transistor T2. A region of the first scanning signal line 21 overlapping the fourth active layer 14 serves as a gate electrode of the fourth transistor T4. A region of the second scanning signal line 22 overlapping the first active layer 11 serves as a gate electrode of the first transistor T1 with a dual gate structure. A region of the second scanning signal line 22 overlapping the seventh active layer 17 serves as a gate electrode of the seventh transistor T7. A region of the light emitting control line 23 overlapping the fifth active layer 15 serves as a gate electrode of the fifth transistor T5. A region of the light emitting control line 23 overlapping the sixth active layer 16 serves as a gate electrode of the sixth transistor T6.
In some examples, after the pattern of the first conductive layer is formed, a part of the semiconductor layer is treated to become a conductor with the first conductive layer as a mask. Channel regions of the first to seventh transistors T1 to T7 are formed by regions of the semiconductor layer masked by the first conductive layer, respectively, and regions of the semiconductor layer not masked by the first conductive layer each become a conductor. That is, both a first region and a second region of each of the first to seventh active layers each become a conductor.
(3) Forming a pattern of a fourth conductive layer. In an exemplary embodiment, the forming a pattern of the second conductive layer may include: sequentially depositing a third insulating film and a fourth conductive film on the base substrate with the above described patterns formed thereon, and patterning the fourth conductive film through a patterning process, to form a third insulating layer covering the first conductive layer and the pattern of the second conductive layer arranged on the third insulating layer. The pattern of the second conductive layer includes, as shown in
In conjunction with
In some examples, the second plate 32 may have a rectangular shape, corners of the rectangular shape may be chamfered. An overlapping region exists between an orthographic projection of the second plate 32 on the base substrate and an orthographic projection of the first plate 24 on the base substrate, and the first plate 24 and the second plate 32 form the storage capacitor of the pixel driving circuit. The second plate 32 has an opening 34, and the opening 34 may be located in the middle of the second plate 32. The opening 34 may be rectangular such that the second plate 32 forms a ring-shaped structure. The opening 34 exposes the third insulating layer covering the first plate 24, and the orthographic projection of the first plate 24 on the base substrate includes the orthographic projection of the opening 34 on the base substrate. In an exemplary embodiment, the opening 34 is configured to receive a subsequently formed first via, which is located within the opening 34 and exposes the first plate 24, to connect a subsequently formed second electrode of the first transistor T1 to the first plate 24.
In an exemplary embodiment, the plate connection line 35 is arranged between the second plates 32 of adjacent pixel driving circuits in the first direction X or in a direction opposite to the first direction X. A first end of the plate connection line 35 is connected to the second plate 32 of the pixel driving circuit, and a second end of the plate connection line 35 extends in the first direction X or in the direction opposite to the first direction X and is connected to the second plate 32 of the adjacent pixel driving circuit. That is, the plate connection line 35 is configured to connect the second plates of the adjacent pixel driving circuits in a unit row to each other. In an exemplary embodiment, the second plates of the plurality of pixel driving circuits in a unit row may form a inter-connected one-piece structure through the plate connection line 35, and the second plates of the one-piece structure may also serve as a power signal line, so as to ensure that the plurality of second plates in a unit row have a same potential, which is beneficial to improving the uniformity of the display panel, avoiding the display defects of the display substrate from occurring, and ensuring a good display effect of the display substrate.
(4) Forming a pattern of a fourth insulation layer. In an exemplary embodiment, the forming a pattern of a fourth insulation layer may include: depositing a fourth insulating film on the base substrate with the above described patterns formed thereon, and patterning the fourth insulating film through a patterning process, to form the fourth insulating layer covering the second conductive layer. Each pixel driving circuit is provided with a plurality of vias, and the plurality of vias include, as shown in
In conjunction with
In some examples, an orthographic projection of the second via V2 on the base substrate is within the orthographic projection of the second plate 32 on the base substrate. A part of the fourth insulating layer in the second via V2 is etched away, exposing a surface of the second plate 32. The second via V2 is configured to connect a subsequently formed first power supply line to the second plate 32 through this via. In some examples, a plurality of second vias V2 as power vias may be provided, and the plurality of second vias V2 may be sequentially arranged along a second direction Y, to increase the connection reliability between the first power supply line and the second plate 32.
In some examples, an orthographic projection of the third via V3 on the base substrate is within an orthographic projection of the fifth active layer on the base substrate, and parts of the fourth insulating layer, the third insulating layer and the second insulating layer in the third via V3 are etched away, exposing a surface of a first region of the fifth active layer. The third via V3 is configured to connect a subsequently formed first power supply line to the fifth active layer through this via.
In some examples, an orthographic projection of the fourth via V4 on the base substrate is within an orthographic projection of the sixth active layer on the base substrate, and parts of the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched away, exposing a surface of a second region of the sixth active layer (also a second region of the seventh active layer). The fourth via V4 is configured to connect a subsequently formed second electrode of the sixth transistor T6 to the sixth active layer through this via, and to connect a subsequently formed second electrode of the seventh transistor T7 to the seventh active layer through this via.
In some examples, an orthographic projection of the fifth via V5 on the base substrate is within an orthographic projection of the fourth active layer on the base substrate, and parts of the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via V5 are etched away, exposing a surface of a first region of the fourth active layer. The fifth via V5 is configured to connect a subsequently formed data signal line to the fourth active layer through this via, and the fifth via V5 is referred to as a data writing hole.
In some examples, an orthographic projection of the sixth via V6 on the base substrate is within an orthographic projection of the second active layer on the base substrate, and parts of the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are etched away, exposing a surface of a first region of the second active layer (also a second region of the first active layer). The sixth via V6 is configured to connect the subsequently formed second electrode of the first transistor T1 to the first active layer through this via, and to connect the subsequently formed first electrode of the second transistor T2 to the second active layer through this via.
In some examples, an orthographic projection of the seventh via V7 on the base substrate is within an orthographic projection of the seventh active layer on the base substrate, and parts of the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via V7 are etched away, exposing a surface of a first region of the seventh active layer (also a first region of the first active layer). The seventh via V7 is configured to connect a subsequently formed first electrode of the seventh transistor T7 to the seventh active layer through this via, and to connect the subsequently formed first electrode of the first transistor T1 to the first active layer through this via.
In some examples, an orthographic projection of the eighth via V8 on the base substrate is within an orthographic projection of the shielding electrode 33 on the base substrate, and a part of the fourth insulating layer in the eighth via V8 is etched away, exposing a surface of the shielding electrode 33. The eighth via V8 is configured to connect the subsequently formed first power supply line with the shield electrode 33 through this via.
In some examples, an orthographic projection of the ninth via V9 on the base substrate is within an orthographic projection of the first initial signal line 31 on the base substrate, and a part of the fourth insulating layer in the ninth via V9 is etched away, exposing a surface of the first initial signal line 31. The ninth via V9 is configured to connect a subsequently formed first electrode of the seventh transistor T7 (also a first electrode of the first transistor T1) to the first initial signal line 31 through this via.
(5) forming a pattern of a third conductive layer. In some examples, the forming a pattern of a third conductive layer may include: depositing a third conductive film on the base substrate with the above described patterns formed thereon, and patterning the third conductive film through a patterning process, to form a third conductive layer arranged on the fourth insulating layer. The third conductive layer includes, as shown in
In conjunction with
In some examples, an orthographic projection of the at least a part of the shielding electrode 33 on the base substrate may at least partially overlap an orthographic projection of the subsequently formed data signal line on the base substrate. In an exemplary embodiment, the shielding electrodes 33 in the pixel driving circuits adjacent to each other in the first direction X may be connected to each other to reduce resistance.
In some examples, the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via V5, and the data connection electrode 42 is configured to be connected to the subsequently formed data signal line.
In some examples, the first connection electrode 43 extends in the second direction Y, a first end of the first connection electrode 43 is connected to the second region of the first active layer (also the first region of the second active layer) through the sixth via V6, and a second end of the first connection electrode 43 is connected to the first plate 24 through the first via V1, so that the first plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 43 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
In some examples, a first end of the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via V9, and a second end of the second connection electrode 44 is connected to the first region of the seventh active layer (also the first region of the first active layer) through the seventh via V7, so that the first electrodes of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the first initial signal line 31.
In some examples, the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via V4, so that the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In some examples, the third connection electrode 45 is configured to be connected to a subsequently formed anode connection electrode.
(6) Forming a pattern of a first planarization layer. In an exemplary embodiment, the forming a pattern of a first planarization layer may include: coating a first planarization film on the base substrate with the above described patterns formed thereon, and patterning the first planarization film by a patterning process, to form the first planarization layer covering the third conductive layer. As shown in
In conjunction with
In some examples, the eleventh via V11 may be in a strip shape, and an extension length of the eleventh via V11 in the second direction Y is greater than an extension length thereof in the first direction X. According to the present disclosure, by providing the eleventh via V11 in the strip shape extending in the second direction Y, a width of the eleventh via V11 in the first direction X may be reduced, and an inclination degree of a subsequently formed anode may be reduced.
An orthographic projection of the twelfth via V12 on the base substrate is within an orthographic projection of the third connection electrode 45 on the base substrate, and a part of the first planarization layer in the twelfth via V12 is removed, exposing a surface of the third connection electrode 45. The twelfth via V12 is configured to connect the subsequently formed anode connection electrode to the third connection electrode 45 through this via.
(7) Forming a pattern of a second conductive layer. In an exemplary embodiment, the forming a pattern of a second conductive layer may include: depositing a second conductive film on the base substrate with the above described patterns formed thereon, and patterning the second conductive film through a patterning process, to form the fourth conductive layer arranged on the first planarization layer. The fourth conductive layer includes, as shown in
In conjunction with
In some examples, the anode connection electrode 52 is provided in at least a part of the pixel driving circuits. The anode connection electrode 52 is connected to the third connection electrode 45 through the twelfth via V12. Since the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via V4, it is achieved that the anode connection electrode 53 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the third connection electrode 45.
(8) Forming a pattern of a second planarization layer. In an exemplary embodiment, the forming a pattern of a second planarization layer may include: coating a second planarization film on the base substrate with the above described patterns formed thereon, and patterning the second planarization film through a patterning process, to form the second planarization layer covering the fourth conductive layer. As shown in
In conjunction with
To this end, the driving circuit layer is formed on the base substrate. The driving circuit layer may include a plurality of pixel driving circuits in a plane parallel to the display substrate, and each of the plurality of pixel driving circuits may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a light emitting control line, a data signal line, a first power supply line, and a first initial signal line, which are connected to the pixel driving circuit. The driving circuit layer may include, in a plane perpendicular to the display substrate, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer, which are sequentially stacked on the base substrate.
(9) forming a pattern of anodes. In some examples, the forming a pattern of anodes may include: depositing a fifth conductive film on the base substrate with the above described patterns formed thereon, and patterning the fifth conductive film through a patterning process, to form the pattern of anodes arranged on the second planarization layer. As shown in
In conjunction with
In some examples, in one pixel unit, the first anode 71A is connected to the anode connection electrode 52 in the pixel driving circuit in the Mth row and Nth column through the thirteenth via V13 in this pixel driving circuit, the second anode 71B is connected to the anode connection electrode 52 in the pixel driving circuit in the (M+1)th row and Nth column through the thirteenth via V13 in this pixel driving circuit, the third anode 71C is connected to the anode connection electrode 52 in the pixel driving circuit in the Mth row and (N+1)th column through the thirteenth via V13 in this pixel driving circuit, and the fourth anode 71D is connected to the anode connection electrode 52 in the pixel driving circuit in the (M+1)th row and (N+1)th column through the thirteenth via V13 in this pixel driving circuit. In another pixel unit, the first anode 71A is connected to the anode connection electrode 52 in the pixel driving circuit in the (M+1)th row and (N+2)th column through the thirteenth via V13 in this pixel driving circuit, the second anode 71B is connected to the anode connection electrode 52 in the pixel driving circuit in the Mth row and (N+2)th column through the fourteenth via V14 in this pixel driving circuit, the third anode 71C is connected to the anode connection electrode 52 in the pixel driving circuit in the (M+1)th row and (N+3)th column through the thirteenth via V13 in this pixel driving circuit, and the fourth anode 71D is connected to the anode connection electrode 53 in the pixel driving circuit in the Mth row and (N+3)th column through the thirteenth via V13 in this pixel driving circuit.
After the pattern of anodes of the light emitting devices is formed, the manufacturing procedure further includes forming structures such as a pixel defining layer, a light emitting layer and an encapsulation layer, so as to form a plurality of light emitting devices of a light emitting structure layer. Conventional process steps may be adopted for forming the light emitting device, and therefore, the description thereof will not be repeated.
In some examples, the base substrate may be a flexible base substrate, or may be a rigid base substrate. The rigid base substrate may be, but is not limited to, one or more of glass, quartz, and the flexible base substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible base substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The first flexible material layer and the second flexible material layer may be made of Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like, for improving water-oxygen resistance of the base substrate. The semiconductor layer may be made of amorphous silicon (a-si).
In some examples, the first, second, third, and fourth conductive layers may each be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may each have a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, or the like. The first, second, third, and fourth insulating layers may each be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may each be of a single layer, a multilayer, or a composite layer. The first insulating layer is referred to as a buffer layer for improving water-oxygen resistance of the base substrate. The second and third insulating layers each are referred to as a gate insulating (GI) layer, and the fourth insulating layer is referred to as an interlayer insulating (ILD) layer. The active layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin oxide (IZTO), amorphous silicon (a-Si), poly-silicon (p-Si), hexathiophene, polythiophene, or the like. That is, the present disclosure is applicable to a transistor manufactured based on an oxide technology, a silicon technology, or an organic technology. The first and second planarization layers may be made of an organic material such as resin or the like.
As described above, it can be seen that the signal lines in the display substrate include the first scanning signal line, the second scanning signal line, the light emitting control line, and the first initial signal line, which each have the main body portion extending in the first direction, and the data line and the first power supply line, which each have the main body portion extending in the second direction. Where a blank region is reserved in the display region of the display substrate to form the functional element, these signal lines must be designed as winding or breaking so as to provide signals to the pixel driving circuit in the display substrate. In an embodiment of the present disclosure, a display substrate having a functional region in a display region is provided, which is similar to the above described display substrate and also includes the above described films, where the signal lines may include at least one of the above described first scanning signal line, second scanning signal line, light emitting control line, first initial signal line, data line, and first power supply line. The display substrate according to an embodiment of the present disclosure will be described in detail below.
In a first aspect, an embodiment of the present disclosure provides a display substrate having a display region, where the display region includes a functional region and a main display region. The functional region is provided with at least one functional unit, and each functional unit has a blank region, a winding region, and a circuit region. The winding region surrounds at least a part of the blank region, and other region except the blank region and the winding region in the functional unit is the circuit region. The display substrate includes a base substrate, and a plurality of conductive layers arranged on the base substrate, for example, including the first to fifth conductive layers described above. The plurality of conductive layers in the embodiment of the disclosure, form at least one hollow pattern, and the hollow pattern is arranged in the blank region. The plurality of conductive layers include a first signal line, and the first signal line includes a first line segment located in the main display region, a second line segment located in the circuit region and a third line segment located in the winding region. Extending directions of the first line segment and the second line segment are the same, the third line segment electrically connects the first line segment and the second line segment together, and the third line segment includes at least two line sub-segments with different extending directions.
For example, the display substrate includes a first type signal line having a main body portion extending in a first direction, and the first type signal lines include, but are not limited to, the first scanning signal line, the second scanning signal line, the light emitting control line, and the first initial signal line described above. The first type signal lines include a first sub-type signal line and a second sub-type signal line. The first sub-type signal line includes only a portion located in the main display region, and the second sub-type signal line includes not only a portion located in the main display region but also a portion located in the functional region. The second sub-signal line may be the above described first signal line. For convenience of understanding, taking the first type signal line being the second scanning signal line as an example, the second scanning signal line located in both the main display region and the functional region is the first signal line. Both of the first line segment and the second line segment of the first signal line extend in the first direction, and the third line segment of the first signal line includes not only a line sub-segment extending in the first direction but also a line sub-segment extending in the second direction. Similarly, the first scanning signal line, the light emitting control line, and the first initial signal line located in both the main display region and the functional region also may be arranged in the manner of arranging the second scanning signal line located in both the main display region and the functional region.
For another example, the display substrate includes a second type signal lines having a main body portion extending in the second direction, and the second type signal lines include, but are not limited to, the data line and the first power supply line. The second type signal lines include a third sub-type signal line and a fourth type signal line. The third sub-type signal line includes only a portion located in the main display region, and the fourth sub-type signal line includes not only a portion located in the main display region but also a portion located in the functional region. The fourth sub-type signal line may be the first signal line. For convenience of understanding, taking the second type signal line being the data line as an example, the data line located in both the main display region and the functional region is the first signal line. Both of the first line segment and the second line segment of the first signal line extend in the second direction, and the third line segment of the first signal line includes not only a line sub-segment extending in the first direction but also a line sub-segment extending in the second direction. Similarly, the first power supply line located in both the main display region and the functional region also may be arranged in the manner of arranging the data lines located in both the display region and the functional region.
In order to make the structure of the first signal line in the embodiment of the present disclosure clearer, the following description is made with reference to specific examples. For convenience of understanding, in the following description, it is taken as an example that the first signal lines are the second scanning signal line located in both the main display region and the functional region (such first signal line is hereinafter simply referred to as the second scanning signal line), and data line located in both the main display region and the functional region (such first signal line is hereinafter simply referred to as the data line), respectively.
A first example: referring to
In some examples, a plurality of first scanning signal lines 21 including a portion located in the main display region Q1 and a portion located in the functional region are provided, and in this case, the plurality of first scanning signal lines 21 are mirror-symmetrical, taking a straight line passing through the center of the blank region Q21 along the first direction X as a symmetry axis. That is, half of the first scanning signal lines 21 are routed on an upper side of the blank region Q21, and the other half of the first scanning signal lines 21 are routed on a lower side of the blank region Q21.
Accordingly, as shown in
A second example: the second example is similar to the first example except that the rectangle of the blank region Q21 is in the shape of a Chinese character “yi” (“”, which means “one” in English), which is a line shape extending in the first direction X. Referring to
”, the first scanning signal line 21 and the data line 51 are routed in the same manner as that in the first example described above, and therefore, the description thereof will not be repeated.
A third example: referring to
Specifically, referring to
Referring to
In some examples, a plurality of first scanning signal lines 21 including a portion located in the main display region Q1 and a portion located in the functional region are provided, and in this case, the plurality of first scanning signal lines 21 are mirror-symmetrical, taking a straight line passing through the center of the blank region Q21 in the first direction X as a symmetry axis. That is, half of the first scanning signal lines 21 are routed on the upper side of the blank region Q21, and the other half of the first scanning signal lines 21 are routed on the lower side of the blank region Q21.
Accordingly, referring to
In some examples, a plurality of data lines 51 including a portion located in the main display region Q1 and a portion located in the functional region are provided, and in this case, the data lines 51 are mirror-symmetrical, taking a straight line passing through the blank region Q21 in the second direction Y as a symmetry axis. That is, half of the data lines 51 are routed on the left side, and the other half of the data lines 51 are routed on the right side.
A fourth example: referring to
It should be noted that, although the routing method corresponding to the shapes of the blank regions Q21 is described above, the shape of the blank region Q21 may be in a “” shape, a “
” shape, or the like in the actual product. Since the blank regions Q21 of the “
” and the “
” shapes each include the first blank region Q211 extending in the first direction X and the second blank region Q212 extending in the second direction Y, the routing of the first signal lines is performed with reference to the above example for the existence of the two blank regions Q21.
In some examples, regardless of any of the above cases, where the third line segment of the first signal line includes a first line sub-segment along the first direction X and a second line sub-segment along the second direction Y, the first line sub-segment and the second line sub-segment may have a one-piece structure. That is, the first line sub-segment and the second line sub-segment are directly electrically connected together. In this case, the first line sub-segment and the second line sub-segment are made of the same material, so that they may be formed in the same patterning process. Alternatively, in some examples, the first line sub-segment extending in the first direction X and the second line sub-segment extending in the second direction Y in the third line segment may be distributed in two conductive layers, respectively. For example, the first conductive layer includes the first line sub-segment, the second conductive layer includes the second line sub-segment, an interlayer insulating layer is arranged between the first conductive layer and the second conductive layer, and the first line sub-segment and the second line sub-segment may be electrically connected together through a via penetrating through the interlayer insulating layer.
In some examples, regardless of any of the above cases, a line spacing between the third line segments of the first signal lines is less than a line spacing between the first line segments of the first signal lines, and the line spacing between the first line segments may be equal to a line spacing between the second line segments of the first signal lines.
In some examples, pixel driving circuits are provided in both the main display region Q1 and the circuit region Q23 in the functional region of the display substrate, and an arrangement density of the pixel driving circuits is the same. For example, the pixel driving circuits in the display substrate may be arranged in an array, and it is enough that only the winding region Q22 and the blank region Q21 is not provided with the pixel driving circuit. In this case, the pixel driving circuits in the main display region Q1 and the circuit region Q23 are arranged in the same pattern, which facilitates the manufacturing of the pixel driving circuits.
In some examples, the display substrate includes not only the above described structure but also a plurality of light emitting devices, such as OLED devices, and each pixel driving circuit is configured to drive one light emitting device to emit light. Since no pixel driving circuit is arranged in the blank region Q21 and the winding region Q22 in the functional region of the display substrate, in a case where the pixel driving circuits in the main display region Q1 and in the circuit region Q23 are arranged in the same pattern, if the areas of the anodes of the light emitting devices of the same color in the main display region Q1 and the functional region are the same, arrangement densities of the light emitting devices in the main display region Q1 and in the functional region are different. Specifically, the arrangement density of the light emitting devices in the main display region Q1 is greater than that in the functional region. The arrangement density of the light emitting devices means the number of light emitting devices of any one same color in the same region per unit area. The larger the number is, the greater the density is. Alternatively, where the arrangement density of the light emitting devices in the main display region Q1 is greater than that in the functional region, the sizes of the anodes of the light emitting devices having the same color in the main display region Q1 and the functional region may alternatively be different. For example, the size of the anode of the light emitting device in the functional region is larger than that of the light emitting device in the main display region Q1.
In some examples, an orthographic projection of anodes of at least a part of the light emitting devices in the display substrate on the base substrate covers the blank region Q21. That is, the pattern of the anodes with the orthographic projections covering the blank region Q21 determines the outline format of the hollow pattern.
In some examples, the functional component 200 may specifically be at least one of a camera, a distance sensor, a fingerprint sensor, a near field communication (NFC) antenna, a radio frequency chip, and the like.
Where the functional component 200 is a camera, the functional region may include only one functional unit, the blank region in the functional unit forms the hollow pattern, and an orthographic projection of the camera on the base substrate is within an orthographic projection of the hollow pattern on the base substrate. That is, an orthographic projection of a conductive element (for example, a first scanning line, a second scanning line, a data line, an anode of a light emitting device, etc.) in any conductive layer in the display substrate 100 on the base substrate does not overlap the orthographic projection of the camera on the base substrate, thereby ensuring an image capturing function of the camera.
Where the functional component 200 is a distance sensor, the electronic apparatus may realize a distance measuring function. In this case, the orthographic projection of the hollow pattern in the functional unit on the base substrate may partially overlap an orthographic projection of the distance sensor on the base substrate, but the distance measuring function of the distance sensor is not affected. In an embodiment, the orthographic projection of the hollow pattern on the base substrate covers the orthographic projection of the distance sensor on the base substrate, so that an influence of a signal sent by the distance sensor during the distance sensor is working on an operation of the display device is avoided.
Where the functional component 200 is a fingerprint sensor, the functional region may include a plurality of functional units. Each functional unit is correspondingly provided with one fingerprint sensor. An orthographic projection of each fingerprint sensor on the base substrate may partially overlap the orthographic projection of one hollow pattern on the base substrate, as long as it is ensured that light emitted by the light emitting device irradiates onto the finger and then be reflected to the fingerprint sensor, thereby realizing the function of fingerprint identification.
Where the functional component 200 is a near field communication antenna, the functional region may include only one functional unit, the blank region in the functional unit forms the hollow pattern, and an orthographic projection of the near field communication antenna on the base substrate is within an orthographic projection of the hollow pattern on the base substrate, so as to avoid signal radiation of the near field communication antenna from affecting the operation of the display device.
Where the functional component 200 is a radio frequency chip, an orthographic projection of the radio frequency chip on the base substrate may at least partially overlap the orthographic projection of the hollow pattern in the functional region on the base substrate. In this case, a microwave signal transmitted by the radio frequency chip may be subjected to frequency selection through the hollow pattern in the functional region, so as to realize radiation of the microwave signal in a specific frequency band.
Only several functional components 200 are described in the above, but this does not limit the protection scope of the embodiments of the present disclosure.
The electronic apparatus may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiment of the present invention is not limited thereto.
It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to one of ordinary skill in the art that various modifications and improvements can be made without departing from the spirit and scope of the present disclosure, and such modifications and improvements are also considered to be within the scope of the present disclosure.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/125663 | 10/22/2021 | WO |
