Patent Application
20090251656
This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2008-31067, filed on Apr. 3, 2008, the disclosure of which is hereby incorporated by reference herein in it's entirety.
1. Technical Field
Example embodiments of the present invention relates to a display substrate and to a method for manufacturing the display substrate.
2. Description of the Related Art
In a liquid crystal display (LCD) apparatus, an image may be displayed by applying a voltage to a liquid crystal layer interposed between two glass substrates and controlling light transmissivity. Generally, borosilicate glass substrates are used for the glass substrates. A borosilicate glass substrate has high resistance to thermal shock, rapid temperature variation and chemical corrosion. However, the price of the borosilicate glass substrate may be high so that the borosilicate glass substrate may make up a large portion of the cost of materials for the LCD apparatus.
On the other hand, a soda-lime glass substrate may be cheaper, and may have high resistance to corrosive compounds because the soda-lime glass substrate is an oxide mixture including silica, calcium, sodium and so on. However, the soda-lime glass substrate may become warped in a high-temperature process, so that it may be difficult to maintain the uniformity of a thin film. In addition, another difficulty which may be associated with the soda-lime glass substrate is that alkali ions, such as the sodium, may flow into the thin film from the soda-lime glass substrate so that device characteristics of the product may be deteriorated or the reliability of the product may be reduced. Accordingly, the soda-lime glass substrate may be difficult to apply to the LCD apparatus.
However, the demand for large-sized LCD apparatus is rapidly increasing, and thus a technique for applying the cheaper soda-lime glass substrate to the LCD apparatus instead of the expensive borosilicate glass substrate may be required to enhance price competitiveness.
Exemplary embodiments of the present invention may provide a display substrate to enhance the reliability of a product.
Exemplary embodiments of the present invention may also provide a method for manufacturing the display substrate.
In accordance with an exemplary embodiment of the present invention, a display substrate is provided. The display substrate includes a soda-lime glass substrate, a first conductive pattern, a barrier pattern, a second conductive pattern and a third conductive pattern. The soda-lime glass substrate has a pixel area. The first conductive pattern includes a gate line. The gate line is formed on the soda-lime glass substrate and is formed from a first conductive layer. The barrier pattern is formed between the first conductive pattern and the soda-lime glass substrate. The second conductive pattern includes a data line crossing the gate line. The data line is formed on the first conductive pattern and is formed from a second conductive layer. The third conductive pattern includes a pixel electrode formed in the pixel area of the soda-lime glass substrate. The pixel electrode is formed on the second conductive pattern and is formed from a third conductive layer.
In accordance with an exemplary embodiment of the present invention, a display substrate is provided. The display substrate includes a soda-lime glass substrate, a gate line, a gate circuit part, a circuit barrier pattern, a data line and a pixel electrode. The soda-lime glass substrate has a plurality of pixel areas. The gate line is formed by making direct contact with the soda-lime glass substrate. The gate circuit part applies a driving signal to the gate line. The circuit barrier pattern is disposed between the gate circuit part and the soda-lime glass substrate. The data line crosses the gate line. The pixel electrode is formed in each of the pixel areas.
In accordance with an exemplary embodiment of the present invention, a method for manufacturing a display substrate is provided. The method includes forming a barrier layer and a first conductive layer on a soda-lime glass substrate, wherein the soda-lime glass substrate includes a pixel area. A first conductive pattern having a gate line and a barrier pattern is formed between the first conductive pattern and the soda-lime glass substrate, by patterning the barrier layer and the first conductive layer using substantially the same mask. A second conductive pattern including a data line crossing the gate line is formed. The data line is formed on the first conductive pattern and is formed from a second conductive layer. A third conductive pattern including a pixel electrode is formed in the pixel area of the soda-lime glass substrate. The pixel electrode is formed on the second conductive pattern and is formed from a third conductive layer.
In accordance with another exemplary embodiment of the present invention, a method for manufacturing a display apparatus is provided. The method includes forming a barrier layer on a soda-lime glass substrate. The soda-lime glass substrate has a display area a gate circuit area in which a gate circuit part is formed and a pixel area. A circuit barrier pattern is formed in the gate circuit area, by patterning the barrier layer. A first conductive pattern including a gate line is formed. The gate line is formed on the soda-lime glass substrate having the circuit barrier pattern formed thereon and is formed from the first conductive layer. A second conductive pattern including a data line crossing the gate line is formed. The data line is formed on the soda-lime glass substrate having the first conductive pattern formed thereon and is formed from the second conductive layer. A third conductive pattern including a pixel electrode formed in the pixel area of the soda-lime glass substrate is formed. The pixel electrode is formed on the second conductive pattern and is formed from a third conductive layer.
According to exemplary embodiments of the present invention, a patterned barrier layer is formed on a soda-lime glass substrate, so that an area in which the barrier layer is formed may be decreased, malfunctions due to foreign matter may be decreased, and the light transmissivity may be enhanced.
Exemplary embodiments of the present invention can be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which:
The invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and relative sizes of layers and areas may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, areas, layers and/or sections, these elements, components, areas, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or section from another area, layer or section. Thus, a first element, component, area, layer or section discussed below could be termed a second element, component, area, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments of the invention should not be construed as limited to the particular shapes of areas illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted area illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted area. Likewise, a buried area formed by implantation may result in some implantation in the area between the buried area and the surface through which the implantation takes place. Thus, the areas illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of an area of a device and are not intended to limit the scope of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, the exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
Referring to
The data circuit area DCA is defined as an area adjacent to a portion of the data line DL, and a data pad part 210 is formed in the data circuit area DCA. The data pad part 210 includes input pads receiving a signal from outside and output pads electrically connected to the data line DL. For example, a data driving circuit may be mounted on the data circuit area DCA as a chip type, or a flexible printed circuit board (FPCB) having the data driving circuit mounted thereon may be mounted on the data circuit area DCA. Alternatively, the data driving circuit and a line for driving the data driving circuit may be directly formed on the data circuit area DCA.
The gate circuit areas GCA1 and GCA2 are defined as areas adjacent to both end portions of the gate line GL. For example, a first gate circuit part 230 which outputs a high voltage to the gate line GL is formed in a first gate circuit area GCA1 adjacent to a first end portion of the gate line GL. The first gate circuit part 230 includes a gate driving circuit 231 and a first line 233. The gate driving circuit 231 includes a second switching element TR2 to sequentially output the high voltage. The first line 233 is electrically connected to the data pad part 210 to transfer a driving signal of the gate driving circuit 231 to the gate driving circuit 231.
A second gate circuit part 250 is formed in a second gate circuit area GCA2 adjacent to a second end portion of the gate line GL. The second gate circuit part 250 includes a subsidiary driving circuit 251 and a second line 253. The subsidiary driving circuit 251 maintains a voltage of the gate line GL to be a low voltage. The second line 253 is electrically connected to the data pad part 210 to transfer a driving signal of the subsidiary driving circuit 251 to the subsidiary driving circuit 251. The subsidiary driving circuit 251 also includes the second switching element TR2.
As mentioned above, the subsidiary driving circuit 251 is formed in the second gate circuit area GCA2. Alternatively, a gate driving circuit substantially the same as the gate driving circuit 231 may be formed in the second gate circuit area GCA2. In this case, the gate driving circuit formed in the first gate circuit area GCA1 may drive odd-numbered gate lines, and the gate driving circuit formed in the second gate circuit area GCA2 may drive even-numbered gate lines.
Referring to
The SLG substrate 101 includes a pixel area PA in which the pixel portion P is formed, and first and second gate circuit areas GCA1 and GCA2 in which the first and second gate circuit parts 230 and 250 are respectively formed. The first and second gate circuit areas GCA1 and GCA2 will be referred to as the gate circuit area GCA in the following descriptions.
Barrier patterns 111, 113 and 117 are formed on the SLG substrate 101. The barrier patterns 111, 113 and 117 are formed between the SLG substrate 101 and a first conductive pattern. The barrier patterns 111, 113 and 117 are patterned in substantially the same way as the first conductive pattern.
The barrier patterns 111, 113 and 117 strengthen the adhesive strength between the SLG substrate 101 and the first conductive pattern. For example, the barrier patterns 111, 113 and 117 prevents the first conductive pattern from being disconnected or released from the SLG substrate 101 due to alkali ions from the SLG substrate 101. The barrier patterns 111, 113 and 117 may include, for example, a conductive material, a non-conductive material, a transparent material or an opaque material. For example, the barrier patterns 111, 113 and 117 may include one of molybdenum, amorphous indium-tin-oxide (a-ITO), indium-tin-oxide (ITO), indium-zinc-oxide (IZO), silicon nitride (SiNx), silicon oxide (SiOx) and a metal compound. The metal compound may be, for example, one of a metal oxide, a metal nitride, a metal boride and a metal carbide. The thickness of the barrier layer 110 may be between about 50 angstroms (Å) and about 2,000 Å.
The first conductive pattern includes a gate line GL formed in the pixel area PA, a first gate electrode GE1 of the first switching element TR1, a storage line STL, and a second gate electrode GE2 of the second switching element TR2.
For example, the barrier patterns 111, 113 and 117 are formed beneath the first gate electrode GE1, the storage line STL and the second gate electrode GE2, respectively. The first gate electrode GE1 is protruded from the gate line GL, so that the barrier pattern 111 is formed beneath the gate line GL in substantially the same way as the first gate electrode GE1.
Accordingly, the barrier patterns 111, 113 and 117 that are patterned in substantially the same way as when forming the first conductive pattern on the SLG substrate 101, so that malfunctions due to adhesive foreign matter may be decreased.
For example, when the foreign matter is adhered to a surface of the SLG substrate 101, the barrier layer is formed on the SLG substrate 101 to strengthen the adhesive strength between the SLG substrate 101 and the first conductive pattern. In this case, when heat is generated due to additional processes, a gas may flow from a portion to which the foreign matter is adhered, so that the barrier layer is exploded. Accordingly, the lines formed on the barrier layer may be disconnected or be released. Thus, the barrier layer is patterned in substantially the same way as the first conductive pattern to decrease the area of the barrier layer, so that malfunctions due to the adhesive foreign matter may be decreased.
A gate insulation layer 130 is formed on the SLG substrate 101 on which the first conductive pattern is formed. A first semiconductor pattern 141 of the first switching element TR1 and a second semiconductor pattern 142 of the second switching element TR2 are formed on the gate insulation layer 130. The first and second semiconductor patterns 141 and 142 include an active layer 140a doped with impurities and a resistant contact layer 140b formed on the active layer 140a, respectively.
A second conductive pattern is formed on the SLG substrate 101 on which the first and second semiconductor patterns 141 and 142 are formed. The second conductive pattern includes a data line DL crossing the gate line GL, a first source electrode SE1 of the first switching element TR1, a first drain electrode DE1 of the first switching element TR1, a second source electrode SE2 of the second switching element TR2 and a second drain electrode DE2 of the second switching element TR2. The data line DL, the first source electrode SE1 and the first drain electrode DE1 are formed in the pixel area PA. The second source electrode SE2 and the second drain electrode DE2 are formed in the gate circuit area GCA.
A protective insulation layer 160 is formed on the SLG substrate 101 on which the second conductive pattern is formed. A pixel electrode PE electrically connected to the first drain electrode DE1 is formed on the protective insulation layer 160.
Referring to
A first conductive layer 120 is formed on the barrier layer 110. The first conductive layer 120 may include, for example, at least one of chromium (Cr), chromium (Cr) alloy, molybdenum (Mo), molybdenum-nitride (MoN), molybdenum-niobium (MoNb), molybdenum (Mo) alloy, copper (Cu), copper (Cu) alloy, copper-molybdenum (CuMo) alloy, aluminum (Al), aluminum (Al) alloy, silver (Ag) and silver (Ag) alloy.
A photoresist layer is formed on the SLG substrate 101 on which the first conductive layer 120 is formed, and then the photoresist layer is patterned using a mask to leave a photoresist pattern PR in a first area MA1 in which the first conductive pattern is formed.
The first conductive pattern includes the gate line GL, the first gate electrode GE1, the storage line STL and the second gate electrode GE2. The barrier layer 110 and the first conductive layer 120 are patterned using the photoresist pattern PR to form the first conductive pattern on the SLG substrate 101.
When the barrier layer 110 includes the metal material such as, for example, a-ITO, IZO and molybdenum (Mo), the barrier layer 110 and the first conductive layer 120 may be patterned, for example, by a wet etching at the same time. However, when the barrier layer 110 includes the insulating material and the metal compound, the barrier layer 110 may be patterned by, for example, a dry etching and the first conductive layer 120 may be patterned by, for example, the wet etching.
Referring to
The area of the barrier layer 110 formed on the SLG substrate 101 may be decreased, so that malfunctions due to the foreign matter adhered between the SLG substrate 101 and the barrier layer 110 may be decreased. In addition, the barrier layer 110 is patterned to enhance the light transmissivity of the display substrate 100.
The gate insulation layer 130 is formed on the SLG substrate 101 on which the first conductive pattern is formed. The first and second semiconductor patterns 141 and 142 are formed on the SLG substrate 101 on which the gate insulation layer 130 is formed. The semiconductor layer 140 including the active layer 140a doped with the impurities and the resistant contact layer 140b is formed on the gate insulation layer 130. The semiconductor layer 140 is patterned using the photoresist pattern PR to form the first and second semiconductor patterns 141 and 142 on the first and second gate electrodes GE1 and GE2.
Referring to
The photoresist layer is formed on the SLG substrate 101 on which the second conductive layer 150 is formed, and the photoresist layer is patterned using, for example, a slit mask, so that the photoresist pattern PR is formed on the area in which the second conductive pattern is formed. The second conductive pattern includes the data line DL, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2 and the second drain electrode DE2. Thus, the photoresist pattern PR has a first thickness in an area in which the second conductive pattern is formed, and has a second thickness in an area correspond to a channel area of the first and second switching elements TR1 and TR2. The first thickness is thicker than the second thickness.
The data line DL, an electrode pattern of the first switching element TR1 and an electrode pattern of the second switching element TR2 are formed by patterning the second conductive layer 150 using the photoresist pattern PR. Then, the photoresist pattern PR is eliminated by a constant thickness to expose the electrode patterns on the channel areas C1 and C2 of the first and second switching elements TR1 and TR2, and to leave the photoresist pattern PR on the second conductive pattern. The electrode patterns on the channel areas C1 and C2 are patterned using the remaining photoresist pattern PR, to form the first source electrode SE1 and the first drain electrode DE1 separated from each other and to form the second source electrode SE2 and the second drain electrode DE2 separated from each other. Accordingly, the first and second switching elements TR1 and TR2 are completed.
Referring to
A third conductive layer 170 is formed on the SGL substrate 101 through which the contact hole 161 is formed. For example, the third conductive layer 170 may include the transparent conductive material such as IZO, ITO and a-ITO. The photoresist layer is formed on the third conductive layer 170, and the photoresist layer is patterned using the mask to form the photoresist pattern PR. The third conductive layer 170 is patterned using the photoresist pattern PR to form a third conductive pattern including the pixel electrode PE.
Referring to
The barrier patterns are formed on the SLG substrate 101. The barrier patterns 111 and 113 patterned in substantially the same way as the first conductive pattern are formed in the pixel area PA to decrease the area of the barrier layer. Thus, malfunctions due to the adhesive foreign matter may be decreased.
A circuit barrier pattern 110c is entirely formed in the gate circuit area GCA. The circuit barrier pattern 110c strengthens the adhesive strength between the SLG substrate 101 and the gate circuit part formed on the SGL substrate 101.
When the gate circuit part is driven, the heat is generated in itself and the heat accelerates the flow of the alkali ions of the SLG substrate 101, so that the adhesive strength between the gate circuit part and the SLG substrate 101 may be weakened. For example, the area of the second semiconductor pattern 142 of the second switching element TR2 is larger than that of the first semiconductor pattern 141 of the first switching element TR1, so that the temperature of the heat generated by an electric signal is higher in the gate circuit area GCA than in the pixel area PA. Accordingly, the adhesive strength between the gate circuit part and the SLG substrate 101 may be weakened.
Thus, the circuit barrier pattern 110c is entirely formed in the gate circuit area GCA, to strengthen the adhesive strength between the gate circuit part and the SLG substrate 101.
Referring to
The photoresist layer is formed on the SLG substrate 101 on which the barrier layer 110 is formed, and the photoresist layer is patterned using the mask to form the photoresist pattern PR. The photoresist pattern PR is formed in the area of the pixel area PA in which the first conductive pattern, for example the gate line GL, the first gate electrode GE1 and the storage line STL, is formed. The photoresist pattern PR is entirely formed in the gate circuit area GCA.
Referring to
The first conductive layer 120 is formed on the SLG substrate 101 on which the barrier patterns 111 and 113 and the circuit barrier pattern 110c are formed. The photoresist layer is formed on the first conductive layer 120, and the photoresist layer is patterned using the mask, to form the photoresist pattern PR on the first conductive layer 120. The photoresist pattern PR is formed in the area in which the first conductive pattern is formed, for example the first area MA1. The photoresist pattern PR is formed in the area of the pixel area PA in which the gate line GL, the first gate electrode GE1 and the storage line STL are formed. The photoresist pattern PR is formed in the area of the gate circuit area GCA in which the second gate electrode GE2 is formed.
Referring to
The process of forming the semiconductor patterns 141 and 142, the second conductive pattern including the data line DL and the third conductive pattern including the pixel electrode PE on the SLG substrate 101, is substantially the same as the process explained in
Referring to
The circuit barrier pattern 110c is formed on the SLG substrate 101 to correspond to the gate circuit area GCA. The barrier pattern may not be formed in the pixel area PA.
The gate circuit part is formed in the gate circuit area GCA. When the gate circuit part is driven, the heat generated from the gate circuit part accelerates the generation of the alkali ions from the LSG substrate 101, so that the adhesive strength between the SLG substrate 101 and the gate circuit part may be weakened. The circuit barrier pattern 110c is entirely formed in the gate circuit area GCA to strengthen the adhesive strength between the SLG substrate 101 and the gate circuit part.
In the pixel area PA, the first conductive pattern, the gate line GL, the first gate electrode GE1 and the storage line STL are directly formed on the SLG substrate 101. The barrier pattern may not be formed in the pixel area PA, so that malfunctions due to the adhesive foreign matter may be prevented and the light transmissivity may be enhanced.
Referring to
Comparing the first graph A to the second graph B, the resistance Rg of the gate electrode in the panel including the SLG substrate without the barrier layer is substantially the same as that in the panel including the SLG substrate with the barrier layer. Thus, when the display panel is driven, the heat and an electric field generated from the pixel area PA are much smaller than those generated from the gate circuit area GCA. Thus, difficulties such as disconnecting and breaking of lines that are caused by weakening of the adhesive strength due to the alkali ions, may be significantly decreased. Accordingly, the barrier pattern may not be formed in the pixel area PA.
Referring to
The photoresist layer is formed on the SLG substrate 101 on which the barrier layer 110 is formed, and the photoresist layer is patterned using the mask to form the photoresist pattern PR. The photoresist pattern PR is entirely formed in the gate circuit area GCA, and may not be formed in the pixel area PA.
Referring to
Referring to
Referring to
Then, the processes of forming the second conductive pattern including the semiconductor patterns 141 and 142 and the data line DL, and the third conductive pattern including the pixel electrode PE on the SLG substrate 101, are substantially the same as the processes in
According to exemplary embodiments of the present invention, the area of a soda-lime glass substrate in which a barrier layer is formed may be decreased, so that malfunctions due to foreign matter adhered to the soda-lime glass substrate may be decreased. In addition, the barrier layer may not be formed in the pixel area to thereby enhance light transmissivity.
Having described the exemplary embodiments of the present invention, it is further noted that it is readily apparent to those of reasonable skill in the art that various modifications may be made without departing from the spirit and scope of the invention which is defined by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-31067 | Apr 2008 | KR | national |
