DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Chinese Patent Application No. 201710212461.9 filed on Mar. 31, 2017, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to the field of display technologies, and specifically to a display substrate, its manufacturing method, and a display panel.

BACKGROUND

Because of the advantages such as small sizes, low energy consumption, no radiation, and low manufacturing cost, thin-film transistor liquid crystal displays (TFT-LCDs) have been widely applied in various fields, including the field of vehicle-mounted display.

In a vehicle-mounted display, the liquid crystal display panel typically includes a display substrate (also known as thin-film transistor panel), and an encasing substrate (sometimes known as the color filter substrate). Usually the display substrate is provided with one or more conductive adhesive coating portions configured to provide regions for coating a conductive adhesive (e.g., a silver paste) thereupon, and the encasing substrate is equipped with a coupling portion, which may include an anti-static sub-portion configured to collect and guide out the static electricity that is accumulated in the encasing substrate.

SUMMARY

The present disclosure provides a display substrate, its manufacturing method, and a display panel including the display substrate.

In a first aspect, a display substrate is disclosed. The display substrate includes a substrate, a first portion, a second portion, and a protruding portion. The first portion, the second portion, and the protruding portion are disposed over an upper surface of the substrate.

The first portion is configured to coat a conductive adhesive thereon for attachment, and for electric coupling, of the display substrate with an encasing substrate. The second portion includes at least one wiring. The protruding portion is disposed between the first portion and the second portion, and is configured to prevent the conductive adhesive coated on the first portion from spreading to the second portion.

According to some embodiments of the display substrate, an upper surface of the protruding portion has a larger distance to the upper surface of the substrate than an upper surface of the first portion. According to some other embodiments, an upper surface of the protruding portion has a distance to the upper surface of the substrate smaller than, or equal to, an upper surface of the first portion.

In the display substrate, one or more first depressions can be arranged between the first portion and the protruding portion. The one or more first depressions are configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate than the upper surface of the first portion.

The one or more first depressions can take a shape of strips, extending in a direction substantially parallel to one of the at least one wiring in the second portion that is closest to the first portion, and can take other shapes as well.

According to some embodiments, the bottom surface of the one or more first depressions is on a substantially same plane as the upper surface of the substrate.

The display substrate can further include a display area having a plurality of layers, and the protruding portion can include at least one patterned layer, configured to be at a substantially same layer as one or more of the plurality of layers in the display area of the display substrate.

Herein the one or more of the at least one patterned layer of the protruding portion can be further configured to have a substantially same composition as one or more of the plurality of layers in the display area of the display substrate.

The display area can include at least one thin-film transistor and at least one pixel electrode, which are disposed over the upper surface of the substrate. The one or more of the at least one patterned layer in the protruding portion is configured to be at a substantially same layer, and have a substantially same composition, as at least one of a gate electrode, an active layer, or a source electrode and a drain electrode, of the at least one thin-film transistor, or the at least one pixel electrode.

According to some embodiments of the display substrate, the protruding portion includes a first patterned layer, a second patterned layer, a third patterned layer, and a fourth patterned layer. It is configured such that the first patterned layer is at a substantially same layer, and has a substantially same composition, as the gate electrode; the second patterned layer is at a substantially same layer, and has a substantially same composition, as the active layer; the third patterned layer is at a substantially same layer, and has a substantially same composition, as the source electrode and the drain electrode; and the fourth patterned layer is at a substantially same layer, and has a substantially same composition, as the pixel electrode.

In some embodiments of the display substrate as described above, the display area comprises at least one thin-film transistor, at least one pixel electrode, at least one common electrode, and a passivation layer, disposed over the upper surface of the substrate. The one or more of the at least one patterned layer in the protruding portion can be configured to be at a substantially same layer, and have a substantially same composition, as at least one of a gate electrode, an active layer, or a source electrode and a drain electrode, of the at least one thin-film transistor, the at least one pixel electrode, the at least one common electrode, or the passivation layer.

In some embodiments of the display substrate as described above, the protruding portion comprises a first patterned layer, a second patterned layer, a third patterned layer, a fourth patterned layer, and a fifth patterned layer. It is configured such that the first patterned layer is at a substantially same layer, and has a substantially same composition, as the gate electrode; the second patterned layer is at a substantially same layer, and has a substantially same composition, as the active layer; the third patterned layer is at a substantially same layer, and has a substantially same composition, as the source electrode and the drain electrode; the fourth patterned layer is at a substantially same layer, and has a substantially same composition, as the pixel electrode; and the fifth patterned layer is at a substantially same layer, and has a substantially same composition, as the at least one common electrode.

According to some embodiments of the display panel, an upper surface of the first portion is provided with one or more second depressions, which are configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate than the upper surface of the first portion.

The one or more second depressions can take a shape of strips, extending in a direction substantially parallel to one of the at least one wiring in the second portion that is closest to the first portion, and can take other shapes as well.

In the display substrate as described above, the first portion includes a metal patterned layer, an insulating layer, and a transparent conductive patterned layer, which are sequentially disposed over the upper surface of the substrate.

The metal patterned layer can be provided with at least one first opening, which is configured such that an orthographic projection of the at least one first opening on the substrate is overlapped with an orthographic projection of the one or more second depressions on the substrate. The insulating layer can be provided with at least one second opening, which is configured such that an orthographic projection of the at least one second opening on the substrate is overlapped with an orthographic projection of the one or more second depressions on the substrate.

Herein the metal patterned layer can be configured to be at a substantially same layer, and have a substantially same composition, as either or both of a source electrode and a drain electrode, or a gate electrode of at least one thin-film transistor in the display substrate, and the transparent conductive patterned layer is configured to be at a substantially same layer, and have a substantially same composition, as either or both of at least one pixel electrode or at least one common electrode in the display substrate.

In a second aspect, the disclosure further provides a display panel. The display panel comprises an encasing substrate and a display substrate according to any one embodiment of the display substrate as mentioned above.

The encasing substrate is assembled with the display substrate, and is electrically coupled with the display substrate via the conductive adhesive coated onto the first portion of the display substrate.

In the display panel, the first portion on the display substrate can include two conductive adhesive coating sub-portions, and the two conductive adhesive coating sub-portions can be disposed respectively at two ends of a diagonal line on the display substrate.

In the display panel, the encasing substrate can be provided with a coupling portion, which is configured to be electrically coupled with the first portion on the display substrate via the conductive adhesive. The coupling portion can include an anti-static sub-portion, which comprises a transparent conductive film, disposed on a side of the encasing substrate far away from the display substrate.

In any of the display panel as described above, the conductive adhesive can be a silver paste.

In a third aspect, the disclosure further provides a method for manufacturing a display panel. The method includes a step of forming a first portion, a second portion, and a protruding portion over an upper surface of a substrate. The first portion is configured to coat a conductive adhesive thereon for attachment, and for electric coupling, of the display substrate with an encasing substrate. The second portion comprises at least one wiring. The protruding portion is disposed between the first portion and the second portion, and is configured to prevent the conductive adhesive coated on the first portion from spreading to the second portion.

Other embodiments may become obvious in light of the aforementioned display substrate, the manufacturing method thereof, and the display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

To more clearly illustrate some of the embodiments disclosed herein, the following is a brief description of the drawings. The drawings in the following descriptions are only illustrative of some embodiments. For those of ordinary skill in the art, other drawings of other embodiments can become apparent based on these drawings.

FIG. 1 illustrates a structural diagram of a non-display area having a conductive adhesive coating portion and a wiring region in a conventional display substrate;

FIG. 2A is a schematic diagram of a non-display area of a display substrate according to a first embodiment of the present disclosure;

FIG. 2B illustrates the display substrate as shown in FIG. 2A, where the conductive adhesive is applied onto the conductive adhesive coating portion and there are ruptures and perforations in the passivation layer;

FIG. 3A is a schematic diagram of a non-display area of a display substrate according to a second embodiment of the present disclosure;

FIG. 3B illustrates the display substrate as shown in FIG. 3A, where the conductive adhesive is applied onto the conductive adhesive coating portion and there are ruptures and perforations in the passivation layer;

FIG. 4A is a schematic diagram of a display area of a display substrate according to a third embodiment of the present disclosure;

FIG. 4B is a schematic diagram of a non-display area of the display substrate as mentioned in FIG. 4A;

FIG. 5A is a schematic diagram of a display area of a display substrate according to a fourth embodiment of the present disclosure;

FIG. 5B is a schematic diagram of a non-display area of the display substrate as mentioned in FIG. 5A;

FIG. 6A is a schematic diagram of a non-display area of a display substrate according to a fifth embodiment of the present disclosure;

FIG. 6B is a schematic diagram of a non-display area of a display substrate according to a sixth embodiment of the present disclosure;

FIG. 7A is a schematic diagram of a non-display area of a display substrate according to a seventh embodiment of the present disclosure;

FIG. 7B illustrates the display substrate as shown in FIG. 7A, where the conductive adhesive is applied onto the conductive adhesive coating portion and there are ruptures and perforations in the passivation layer;

FIG. 8 is a top view of the metal patterned layer of the conductive adhesive coating portion in the display substrate as shown in FIG. 7A;

FIG. 9 is a schematic diagram of a non-display area of a display substrate according to an eighth embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a non-display area of a display substrate according to a ninth embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a non-display area of a display substrate according to a tenth embodiment of the present disclosure;

FIG. 12 is a top view of a display panel according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates one conventional conductive adhesive coating portion according to an existing technology. As shown in FIG. 1, the conductive adhesive coating portion 10 comprises a metal patterned layer 101 and a transparent conductive patterned layer 102. The transparent conductive patterned layer 102 is disposed on an outer surface (i.e. an upper surface as shown in FIG. 1) of the display substrate, and is electrically connected with the metal patterned layer 101 through vias 103 arranged on a passivation layer 20 that is sandwiched between the metal patterned layer 101 and the transparent conductive patterned layer 102.

In a conductive adhesive coating process (also known as a silver dotting process if a silver paste is used as a conductive adhesive 30) in which the conductive adhesive 30 is applied on a top surface of the conductive adhesive coating portion 10 to thereby allow the attachment of the display substrate and the encasing substrate, while at the same time to realize an electrical connection between the coupling portion (e.g. anti-static sub-portion) of the encasing substrate and a common electrode of the display substrate through the conductive adhesive 30 and the conductive adhesive coating portions 10.

Because the conductive adhesive coating portion is electrically connected to a grounding wire (such as a common electrode?), the static electricity accumulated in the encasing substrate can be guided out by means of the electrical connection through the conductive adhesive and the conductive adhesive coating portion. As such the reliability of the vehicle-mounted display can be effectively increased.

However, during a conventional conductive adhesive coating process, because the conductive adhesive 30 employed for coating the conductive adhesive coating portion 10 usually has a certain level of fluidity, the conductive adhesive 30 can occasionally spread to a wiring region (i.e. a region of the display substrate having wirings 40 disposed therein, as illustrated in FIG. 1) in the proximity of the conductive adhesive coating portion 10.

Because of the environment where the vehicle-mounted displays are applied, rupture and perforation occasionally occur on the passivation layer 20 during use, transportation, and/or reliability tests of the vehicle-mounted displays. Consequently, short circuiting can occasionally happen due to the contact of the conductive adhesive 30 with the wirings 40 that are exposed because of the ruptures and perforations in the passivation layer 20, in turn leading to a poor display effect.

In the following, with reference to the drawings of various embodiments disclosed herein, the technical solutions of the embodiments of the disclosure will be described in a clear and fully understandable way.

It is obvious that the described embodiments are merely a portion but not all the embodiments of the disclosure. Based on the described embodiments of the disclosure, those ordinarily skilled in the art can obtain other embodiment(s), which come(s) within the scope sought for protection by the disclosure.

In one aspect, the present disclosure provides a display substrate.

The display substrate comprises a substrate, a first portion, a second portion, and a protruding portion. The first portion, the second portion, and the protruding portion are disposed over an upper surface of the substrate.

Herein any of the first portion, the second portion, and the protruding portion can be disposed directly on an upper surface of the substrate, but can also be disposed to have a distance to the upper surface of the substrate.

It is noted that throughout the disclosure, the terms “upper surface” and “lower surface” are relative terms that are respectively referred to as one and another of the two opposing surfaces of an object, and are relative to the viewing angle of the object that is illustrated in the drawings, but do not impose any special or positional limitations.

FIG. 2A shows a non-display area of a display substrate according to a first embodiment of the present disclosure.

As illustrated in FIG. 2A, in the non-display area, this first embodiment of the display substrate 01 includes a conductive adhesive coating portion 10, and at least one wiring 40. The conductive adhesive coating portion 10 is configured to provide a coating region for a conductive adhesive to allow a subsequent attachment of the display substrate with an encasing substrate. The at least one wiring 40 is located in a wiring region (i.e. the region in the display substrate 01 that has the at least one wiring 40 disposed therein).

As shown in FIG. 2A, the display substrate 01 further includes a protruding portion 60, which is disposed between the conductive adhesive coating portion 10 and one of the at least one wiring 40 that is closest to the conductive adhesive coating portion 10.

The protruding portion 50 is configured to have a larger height from a reference surface than the conductive adhesive coating portion 10. Herein the reference surface is referred to an upper surface of the substrate 50, and the upper surface of the substrate 50 is referred to as a surface of the substrate 50 on which the conductive adhesive coating portion 10 and at least one wiring 40 are disposed.

The height of the protruding portion 50/conductive adhesive coating portion 10 is defined as a distance between an upper surface of the protruding portion 50/conductive adhesive coating portion 10 from the reference surface. An upper surface of the protruding portion 50/conductive adhesive coating portion 10 is referred to as a surface thereof that is farthest away from the upper surface of the substrate 50.

The protruding portion 60 is configured to separate the conductive adhesive coating portion 10 with the at least one wiring 40 to thereby block the conductive adhesive 30 from spreading to the wiring region during a conductive adhesive coating process (the display substrate 01 having the conductive adhesive coating portion 10 coated with the conductive adhesive 30 is illustrated in FIG. 2B).

Because of the separation and block of the protruding portion 60, it is difficult for the conductive adhesive 30 to spread to the wiring region. As such, as illustrated in FIG. 2B, if rupture and/or perforation occurs in the passivation layer 20, because there is no conductive adhesive 30 in the wiring region to electrically connect the wirings 40 in the wiring region through the ruptures and/or the perforations in the passivation layer 20, the issue of short circuiting can be effectively avoided.

The following are noted for the embodiments of the display substrate 01 as described above.

First, as known by people of ordinary skill in the field, the conductive adhesive coating process is performed only when it is needed for the display substrate and the encasing substrate to align together for encasing (or attachment), when the conductive adhesive 30 is coated onto a top surface of the conductive adhesive coating portion 10 of the display substrate. To provide an anti-static function, the conductive adhesive coating portion 10 is further configured to be electrically connected to a grounding wiring on the display substrate 01.

Second, more than one conductive adhesive coating portions 10 can be employed. The number of the conductive adhesive coating portion 10 can be chosen based on a size of the display panel having the display substrate 01.

If the display panel is small, only one conductive adhesive coating portion 10 is needed; and if the display panel is relatively big-sized, two or more conductive adhesive coating portions 10 can be employed to allow a sufficient grounding for the anti-static sub-portion on the encasing substrate. For example, two conductive adhesive coating portions 10 can be configured on the display substrate of a vehicle-mounted display panel.

It is noted that regardless of how many conductive adhesive coating portions 10 that are employed in the display substrate, all the conductive adhesive coating portions 10 and the at least one wiring 40 shall be arranged in a non-display area of the substrate 50.

Third, the protruding portion 60 can have any shape or structure as long as it can block the spreading of the conductive adhesive 30 during the conductive adhesive coating process.

In the display substrate 01 as shown in FIG. 2A and FIG. 2B, the conductive adhesive coating portion 10 includes a metal patterned layer 101, a transparent conductive patterned layer 102, and a passivation layer 20.

The metal patterned layer 101 and the transparent conductive patterned layer 102 are disposed consecutively over the upper surface of the substrate 50, and the passivation layer 20 is sandwiched between, and configured to insulate, the metal patterned layer 10 and the transparent conductive patterned layer 102. The passivation layer 20 is provided with at least one via 103, and the metal patterned layer 101 and the transparent conductive patterned layer 102 are electrically connected to each other through the at least one via in the passivation layer 20.

It is noted that the display substrate 01 as shown in FIG. 2A and FIG. 2B serve only as one illustrating embodiment and does not impose a limitation to the scope of the disclosure. There are other embodiments based on practical needs.

According to some embodiments of the present disclosure, an insulating layer other than the passivation layer 20 in the embodiment as illustrated in FIG. 2A and FIG. 2B can be arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101. Herein the insulating layer can be an interlayer insulating layer or a gate insulating layer.

Similar to the embodiment as illustrated in FIG. 2A and FIG. 2B, the transparent conductive patterned layer 102 and the metal patterned layer 101 in these embodiments can be electrically connected through at least one via that is arranged in the insulating layer.

In some embodiments of the display substrate, a gate insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101, and the transparent conductive patterned layer 102 and the metal patterned layer 101 are electrically connected through at least one via arranged in the gate insulating layer.

In yet some other embodiments of the display substrate, an interlayer insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101, and the transparent conductive patterned layer 102 and the metal patterned layer 101 are electrically connected through at least one via arranged in the interlayer insulating layer.

It is possible that more than one insulating layers are disposed between the transparent conductive patterned layer 102 and the metal patterned layer 101, with at least one vias arranged to run through the more than one insulating layers to thereby allow an electric connection between the transparent conductive patterned layer 102 and the metal patterned layer 101. Herein each of the more than one insulating layers can be selected from a passivation layer 20, a gate insulating layer, and an interlayer insulating layer.

It is further noted that regardless of the employment of one or more of a passivation layer 20, a gate insulating layer, or an interlayer insulating layer that are disposed between the transparent conductive patterned layer 102 and the metal patterned layer 101 in the display substrate, each of the passivation layer 20, the gate insulating layer, and the interlayer insulating layer is essentially an insulating layer which is formed by coating over the substrate 50.

As such, in the manufacturing of the display substrate, the at least one via that runs through one or more insulating layers to thereby provide a means for electrically connecting the transparent conductive patterned layer 102 and the metal patterned layer 101 in the display substrate can be formed through one or more patterning processes over each of the one or more insulating layers.

In any of the embodiments of the display substrate 01 as described above, by configuring a protruding portion 60 between a conductive adhesive coating portion 10 and one wiring 40 that is closest thereto (i.e. the wiring 40 that is closest to the conductive adhesive coating portion 10), because of the block by the protruding portion 60, it is difficult for the conductive adhesive 30 to spread to the wiring region (i.e., a region on the display substrate having the at least one wire 40) in the proximity of the conductive adhesive coating portion 10 when the conductive adhesive 30 is applied onto the conductive adhesive coating portion 10 in a conductive adhesive coating process.

As such, the above mentioned issue of short circuiting among the conductive adhesive coating portion 10 and the at least one wiring 40 in the wiring region in the proximity of the conductive adhesive coating portion 10 can be effectively avoided.

FIG. 3A illustrates a non-display area of a display substrate according to a second embodiment of the present disclosure. As illustrated in FIG. 3A, the non-display area of this second embodiment of the display substrate is further provided with a depression 70, which is arranged between each conductive adhesive coating portion 10 and a protruding portion 60 corresponding thereto (i.e. the protruding portion 60 closest to the each conductive adhesive coating portion 10). The depression 70 is configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate 50 than an upper surface of the each conductive adhesive coating portion 10.

Herein the bottom surface of the depression 70 is referred to as a surface thereof that is closest to the upper surface of the substrate 50, which can also be considered as a bottom surface of the depression 70, and the upper surface of the substrate 50 has been defined above whose description is skipped.

It is noted that the depression 70 can be a groove structure formed on a surface of the display substrate, or can be substantially a gap between two portions, such as between the each conductive adhesive coating portion 10 and a protruding portion 60 that are formed on the upper surface of the substrate 50.

As shown in FIG. 3B, if rupture and/or perforation occurs in the passivation layer 20 after the conductive adhesive coating process, because of the relatively large distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, it increases the level of difficulty for the conductive adhesive 30 to go beyond the protruding portion 60 to thereby electrically connect with the at least one wiring 40 through the ruptures and/or the perforations in the passivation layer 20.

It is noted that the display substrate as shown in FIG. 3A and FIG. 3B, wherein each conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, and the metal patterned layer 101 and the transparent conductive patterned layer 102 are electrically connected through the vias in the passivation layer 20, serve only as an illustrating embodiment and does not impose a limitation to the scope of the disclosure. Other embodiments that are based on practical needs are also possible.

In the embodiments of the display substrate 01 as described above and illustrated in FIG. 3A and FIG. 3B, a depression 70 and a protruding portion 60 are arranged between each conductive adhesive coating portion 10 and one wiring 40 that is closest to the each conductive adhesive coating portion 10, with the depression 70 arranged between the each conductive adhesive coating portion 10 and the protruding portion 60. As such, it is substantially configured such that a depression 70 and a protrusion are arranged between the each conductive adhesive coating portion 10 and the one wiring 40 that is closest to the each conductive adhesive coating portion 10.

Because of the relatively large distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, compared with the embodiments of the display substrate 01 where only a protruding portion 60 is arranged between each conductive adhesive coating portion 10 and one wiring 40 that is closest to the each conductive adhesive coating portion 10, it further increases the level of difficulty for the conductive adhesive 30 to go beyond the protruding portion 60 to electrically connect with the at least one wiring 40 through the ruptures and/or the perforations in the passivation layer 20.

FIG. 4A is a schematic diagram of a display area of a display substrate according to a third embodiments of the present disclosure. As illustrated in FIG. 4A, this third embodiment of the display substrate 01 can further comprise a thin-film transistor 80 and a pixel electrode 90, disposed over the substrate 50 and in a display area of the display substrate 01. The thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804, and a drain electrode 805.

On the above basis, the protruding portion 60 can comprise more than one patterned layers according to some embodiments of the present disclosure. In these embodiments, one or more of the patterned layers in the protruding portion 60 can be configured to be at a substantially same layer as the gate electrode 801, and/or the active layer 803, and/or the source electrode 804 and a drain electrode 805, and/or the pixel electrode 90.

As such, because one or more of the patterned layers in the protruding portion 60 and one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 are at substantially same layer(s), during the manufacturing process, at least the one or more of the patterned layers in the protruding portion 60 can be formed at the same time when the one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 that are at the same layer(s) are fabricated. Therefore, it leads to a simplified manufacturing process for the display substrate and the display panel containing the display substrate as disclosed herein.

It is further noted that one or more of the patterned layers in the protruding portion 60 and one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 that are at substantially same layer(s) can have a substantially same composition, which can lead to an even more simplified manufacturing process.

Among the various patterned layers in the thin-film transistor 80, the gate insulating layer 802 is formed by coating over the substrate 50, thus the gate insulating layer 802 can be retained in the protruding portion 60. As such, the gate insulating layer 802 can constitute one patterned layer in the protruding portion 60.

On this above basis, the protruding portion 60 can further include a first patterned layer that is at a substantially same layer as the gate electrode 801, and/or a second patterned layer that is at a substantially same layer as the active layer 803, and/or a third patterned layer that is at a substantially same layer as the source electrode 804 and the drain electrode 805, and/or a fourth patterned layer that is at a substantially same layer as the pixel electrode 90.

Additionally, an interlayer insulating layer can be formed by coating over the substrate 50 during the formation of the thin-film transistor 80 and the pixel electrode 90, thus the protruding portion 60 can further include an interlayer insulating layer. Herein there is no limitation to the position of the interlayer insulating layer, which can be arranged between any two electrodes to be insulated based on practical needs.

As illustrated in FIG. 4A, the display substrate 01 further comprises a thin-film transistor 80 and a pixel electrode 90, which are consecutively disposed in a display area over the substrate 50. The thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804 and a drain electrode 805, which are consecutively disposed over the substrate 50. The drain electrode 805 is electrically connected with a pixel electrode 90 through vias in an interlayer insulating layer 100. The gate insulating layer 802 and the interlayer insulating layer 100 are both configured to coat over the substrate 50.

On the above structural basis of the thin-film transistor 80 and a pixel electrode 90 as shown in FIG. 4A, the protruding portion 60 further comprises, in addition to the gate insulating layer 802 and the interlayer insulating layer 100, a first patterned layer 601 that is at a substantially same layer as the gate electrode 801, a second patterned layer 602 that is at a substantially same layer as the active layer 803, a third patterned layer 603 that is at a substantially same layer as the source electrode 804 and the drain electrode 805, and a fourth patterned layer 604 that is at a substantially same layer as the pixel electrode 90, as illustrated in FIG. 4B.

Further as illustrated in FIG. 4B, the conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, wherein the metal patterned layer 101 is at a substantially same layer as the source electrode 804 and the drain electrode 805, as well as the third patterned layer 603 in the protruding portion 60. The transparent conductive patterned layer 102 is at a substantially same layer as the pixel electrode 90, as well as the fourth patterned layer 604 in the protruding portion 60.

Further as illustrated in FIG. 4B, a wiring 40 is at a substantially same layer as the source electrode 804 and the drain electrode 805, as the third patterned layer 603 in the protruding portion 60, and as the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10.

It is noted that there is no limitation to the type of the thin-film transistor 80, which can be an amorphous silicon thin-film transistor, a metal oxide thin-film transistor, a polycrystalline silicon thin-film transistor, or an organic thin-film transistor, etc.

In addition, there is no limitation to the configuration of the film transistor 80, which can be of a bottom-gate type or can be of a top-gate type. Only a bottom-gate thin-film transistor is shown in FIG. 4A as an illustrated example.

In the embodiments of the display substrate 01 as described above and illustrated in FIG. 4A and FIG. 4B, because one or more of the patterned layers in the protruding portion 60, one or more patterned layers in the conductive adhesive coating portion 10, and one or more patterned layers in the thin-film transistor 80 and the pixel electrode 90 are all at substantially same layer(s), these one or more patterned layers can be formed at the same time through a one-time patterning process.

FIG. 5A is a schematic diagram of a display area of a display substrate according to a fourth embodiment of the present disclosure. As illustrated in FIG. 5A, in addition to a thin-film transistor 80 and a pixel electrode 90, this fourth embodiment of the display substrate 01 can further include at least one common electrode 110 and a passivation layer 20.

On the above basis, the protruding portion 60 can include a plurality of patterned layers, wherein one or more of the plurality of patterned layers are configured to be at a substantially same layer as the gate electrode 801, the active layer 803, the source electrode 804 and the drain electrode 805, the pixel electrode 90, or the at least one common electrode 110.

As such, during the formation of the thin-film transistor 80, the pixel electrode 90, the common electrode 110, and the passivation layer 20, one or more of the plurality of patterned layers in the protruding portion 60 can be formed at the same time by least one one-time patterning process.

In the embodiments of the display substrate 01 as described above, because the gate insulating layer 802 of the thin-film transistor and the passivation layer 20 are formed by coating over the substrate 50, the gate insulating layer 802 and the passivation layer 20 can be retained in the protruding portion 60. As such, the gate insulating layer 802 and the passivation layer 20 can constitute two patterned layers in the protruding portion 60.

On the above basis, the protruding portion 60 can further include at least one of a first patterned layer 601 that is at a substantially same layer as the gate electrode 801, a second patterned layer 602 that is at a substantially same layer as the active layer 803, a third patterned layer 603 that is at a substantially same layer as the source electrode 804 and the drain electrode 805, a fourth patterned layer 604 that is at a substantially same layer as the pixel electrode 90, or a fifth patterned layer 605 that is at a substantially same layer as the at least one common electrode 110.

In the embodiments of the display substrate 01 as illustrated in FIG. 5A, the display substrate 01 comprises a thin-film transistor 80, a pixel electrode 90, a passivation layer 20, and at least one common electrode 110, which are consecutively disposed over the substrate 50 in a display area.

The thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804 and a drain electrode 805, which are consecutively disposed over the substrate 50. The pixel electrode 90 is disposed at a lateral side of the drain electrode 805 that is close to the substrate 50, and the pixel electrode 90 is directly in contact with the drain electrode 805.

The passivation layer 20 and the common electrodes 110 are disposed over a top surface of the source electrode 804 and the drain electrode 805 that is far away from the substrate 50. The gate insulating layer 802 and the passivation layer 20 are disposed to coat over the whole substrate 50.

In the embodiments as illustrated in FIG. 5B, in addition to the gate insulating layer 802 and the passivation layer 20, the protruding portion 60 further includes a first patterned layer 601 that is at a substantially same layer as the gate electrode 801, a second patterned layer 602 that is at a substantially same layer as the active layer 803, a third patterned layer 603 that is at a substantially same layer as the source electrode 804 and the drain electrode 805, a fourth patterned layer 604 that is at a substantially same layer as the pixel electrode 90, and a fifth patterned layer 605 that is at a substantially same layer as the common electrode 110.

Further as illustrated in FIG. 5B, a conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, wherein the metal patterned layer 101 is at a substantially same layer as the source electrode 804 and the drain electrode 805, and as well as the third patterned layer 603 in the protruding portion 60. The transparent conductive patterned layer 102 is at a substantially same layer as the common electrode 110 and the fifth patterned layer 605 in the protruding portion 60.

Further as illustrated in FIG. 5B, a wiring 40 is at a substantially same layer as the source electrode 804 and the drain electrode 805 in the thin-film transistor 80, as the third patterned layer 603 in the protruding portion 60, and as the metal patterned layer 101 in the conductive adhesive coating portion 10.

The configurations as mentioned above and illustrated in FIGS. 4A, 4B, 5A, and 5B can avoid the addition of extra patterning processes and can increase the height of the protruding portion 60. In one specific embodiment as an illustrating example, the protruding portion 60 having one of the above mentioned configurations can have a height difference of more than 1.9 μm between the protruding portion 60 and the conductive adhesive coating portions 10. Herein the height difference between the protruding portion 60 and the conductive adhesive coating portions 10 is referred to as a distance between an upper surface of the protruding portion 60 and an upper surface of the conductive adhesive coating portion 10.

It is noted that the metal patterned layer 101 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801. Alternatively, the metal patterned layer 101 can include two sub-layers, with a first sub-layer at a substantially same layer as the source electrode 804 and the drain electrode 805, and with a second sub-layer at a substantially same layer as the gate electrode 801.

It is further noted that the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the common electrode 110, or can be configured to be at a substantially same layer as the pixel electrode 90. Alternatively, the transparent conductive patterned layer 102 can include two sub-layers, with one sub-layer at a substantially same layer as the common electrode 110, and with another sub-layer at a substantially same layer as the pixel electrode 90.

It is further noted that the at least one wiring 40 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801. Alternatively, each wiring 40 can include two layers, with one layer at a substantially same layer as the source electrode 804 and the drain electrode 805, and with another layer at a substantially same layer as the gate electrode 801.

FIG. 6A and FIG. 6B illustrated a non-display area of a fifth embodiment and a sixth embodiment of the display substrate, respectively.

According to the fifth embodiment of the display substrate 01 as shown in FIG. 6A, the depression 70 can be configured such that a bottom surface (i.e., a bottom surface) thereof is at a substantially same plane as an upper surface of the gate insulating layer 802.

According to the sixth embodiment of the display substrate 01 as shown in FIG. 6B, the depression 70 can be configured such that a bottom surface (i.e., a bottom surface) thereof is at a substantially same plane as an upper surface of the substrate 50.

In other words, in the above two embodiments of the display substrate 01, it is substantially configured such that the upper surface of the gate insulating layer 802 (shown in FIG. 6A) or the substrate 50 (shown in FIG. 6B) can be exposed at the site for the depression 70 to thereby form the depression 70.

In one specific embodiment as an illustrating example, the depression 70 is configured to have the upper surface of the substrate 50 exposed (as illustrated in FIG. 6B), and such a configuration can realize a distance of about 0.8 μm between the bottom surface of the depression 70 and the upper surface of the conductive adhesive coating portions 10.

Such a configuration substantially further increases the distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, which in turn can result in a better effect in blocking the conductive adhesive 30 from spreading to the wiring region (i.e., the region having the at least one wirings 40) after the conductive adhesive coating process.

The present disclosure further provides a display substrate 01 according to a seventh embodiment. As shown in FIG. 7A, this seventh embodiment of the display substrate 01 includes a substrate 50, at least one conductive adhesive coating portion 10, and at least one wiring 40. The at least one conductive adhesive coating portion 10 and the at least one wiring 40 are disposed over the substrate 50.

Each of the at least one conductive adhesive coating portion 10 comprises a metal patterned layer 101 and a transparent conductive patterned layer 102, wherein the transparent conductive patterned layer 102 is disposed over a side of the metal patterned layer 101 that is farther away from the substrate 50 (i.e., the metal patterned layer 101 is between the substrate 50 and the transparent conductive patterned layer 102).

As illustrated in FIG. 7A and FIG. 8, the metal patterned layer 101 is configured to include a at least one first opening 1011. The at least one first opening 1011 take a shape of strips and are spaced apart from one another, and are configured such that each opening 1011 can have an extending direction substantially in parallel to one of the at least one wiring 40 that is closest thereto. In a preferred embodiment as illustrated in FIG. 8, the plurality of the first openings take a shape of straight stripes and are evenly spaced apart from one another. It is noted that at least one first opening 1011 may not be spaced apart but may be connected with each other according to some embodiments.

As shown in FIG. 7B, if rupture and/or perforation occurs in the passivation layer 20 after the conductive adhesive coating process, because the at least one first opening 1011 can allow the conductive adhesive 30 to flow along the extending direction of the at least one first opening 1011, it increases the level of difficulty for the conductive adhesive 30 to spread to the region having the at least one wirings 40 (i.e. the wiring region) to cause electrical connection with the at least one wiring 40 through the ruptures and/or the perforations in the passivation layer 20.

It is noted that the at least one first opening 1011 can take various different shapes, such as straight stripes (as shown in FIG. 8), or curved stripes, etc., and that the at least one first opening 1011 do not necessarily need to be spaced apart, and can be connected to one another at any places, as long as the presence of the at least one first opening 1011 allow the conductive adhesive 30 to flow along the extending direction of the at least one first opening 1011 during the conductive adhesive coating process.

The following are noted for the embodiments of the display substrate 01 as described above.

First, as understood by people of ordinary skill in the field, the conductive adhesive coating process is performed only when the display substrate and the encasing substrate are aligned together for encasing, when the conductive adhesive 30 is applied onto, and to thereby contact with, the at least one conductive adhesive coating portion 10. It is further noted that the at least one conductive adhesive coating portion 10 is electrically coupled to a grounding wiring on the display substrate 01.

Second, the number of the at least one conductive adhesive coating portion 10 can be configured based on a size of the display panel to which the display substrate 01 is applied. If the display panel is small, one conductive adhesive coating portion 10 can be configured; and if the display panel is relatively big, two or more conductive adhesive coating portions 10 can be configured to allow a sufficient grounding for the anti-static sub-portion on the encasing substrate.

Regardless of how many conductive adhesive coating portions 10 are configured, all of the conductive adhesive coating portions 10 are disposed in a non-display area of the substrate 50. All of the at least one wiring 40 as mentioned above are also disposed in the non-display area of the substrate 50.

Third, there are no limitations to the size, number, and shape of the at least one first opening 1011 in the conductive adhesive coating portions 10, which can be configured based on practical needs as long as the configuration allows the conductive adhesive 30 to flow along the extending direction of the at least one first opening 1011 to thereby prevent the conductive adhesive 30 from spreading to the wiring region in the proximity of the conductive adhesive coating portion 10.

Fourth, as for the display substrate 01 as shown in FIG. 7A and FIG. 7B, wherein each conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102, which are electrically connected to each other through the vias in the passivation layer 20, the display substrate 01 serves only as illustrating embodiments and do not impose a limitation to the scope of the disclosure. There are other embodiments based on practical needs.

For example, according to some embodiments of the present disclosure, in addition to the passivation layer 20, at least one insulating layer (such as an interlayer insulating layer or a gate insulating layer) can be arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101. In these embodiments, the transparent conductive patterned layer 102 and the metal patterned layer 101 can be electrically connected through vias that are configured in both the passivation layer 20 and the at least one insulating layer.

In some other embodiments of the present disclosure, a gate insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101. In these embodiments, the transparent conductive patterned layer 102 and the metal patterned layer 101 can be electrically connected through vias that are configured in the gate insulating layer.

In yet some other embodiments of the present disclosure, an interlayer insulating layer is arranged between the transparent conductive patterned layer 102 and the metal patterned layer 101. In these embodiments, the transparent conductive patterned layer 102 and the metal patterned layer 101 can be electrically connected through vias that are configured in the interlayer insulating layer.

It is noted that regardless of a passivation layer 20, a gate insulating layer, or an interlayer insulating layer that is employed in the conductive adhesive coating portion 10 of the display substrate 01, each of the passivation layer 20, the gate insulating layer, and the interlayer insulating layer is essentially and substantially an insulating layer which is formed by coating over the substrate 50.

In the following, technical details of the display substrate 01 are further described by referencing to a configuration where an insulating layer is disposed between a transparent conductive patterned layer 102 and a metal patterned layer 101.

In the aforementioned embodiment of the display substrate 01 as illustrated in FIG. 7B and FIG. 8, the metal patterned layer 101 is provided with at least one first opening 1011 that are spaced apart from one another, which substantially provide a plurality of depression 70s having an extending direction along the at least one first opening 1011 for the conductive adhesive 30 during the conductive adhesive coating process to coat the conductive adhesive 30 onto the conductive adhesive coating portion 10 of the display substrate 01 and to attach the encasing substrate with the display substrate 01 through the conductive adhesive coating portion 01 and the conductive adhesive 30.

As such, after the conductive adhesive coating process, the conductive adhesive 30 can flow along the extending direction of the plurality of depression 70s (i.e. the at least one first opening 1011). In addition, the at least one first opening 1011 is further configured to have the extending direction in parallel to the wirings 40 that are close thereto, which can effectively prevent the conductive adhesive 30 from spreading to the nearby wiring region. Due to these above features, the issue of short circuiting between the conductive adhesive 30 and the wirings 40 that are close thereto can be effectively avoided.

FIG. 9 is a schematic diagram of a non-display area of a display substrate according to an eighth embodiment of the present disclosure. As illustrated in FIG. 9, an insulating layer 120 is sandwiched between the metal patterned layer 101 and the transparent conductive patterned layer 102, and the insulating layer 120 is provided with at least one second opening 1201, which are spaced apart and can take a shape of strips. Similar to the at least one first opening 1101, the at least one second opening may not be spaced apart and may be connected to each other.

The at least one second opening 1201 correspond to the at least one first opening 1101 in a one-to-one relationship, and are configured such that an orthographic projection of the at least one second opening 1201 on the substrate 50 overlaps with an orthographic projection of the at least one first opening 1101 on the substrate 50.

Because the orthographic projection of the at least one second opening 1201 on the substrate 50 and the orthographic projection of the at least one first opening 1101 on the substrate 50 overlap with one another, thus the transparent conductive patterned layer 102 can be electrically connected to the metal patterned layer 101 through the overlapped second openings 1201 and first openings 1101.

Herein the insulating layer 120 can be a passivation layer, a gate insulating layer, or an interlayer insulating layer, depending on the specific design and actual manufacturing process.

In the above-mentioned embodiments of the display substrate 01, at least one second opening 1201 are further configured in the insulating layer 120 at sites of each conductive adhesive coating portion 10. The at least one second opening 1201 correspond to the at least one first opening 1101 in the metal patterned layer 101 in a one-to-one relationship, and are further configured to have their orthographic projection on the substrate 50 overlap with the orthographic projection of the at least one first opening 1101 on the substrate 50.

As such, the depression 70s formed by both the second openings 1201 in the insulating layer 120 and the first openings 1101 in the metal patterned layer 101 can be relatively deep, which further ensures that the conductive adhesive 30 can only flow along the extending direction of the depression 70s (i.e. substantially the extending direction of the first openings 1101 and the second openings 1201), thereby effectively preventing the conductive adhesive 30 from spreading to the nearby wiring regions (i.e., regions having the wirings 40).

According to a ninth embodiment of the display substrate 01 as illustrated in FIG. 10, a protruding portion 60 is disposed between each conductive adhesive coating portion 10 and one of the at least one wiring 40 that is closest to the each conductive adhesive coating portion 10.

The protruding portion 60 is configured to have a larger height than the each conductive adhesive coating portion 10 (i.e. a distance from the upper surface of the protruding portion 60 to the upper surface of the substrate 50 is configured to be larger than a distance from the upper surface of the each conductive adhesive coating portion 10 to the upper surface of the substrate 50). The protruding portion 60 is configured to block the conductive adhesive 30 from spreading to a region having wiring 40.

Herein the structure of the protruding portion 60 can be referenced to the above description.

In the display substrate 01 as described above, by configuring a protruding portion 60 between each conductive adhesive coating portion 10 and one wiring 40 that is closest thereto, it increases the difficulty for the conductive adhesive 30 to spread to the region having the at least one wire 40 after being applied in the conductive adhesive coating process because of a block by the protruding portion 60. As such, the issue of short circuiting between the at least one conductive adhesive coating portion 10 and the at least one wiring 40 in a region in the proximity of the at least one conductive adhesive coating portion 10 can be effectively avoided.

Furthermore, according to a tenth embodiment of the display substrate as illustrated in FIG. 11, the display substrate is further provided with a depression 70 (i.e. a depressing structure), which is arranged between each conductive adhesive coating portion 10 and its corresponding protruding portion 60. The depression 70 is configured such that a bottom surface thereof has a shorter distance to the upper surface of the substrate 50 than an upper surface of each conductive adhesive coating portion 10.

In some preferred embodiments, the bottom surface of the depression 70 and the upper surface of the substrate 50 are at a substantially same plane.

In the tenth embodiments of the display substrate 01 as described above and illustrated in FIG. 11, a depression 70 and a protruding portion 60 are arranged between each conductive adhesive coating portion 10 and one wiring 40 that is closest to the each conductive adhesive coating portion 10, configured such that the depression 70 is between the each conductive adhesive coating portion 10 and the protruding portion 60. This is substantially equivalent to the configuration of a depression 70 and a bulge between the each conductive adhesive coating portion 10 and the one wiring 40 that is closest to the each conductive adhesive coating portion 10.

Because of the relatively large distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, it further increases the level of difficulty for the conductive adhesive 30 to go beyond the protruding portion 60 to spread to the region having the wirings 40.

It is of note that the embodiments shown in FIG. 10 and FIG. 11 are illustrated with the passivation layer 20 as the insulating layer 120. The insulating layer 120 can also be a gate insulating layer, or an interlayer insulating layer, depending on the specific design and actual manufacturing process.

As for the metal patterned layer 101, it can be at a substantially same layer as at least one of the gate electrode 801, or the source electrode 804 and the drain electrode 805. As for the transparent conductive patterned layer 102, it can be at a substantially same layer as at least one of the common electrode 110, or the pixel electrode 90. As for the at least one wiring 40, each can be at a substantially same layer as at least one of the gate electrode 801, or the source electrode 804 and the drain electrode 805.

Specifically, the metal patterned layer 101 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801. Alternatively, the metal patterned layer 101 can include two layers, with one layer at a substantially same layer as the source electrode 804 and the drain electrode 805 and another layer at a substantially same layer as the gate electrode 801.

Specifically, the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10 can be configured to be at a substantially same layer as the common electrode 110, or can be configured to be at a substantially same layer as the pixel electrode 90. Alternatively, the transparent conductive patterned layer 102 can include two layers, with one layer at a substantially same layer as the common electrode 110 and another layer at a substantially same layer as the pixel electrode 90.

Specifically, the at least one wiring 40 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or configured to be at a substantially same layer as the gate electrode 801. Alternatively, each wiring 40 can include two layers, with one layer at a substantially same layer as the source electrode 804 and the drain electrode 805 and another layer at a substantially same layer as the gate electrode 801.

In another aspect, the disclosure further provides a display panel. As shown in FIG. 12, the display panel includes a display substrate 01 as described above, and an encasing substrate 02. The encasing substrate 02 is provided with a coupling portion (not shown in the drawings), which is electrically connected with at least one conductive adhesive coating portion 10 arranged on the display substrate 01 via the conductive adhesive 30. Herein the coupling portion can include an anti-static sub-portion, which configured to collect and guide out the static electricity that is accumulated in the encasing substrate, but can also include another sub-portion having another functionality.

As for a vehicle-mounted display panel, the environment where the vehicle-mounted display panel is used can easily cause the insulating layer 120 (e.g. the passivation layer 20) that is sandwiched between the metal patterned layer 101 and the transparent conductive patterned layer 102 to subject to ruptures and perforations. Thus according to some embodiments of the present disclosure, the display panel can be a vehicle-mounted display panel.

The display panel as described above has substantially same advantages or favored features as the aforementioned display substrate, which have been detailed above and will not be repeated herein.

According to some embodiments as illustrated in FIG. 12, there are two conductive adhesive coating portions 10, which are disposed at the two ends of the diagonal line of the display substrate 01.

On the one hand, configuration of two conductive adhesive coating portions 10 can guarantee a relatively high anti-static efficiency, whereas the difficulty in arranging the wirings in the display substrate 01 is not increased, compared with a configuration of more than two conductive adhesive coating portions 10. On the other hand, if one conductive adhesive coating portion 10 cannot exert its anti-static function due to some issues, the other conductive adhesive coating portion 10 can still work to exert its anti-static function, thereby resulting in an increased reliability for the display panel.

According to some embodiments, the coupling portion in the encasing substrate 02 can be a transparent conductive film, which is disposed on a side of the encasing substrate 02 that is relatively farther away from the display substrate 01.

As such, there is no need to alter current manufacturing process of the encasing substrate 02 (i.e. a current manufacturing process can still be applied to manufacture the encasing substrate 02), and the process of fabricating the transparent conductive film is relatively simple.

In yet another aspect, the present disclosure provides a method for manufacturing a display substrate. The method includes the steps of:

Providing a substrate; and

Forming at least one conductive adhesive coating portion 10, at least one wiring 40, and at least one protruding portion 60 over a substrate 50, such that one protruding portion 60 is disposed between each conductive adhesive coating portion 10 and one wiring that is closest to the each conductive adhesive coating portion 10.

Herein, it is configured such that a distance of an upper surface of the one protruding portion 60 to an upper surface of the substrate 50 is larger than a distance of an upper surface of the each conductive adhesive coating portion 10 to the upper surface of the substrate 50. Each of the at least one protruding portion 60 is configured to block a conductive adhesive 30 from spreading to a region containing the at least one wiring 40.

As illustrated in FIG. 4A, a thin-film transistor 80 comprises a gate electrode 801, a gate insulating layer 802, an active layer 803, a source electrode 804 and a drain electrode 805, which are consecutively disposed over the substrate 50. The drain electrode 805 is electrically connected with a pixel electrode 90 through at least one via arranged in an interlayer insulating layer 100. The gate insulating layer 802 and the interlayer insulating layer 100 are configured to be coated onto the whole upper surface of the substrate 50.

Each protruding portion 60 can include a plurality of patterned layers, and one or more of the plurality of patterned layers in each protruding portion 60 can be configured to be formed through a one-time patterning process with one or more of the gate electrode 801, the active layer 803, the source electrode 804 and the drain electrode 805, or the pixel electrode 90 in the thin-film transistor 80.

As such, as illustrated in FIG. 4B, in addition to the gate insulating layer 802 and the interlayer insulating layer 100, the protruding portion 60 can further include a first patterned layer 601 that is formed by a substantially same patterning process as the gate electrode 801, a second patterned layer 602 that is formed by a substantially same patterning process as the active layer 803, a third patterned layer 603 that is formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, a fourth patterned layer 604 that is formed by a substantially same patterning process as the pixel electrode 90.

As mentioned above in some embodiments of the display substrate, each of the at least one conductive adhesive coating portion 10 includes a metal patterned layer 101 and a transparent conductive patterned layer 102. Therefore, according to some embodiments of the method, the metal patterned layer 101 is formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805; the transparent conductive patterned layer 102 is formed by a substantially same patterning process as the pixel electrode 90; and each of the at least one wiring 40 is formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805 of each thin-film transistor 80.

As has been noted for the metal patterned layer 101 in the conductive adhesive coating portion 10, the metal patterned layer 101 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or can be configured to be at a substantially same layer as the gate electrode 801, or alternatively can include two sub-layers, with a first sub-layer at a substantially same layer as the source electrode 804 and the drain electrode 805 and as a second sub-layer at a substantially same layer as the gate electrode 801.

As such, when forming the at least one conductive adhesive coating portion 10, the metal patterned layer 101 can be formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, or as the gate electrode 801, or alternatively, by forming the first sub-layer via a substantially same patterning process as the source electrode 804 and the drain electrode 805, and forming the second sub-layer via a substantially same patterning process as the gate electrode 801.

As also has been noted for the transparent conductive patterned layer 102 in the conductive adhesive coating portion 10, the transparent conductive patterned layer 102 can be configured to be at a substantially same layer as the common electrode 110, or can be configured to be at a substantially same layer as the pixel electrode 90, or alternatively can include two sub-layers, with one sub-layer at a substantially same layer as the common electrode 110, and with another sub-layer at a substantially same layer as the pixel electrode 90.

As such, when forming the at least one conductive adhesive coating portion 10, the transparent conductive patterned layer 102 can be formed by a substantially same patterning process as the common electrode 110, or as the pixel electrode 90, or alternatively, by forming the one sub-layer via a substantially same patterning process as the common electrode 110, and forming the another sub-layer via a substantially same patterning process as the pixel electrode 90.

As also has been noted for the at least one wiring 40, each of the at least one wiring 40 can be configured to be at a substantially same layer as the source electrode 804 and the drain electrode 805, or can be configured to be at a substantially same layer as the gate electrode 801, or alternatively can include two sub-layers, with one sub-layer at a substantially same layer as the source electrode 804 and the drain electrode 805, and with another sub-layer at a substantially same layer as the gate electrode 801.

As such, when forming the at least one wiring 40, the metal patterned layer 101 can be formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, or as the gate electrode 801, or alternatively, by forming the one sub-layer via a substantially same patterning process as the source electrode 804 and the drain electrode 805, and forming the another sub-layer via a substantially same patterning process as the gate electrode 801.

According to some embodiments as illustrated in FIG. 5A, the method for manufacturing a display substrate further includes:

Forming at least one common electrode 110 and a passivation layer 20.

As such, the protruding portion 60 can include a plurality of patterned layers, and it is configured such that one or more of the plurality of patterned layers in the protruding portion 60 are configured to be formed by a substantially same patterning process as the gate electrode 801, the active layer 803, the source electrode 804 and the drain electrode 805, the pixel electrode 90, or the at least one common electrode 110.

In the display substrate 01 as described above, because the gate insulating layer 802 of the thin-film transistor and the passivation layer 20 are coated over the whole upper surface of the substrate 50, the protruding portion 60 can further include the gate insulating layer 802 and the passivation layer 20.

In the embodiments of the display substrate as illustrated in FIG. 5B, the protruding portion 60 includes a first patterned layer 601, a second patterned layer 602, a third patterned layer 603, a fourth patterned layer 604, and a fifth patterned layer 605.

In the method for manufacturing the display substrate as illustrated in FIG. 5B, the first patterned layer 601 can be formed by a substantially same patterning process as the gate electrode 801, the second patterned layer 602 can be formed by a substantially same patterning process as the active layer 803, the third patterned layer 603 can be formed by a substantially same patterning process as the source electrode 804 and the drain electrode 805, the fourth patterned layer 604 can be formed by a substantially same patterning process as the pixel electrode 90, and the fifth patterned layer 605 can be formed by a substantially same patterning process as the at least one common electrode 110.

As such, there is no need to add extra patterning processes in the manufacturing of the display substrate, and the height of the protruding portion 60 can be increased as well (In one illustrating example, the protruding portion 60 having the above mentioned configuration can have a height difference of more than 1.9 μm between the protruding portion 60 and the conductive adhesive coating portions 10).

In some embodiments of the display substrate as illustrated in FIG. 6A and FIG. 6B, there is a depression 70 between each conductive adhesive coating portion 10 and a corresponding protruding portion 60 (i.e., the protruding portion 60 that is configured between the each conductive adhesive coating portion 10 and the wiring 40 that is closest thereto).

As such, according to some embodiments of the disclosure, the method can further include:

Forming a depression 70 between each conductive adhesive coating portion 10 and a corresponding protruding portion 60.

Herein the depression 70 can be configured such that a bottom surface thereof is at a substantially same plane as an upper surface of the gate insulating layer 802, as shown in FIG. 6A, or that the bottom surface thereof is at a substantially same plane as an upper surface of the substrate 50, as illustrated in FIG. 6B. In other words, in the above two embodiments of the display substrate 01, it is substantially configured such that the upper surface of the gate insulating layer 802 (shown in FIG. 6A) or the substrate 50 (shown in FIG. 6B) can be exposed at the site for the depression 70 to thereby form the depression 70.

In one specific embodiment, the depression 70 is configured to have the upper surface of the substrate 50 exposed (as illustrated in FIG. 6B), and such a configuration can realize a distance of about 0.8 μm between the bottom surface of the depression 70 and the upper surface of the conductive adhesive coating portions 10. Such a configuration substantially further increases the distance between the upper surface of the protruding portion 60 and the bottom surface of the depression 70, which in turn can result in a better effect in blocking the conductive adhesive 30 from spreading to the wiring region after the conductive adhesive coating process.

There is no limitation to the type of the thin-film transistor 80, which can be an amorphous silicon thin-film transistor, a metal oxide thin-film transistor, a polycrystalline silicon thin-film transistor, or an organic thin-film transistor, etc. In addition, there is no limitation to the configuration of the film transistor 80, which can be of a bottom-gate type or can be of a top-gate type. Only a bottom-gate thin-film transistor is shown in FIG. 4A as an illustrated example.

In the method for manufacturing a display substrate as described above, by configuring a protruding portion 60 between each conductive adhesive coating portion 10 and one wiring 40 that is closest thereto, it increases the difficulty for the conductive adhesive 30 to spread to the wiring region (i.e. the region having the at least one wire 40) after being applied in a conductive adhesive coating process because of the block by the protruding portion 60. As such, the issue of short circuiting between the at least one conductive adhesive coating portion 10 and the at least one wiring 40 in a region in the proximity of the at least one conductive adhesive coating portion 10 can be effectively avoided.

Additionally, because the protruding portions 60 can be formed at the same time when each thin-film transistor 80 and each pixel electrode 90 are fabricated, the number of patterning processes for the whole manufacturing process of the display substrate do not need to be increased.

Although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise.

Various modifications of, and equivalent acts corresponding to, the disclosed aspects of the exemplary embodiments, in addition to those described above, can be made by a person of ordinary skill in the art, having the benefit of the present disclosure, without departing from the spirit and scope of the disclosure defined in the following claims, the scope of which is to be accorded the broadest interpretation so as to encompass such modifications and equivalent structures.

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL

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