The present disclosure relates to the field of display technology, in particular to a display substrate, a method for manufacturing display substrate, a display panel and a display device.
With the advent of full-screen mobile phones, extensive research has been done into in-screen fingerprint identification. In the related art, a pinhole imaging principle is used for the in-screen fingerprint identification. At an active display area, pinholes are provided as imaging pinholes at regular intervals in pixels (a diameter of each imaging pinhole is usually greater than or equal to 5 μm and smaller than or equal to 15 μm), and a metal layer is deposited as a light-shielding layer at the active display area other than positions where the imaging pinholes are formed. However, in the related art, there is still room for improvement in an imaging effect of the fingerprint identification using the pinhole imaging principle.
In one aspect, the present disclosure provides in some embodiments a display substrate, including a base substrate, and a light-shielding layer and a Thin Film Transistor (TFT) array layer arranged sequentially on the base substrate. A plurality of imaging pinholes is formed in the light-shielding layer. A first protection layer is arranged between the light-shielding layer and the TFT array layer. The base substrate is provided with a first region, an orthogonal projection of a metal film layer of the TFT array layer onto the base substrate is located outside the first region, and at least a part of an orthogonal projection of the imaging pinhole onto the base substrate is located within the first region. An orthogonal projection of the first protection layer onto the base substrate at least covers a part of the first region. The first region includes a pinhole region, and at least a part of the orthogonal projection of the imaging pinhole onto the base substrate is located within the pinhole region. The orthogonal projection of the first protection layer onto the base substrate at least covers the pinhole region. The display substrate further includes a buffer layer arranged between the first protection layer and the TFT array layer.
In a possible embodiment of the present disclosure, the first region includes a first sub-region. The TFT array layer includes a resetting power source line, a first resetting transistor, a threshold compensation transistor and a driving transistor. The first sub-region does not overlap an orthogonal projection of a first conductive member included in a semiconductor material layer pattern of the first resetting transistor onto the base substrate and an orthogonal projection of a second conductive member included in a semiconductor material layer pattern of the threshold compensation transistor onto the base substrate. The first conductive member is electrically connected to a first electrode of the first resetting transistor, and the first electrode is electrically connected to the resetting power source line. The second conductive member is electrically connected to a second electrode of the threshold compensation transistor, and the second electrode is electrically connected to a gate electrode of the driving transistor.
In a possible embodiment of the present disclosure, the first region includes a second sub-region, and the TFT array layer includes a gate line, a threshold compression transistor and a driving transistor. The second sub-region does not overlap an orthogonal projection of the gate line onto the base substrate, an orthogonal projection of a second electrode of the threshold compensation transistor onto the base substrate, an orthogonal projection of a second conductive member included in a semiconductor material layer pattern of the threshold compensation transistor onto the base substrate, and an orthogonal projection of a first gate metal pattern onto the base substrate. The second conductive member is electrically connected to the second electrode of the threshold compensation transistor, and the second electrode is electrically connected to a gate electrode of the driving transistor. The first gate metal pattern is a gate metal pattern arranged between the gate line included in a first gate metal layer of the TFT array layer and the gate electrode of the threshold compensation transistor.
In a possible embodiment of the present disclosure, the first region includes a third sub-region, and the TFT array layer includes a gate line, a threshold compensation transistor and a driving transistor. The third sub-region is among an orthogonal protection of the gate line onto the base substrate, an orthogonal projection of a third conductive member included in a semiconductor material layer pattern of the threshold compensation transistor onto the base substrate, and an orthogonal projection of a first gate metal pattern onto the base substrate. The semiconductor material layer pattern of the threshold compensation transistor includes a first channel member and a second channel member, and the third conductive member does not overlap the first channel member and the second channel member. The first gate metal pattern is a gate metal pattern arranged between the gate line included in the first gate metal layer of the TFT array layer and a gate electrode of the threshold compensation transistor.
In a possible embodiment of the present disclosure, the first region includes a fourth sub-region, and the TFT array layer includes a gate line, a first capacitor, a threshold compensation transistor and a first light-emission control transistor. The fourth sub-region does not overlap an orthogonal projection of the gate line onto the base substrate, an orthogonal projection of a first electrode plate of the first capacitor onto the base substrate, an orthogonal projection of a second electrode of the threshold compensation transistor onto the base substrate, and an orthogonal projection of a fourth conductive member included in a semiconductor material layer pattern of the first light-emission control transistor onto the base substrate. A semiconductor material layer pattern of the threshold compensation transistor includes a first channel member and a second channel member, and the semiconductor material layer pattern of the first light-emission control transistor includes a third channel member. The fourth conductive member is arranged between the second channel member and the third channel member.
In a possible embodiment of the present disclosure, the first region includes a fifth sub-region, and the TFT array layer includes a first capacitor, a threshold compensation transistor, a first light-emission control transistor, a first power source line and a light-emission control signal line. The fifth sub-region does not overlap an orthogonal projection of a first electrode plate of the first capacitor onto the base substrate, an orthogonal projection of the light-emission control signal line onto the base substrate, an orthogonal projection of the first power source line onto the base substrate, and an orthogonal projection of a fourth conductive member included in a semiconductor material layer pattern of the first light-emission control transistor onto the base substrate. A semiconductor material layer pattern of the threshold compensation transistor includes a first channel member and a second channel member, and the semiconductor material layer pattern of the first light-emission control transistor includes a third channel member. The fourth conductive member is arranged between the second channel member and the third channel member.
In a possible embodiment of the present disclosure, the display substrate further includes an anode layer arranged at a side of the TFT array layer distal to the first protection layer, the TFT array layer includes a first power source line and a first light-emission control transistor, the pinhole region does not overlap an orthogonal projection of the first power source line onto the base substrate and an orthogonal projection of a third electrode of the first light-emission control transistor onto the base substrate, and the third electrode is electrically connected to the anode layer.
In a possible embodiment of the present disclosure, a film-forming temperature of the first protection layer is smaller than a threshold temperature, and the threshold temperature is greater than or equal to 230° C. and smaller than or equal to 380° C.
In a possible embodiment of the present disclosure, the first protection layer is made of an inorganic material or an organic material.
In a possible embodiment of the present disclosure, the first protection layer is made of silicon oxide or silicon nitride.
In a possible embodiment of the present disclosure, a thickness of the first protection layer is greater than or equal to 100 nm and smaller than or equal to 400 nm.
In a possible embodiment of the present disclosure, the display substrate further includes a fingerprint identification layer arranged at a side of the base substrate distal to the light-shielding layer and including a fingerprint identification sensor. The light-shielding layer is arranged at a light-entering side of the fingerprint identification sensor, and the imaging pinhole is arranged in such a manner as to allow light to pass therethrough toward the fingerprint identification sensor.
In a possible embodiment of the present disclosure, the light-shielding layer is made of a nontransparent material.
In a possible embodiment of the present disclosure, the display substrate further includes a planarization layer and an anode layer arranged sequentially in that order at a side of the TFT array layer distal to the buffer layer, and an orthogonal projection of the imaging pinhole onto the base substrate does not overlap an orthogonal projection of the anode layer onto the base substrate.
In a possible embodiment of the present disclosure, the buffer layer is made of silicon nitride, silicon oxide or polycrystalline silicon.
In a possible embodiment of the present disclosure, a thickness of the buffer layer is greater than or equal to 200 nm and smaller than or equal to 600 nm.
In a possible embodiment of the present disclosure, the metal film layer include a first metal layer, a second metal layer and a third metal layer. A gate line, a resetting control signal line, a light-emission control signal line, a second electrode plate of a first storage capacitor, and a gate electrode of each transistor in a pixel circuit are located in the first metal layer, a resetting power source line and a first electrode plate of the first storage capacitor are located in the second metal layer, and a first power source line, a data line, and a first electrode and a second electrode of each transistor are located in the third metal layer.
In another aspect, the present disclosure provides in some embodiments a method for manufacturing a display substrate, including: forming a light-shielding layer on a base substrate, the base substrate being provided with a first region, a plurality of imaging pinholes being formed in the light-shielding layer, at least a part of an orthogonal projection of the imaging pinhole onto the base substrate being located within the first region; forming a first protection layer at a side of the light-shielding layer distal to the base substrate; and forming a TFT array layer on the first protection layer in such a manner that an orthogonal projection of a metal film layer of the TFT array layer onto the base substrate is located outside the first region. An orthogonal projection of the first protection layer onto the base substrate at least covers a part of the first region. The first region includes a pinhole region, at least a part of the orthogonal projection of the imaging pinhole onto the base substrate is located within the pinhole region, and the orthogonal projection of the first protection layer onto the base substrate at least covers the pinhole region.
In a possible embodiment of the present disclosure, the forming the first protection layer at the side of the light-shielding layer distal to the base substrate includes: forming the first protection layer at the side of the light-shielding layer distal to the base substrate through a low temperature process, a film-forming temperature of the first protection layer is smaller than a threshold temperature, and the threshold temperature is greater than or equal to 230° C. and smaller than or equal to 380° C.
In yet another aspect, the present disclosure provides in some embodiments a display panel including the above-mentioned display substrate.
In still yet another aspect, the present disclosure provides in some embodiments a display device including the above-mentioned display panel.
The present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.
The present disclosure provides in at least one embodiment a display substrate, which includes a base substrate, and a light-shielding layer and a TFT array layer arranged sequentially in that order on the base substrate. A plurality of imaging pinholes is formed in the light-shielding layer. A first protection layer is arranged between the light-shielding layer and the TFT array layer. The base substrate is provided with a first region, an orthogonal projection of a metal film layer of the TFT array layer onto the base substrate is located outside the first region, and at least a part of an orthogonal projection of the imaging pinhole onto the base substrate is located within the first region. An orthogonal projection of the first protection layer onto the base substrate at least covers a part of the first region. The first region includes a pinhole region, and at least a part of the orthogonal projection of the imaging pinhole onto the base substrate is located within the pinhole region. The orthogonal projection of the first protection layer onto the base substrate at least covers the pinhole region. The display substrate further includes a buffer layer arranged between the first protection layer and the TFT array layer.
In at least one embodiment of the present disclosure, the base substrate may be a flexible substrate, e.g., a polyimide (PI) substrate. However, the base substrate shall not be limited thereto.
In at least one embodiment of the present disclosure, the light-shielding layer may be made of, but not limited to, a metal material.
According to the display substrate in the at least one embodiment of the present disclosure, at least a part of the orthogonal projection of the imaging pinhole in the light-shielding layer onto the base substrate may be arranged within the first region, so as to prevent each imaging pinhole from being shielded by the metal film layer of the TFT array layer, thereby to perform the fingerprint identification in a better manner. In addition, through the first protection layer between the light-shielding layer and the TFT array layer, it is able to effectively prevent plasmas from being accumulated on the light-shielding layer and prevent an electric arc from breaking down the light-shielding layer, thereby to improve a fingerprint identification effect.
In the related art, during the manufacture of the display substrate, a semiconductor layer and an inorganic layer needs to be continuously deposited after the deposition of the light-shielding layer. The semiconductor layer and the inorganic layer are deposited through a high-temperature high-frequency film-forming process, so the plasmas may be accumulated at a surface of the light-shielding layer and the generated electric arc may break down the light-shielding layer, so as to form a light-leakage pinhole in the light-shielding layer. As a result, a slight light leakage may occur and the fingerprint identification effect may be adversely affected. Based on this, according to the display substrate in the at least one embodiment of the present disclosure, at least a part of the orthogonal projection of the imaging pinhole in the light-shielding layer onto the base substrate may be located within the first region, and the first protection layer may be arranged between the light-shielding layer and the TFT array layer.
During the implementation, the orthogonal projection of the first protection layer onto the base substrate may at least overlap a part of the first region, so as to prevent a portion of the light-shielding layer corresponding to the first region from being broken down by the electric arc to generate the light-leakage pinhole, thereby to prevent a fingerprint imaging effect from being adversely affected by stray light penetrating through the light-leakage pinhole.
In at least one embodiment of the present disclosure, the first region may include a pinhole region, and at least a part of the orthogonal projection of the imaging pinhole onto the base substrate may be located within the pinhole region.
During the implementation, the orthogonal projection of the first protection layer onto the base substrate may at least covers the pinhole region.
In at least one embodiment of the present disclosure, the buffer layer may be made of, but not limited to, silicon nitride, silicon oxide or polycrystalline silicon.
During the implementation, the buffer layer may have, but not limited to, a thickness greater than or equal to 200 nm and smaller than or equal to 600 nm.
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In the display substrate in
In the display substrate in
In the display substrate of the related art in
In the display substrate in
In the display substrate in
In
In the display substrate in
Based on the above, in the embodiments of the present disclosure, the first protection layer may be deposited after the deposition of the light-shielding layer and prior to the multi-deposition (i.e., the simultaneous deposition of the inorganic layer and the semiconductor layer), so as to effectively prevent the electric arc from breaking down the light-shielding layer.
In
In actual use, the threshold temperature may be adjusted according to the practical need.
In a preferred embodiment of the present disclosure, the first protection layer may be a low-temperature protection layer. The first protection layer may be formed through a low-temperature process after the deposition of the light-shielding layer, and then a film may be formed on the first protection layer at a high temperature and high power. Through the first protection layer, it is able to prevent the plasmas from being accumulated on the light-shielding layer, thereby to prevent the occurrence of arc breakdown. A specific film-forming condition may depend on the imaging definition and the process requirements.
In at least one embodiment of the present disclosure, the first protection layer may be made of an inorganic material or an organic material. For example, the first protection layer may be made of, but not limited to, silicon oxide or silicon nitride.
During the implementation, the first protection layer may have, but not limited to, a thickness greater than or equal to 100 nm and smaller than or equal to 400 nm.
In at least one embodiment of the present disclosure, the first protection layer may be a transparent film layer. Alternatively, the first protection layer may be nontransparent, and at this time a portion of the first protection layer at a position corresponding to the imaging pinhole needs to be removed through a mask, so as to prevent the light from being blocked during the pinhole imaging.
To be specific, the first protection layer may be made of, but not limited to, silicon oxide or silicon nitride.
During the implementation, the thickness of the first protection layer may be, but not limited to, greater than or equal to 100 nm and smaller than or equal to 400 nm.
To be specific, the display substrate may further include a fingerprint identification layer arranged at a side of the base substrate distal to the light-shielding layer and including a fingerprint identification sensor. The light-shielding layer may be arranged at a light-entering side of the fingerprint identification sensor, and the imaging pinhole may be arranged in such a manner as to allow light to pass therethrough toward the fingerprint identification sensor so as to perform the fingerprint identification.
During the implementation, the fingerprint identification layer may include, but not limited to, a plurality of fingerprint identification sensors arranged in an array form.
In at least one embodiment of the present disclosure, the light-shielding layer may be made of a nontransparent material, e.g., metal. However, the material of the light-shielding layer may not be limited thereto.
To be specific, the display substrate in the at least one embodiment of the present disclosure may further include a planarization layer and an anode layer arranged sequentially in that order at a side of the TFT array layer distal to the buffer layer, and an orthogonal projection of the imaging pinhole onto the base substrate may not overlap an orthogonal projection of the anode layer onto the base substrate.
In at least one embodiment of the present disclosure, the buffer layer may be made of, but not limited to, silicon nitride, silicon oxide or polycrystalline silicon.
During the implementation, the buffer layer may have, but not limited to, a thickness greater than or equal to 200 nm and smaller than or equal to 600 nm.
During the implementation, the anode layer may be made of, but not limited to, a material capable of reflecting light.
Preferably, the orthogonal projection of the imaging pinhole onto the base substrate may not overlap the orthogonal projection of the anode layer onto the base substrate, so as to prevent the imaging pinhole from being shielded by the anode layer that is capable of shielding the light, thereby to prevent the fingerprint imaging from being adversely affected.
To be specific, the display substrate in the at least one embodiment of the present disclosure may further include an organic light-emitting layer and a cathode layer arranged sequentially in that order at a side of the anode layer distal to the planarization layer.
During the implementation, the cathode layer may be made of, but not limited to, a transparent conductive material.
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In the display substrate in
In the display substrate in
In at least one embodiment of the present disclosure, the third insulation layer GI3 may be, but not limited to, an interlayer insulation layer.
In the display substrate in
During the implementation, the plurality of imaging pinholes may correspond to pixel regions respectively, or one imaging pinhole may be arranged in a plurality of pixel regions, as long as the imaging accuracy is satisfied.
In the display substrate in
In addition, during the manufacture of the display substrate in
In at least one embodiment of the present disclosure, the first protection layer P0 may be formed through a low temperature process, and then the film may be formed on the first protection layer P0 at a high temperature and high power. The two film layers are formed at different film-forming temperatures and/or different film-forming powers, so there may exist an obvious interface between the two film layers.
During the manufacture of the display substrate in
In
In the display substrate in
During the implementation, in order to prevent the occurrence of static electricity, the light-shielding layer S1 shall not be in a floating state, i.e., a voltage needs to be applied to the light-shielding layer S1.
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In at least one embodiment of the present disclosure, apart from the pinhole region, the first region may further include some other regions. The orthogonal projection of the metal film layer of the TFT array layer onto the base substrate may not be located within the other regions. The orthogonal projection of the imaging pinhole onto the base substrate may not be located within the other regions, and instead, it may be located at a position close to the other regions. Hence, when the other regions are not protected by the first protection layer, the fingerprint imaging effect may be adversely affected too.
During the implementation, the TFT array layer may include a pixel circuit, and
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For example, one of the first power source line VDD and the second power source line VSS may be a high voltage line, and the other may be a low voltage line. For example, as shown in
For example, the resetting power source line Vinit may be a direct current reference voltage line capable of outputting a direct current reference voltage of a constant value. The resetting power source line Vinit may be a high voltage line or a low voltage line, as long as the resetting signal is capable of being applied to reset the gate electrode of the driving transistor T1 and the electrode of the light-emitting element 120 to which the first light-emission voltage is to be applied, which will not be particularly defined herein.
It should be appreciated that, the gate electrodes of T6 and T7 may be connected to different resetting control signal lines, the first electrodes of T6 and T7 may be connected to different resetting power source lines, the gate electrodes of T4 and T5 may be connected to different light-emission control signal lines, and the gate electrodes of T2 and T3 may be connected to different gate lines, which will not be particularly defined herein.
It should be further appreciated that, the driving circuitry 122, the data write-in circuitry 126, the storage circuitry 127, the threshold compensation circuitry 128 and the resetting circuitry 129 of the pixel circuit in
For example, depending on characteristics of the transistors, the transistors may include N-type transistors and P-type transistors. For clarification, in the embodiments of the present disclosure, the P-type transistors will be taken as an example. In other words, in the description of the present disclosure, the driving transistor T1, the data write-in transistor T2, the threshold compensation transistor T3, the second light-emission control transistor T4, the first light-emission control transistor T5, the first resetting transistor T6 and the second resetting transistor T7 may all be P-type transmissions. However, the transistors in the embodiments of the present disclosure may not be limited to the P-type transistors, and the N-type transistors may also be adopted according to the practical need, so as to achieve functions of one or more of the transistors.
It should be appreciated that, the transistors adopted in the embodiments of the present disclosure may be TFTs, Field Effect Transistors (FETs) or any other switching elements having a same characteristic. The TFT may include an oxide semiconductor TFT, an amorphous silicon TFT or a polycrystalline silicon TFT. A source electrode and a drain electrode of the transistor may be arranged symmetrically in structure, so they may be the same in the physical structure. In the embodiments of the present disclosure, in order to differentiate electrodes of the transistor, apart from a gate electrode as a control electrode, one of the two electrodes may be directly described as a first electrode, and the other may be described as a second electrode. Hence, in the embodiments of the present disclosure, the first electrode and the second electrode of each of all of or parts of the transistors may be replaced with each other according to the practical need.
During the implementation, the TFT array layer may include a semiconductor material layer, a first gate metal layer, a second gate metal layer and a source/drain metal layer.
In at least one embodiment of the present disclosure, the semiconductor material layer may be, but not limited to, an active layer.
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In
In at least one embodiment of the present disclosure, the first electrode 342a of T6 may be a source electrode of T6, the second electrode 341a of T3 may be a source electrode of T3, and the third electrode 343a of T5 may be a drain electrode of T5. However, the present disclosure shall not be limited thereto.
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In at least one embodiment of the present disclosure, the first region may include a first sub-region. The TFT array layer may include a resetting power source line, a first resetting transistor, a threshold compensation transistor and a driving transistor. The first sub-region may not overlap an orthogonal projection of a first conductive member included in a semiconductor material layer pattern of the first resetting transistor onto the base substrate and an orthogonal projection of a second conductive member included in a semiconductor material layer pattern of the threshold compensation transistor onto the base substrate. The first conductive member may be electrically connected to a first electrode of the first resetting transistor, and the first electrode may be electrically connected to the resetting power source line. The second conductive member may be electrically connected to a second electrode of the threshold compensation transistor, and the second electrode may be electrically connected to a gate electrode of the driving transistor.
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In at least one embodiment of the present disclosure, the first region may include a second sub-region, and the TFT array layer may include a gate line, a threshold compression transistor and a driving transistor. The second sub-region may not overlap an orthogonal projection of the gate line onto the base substrate, an orthogonal projection of a second electrode of the threshold compensation transistor onto the base substrate, an orthogonal projection of a second conductive member included in a semiconductor material layer pattern of the threshold compensation transistor onto the base substrate, and an orthogonal projection of a first gate metal pattern onto the base substrate. The second conductive member may be electrically connected to the second electrode of the threshold compensation transistor, and the second electrode may be electrically connected to a gate electrode of the driving transistor. The first gate metal pattern may be a gate metal pattern arranged between the gate line included in a first gate metal layer of the TFT array layer and the gate electrode of the threshold compensation transistor.
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In at least one embodiment of the present disclosure, the first region may include a third sub-region, and the TFT array layer may include a gate line, a threshold compensation transistor and a driving transistor. The third sub-region does not overlap an orthogonal protection of the gate line onto the base substrate, an orthogonal projection of a third conductive member included in a semiconductor material layer pattern of the threshold compensation transistor onto the base substrate and an orthogonal projection of a first gate metal pattern onto the base substrate. The semiconductor material layer pattern of the threshold compensation transistor may include a first channel member and a second channel member, and the third conductive member may be arranged between the first channel member and the second channel member. The first gate metal pattern may be a gate metal pattern arranged between the gate line included in the first gate metal layer of the TFT array layer and a gate electrode of the threshold compensation transistor.
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In at least one embodiment of the present disclosure, the first region may include a fourth sub-region, and the TFT array layer may include a gate line, a first capacitor, a threshold compensation transistor and a first light-emission control transistor. The fourth sub-region may not overlap an orthogonal projection of the gate line onto the base substrate, an orthogonal projection of a first electrode plate of the first capacitor onto the base substrate, an orthogonal projection of a second electrode of the threshold compensation transistor onto the base substrate, and an orthogonal projection of a fourth conductive member included in a semiconductor material layer pattern of the first light-emission control transistor onto the base substrate. A semiconductor material layer pattern of the threshold compensation transistor may include a first channel member and a second channel member, and the semiconductor material layer pattern of the first light-emission control transistor may include a third channel member. The fourth conductive member may be arranged between the second channel member and the third channel member.
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In at least one embodiment of the present disclosure, the first region may include a fifth sub-region, and the TFT array layer may include a first capacitor, a threshold compensation transistor, a first light-emission control transistor, a first power source line and a light-emission control signal line. The fifth sub-region may not overlap an orthogonal projection of a first electrode plate of the first capacitor onto the base substrate, an orthogonal projection of the light-emission control signal line onto the base substrate, an orthogonal projection of the first power source line onto the base substrate, and an orthogonal projection of a fourth conductive member included in a semiconductor material layer pattern of the first light-emission control transistor onto the base substrate. A semiconductor material layer pattern of the threshold compensation transistor may include a first channel member and a second channel member, and the semiconductor material layer pattern of the first light-emission control transistor may include a third channel member. The fourth conductive member may be arranged between the second channel member and the third channel member.
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During the implementation, in at least one embodiment of the present disclosure, the display substrate may further include an anode layer arranged at a side of the TFT array layer distal to the first protection layer, the TFT array layer may include a first power source line and a first light-emission control transistor, the pinhole region may not overlap an orthogonal projection of the first power source line onto the base substrate and an orthogonal projection of a third electrode of the first light-emission control transistor onto the base substrate, and the third electrode may be electrically connected to the anode layer.
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In at least one embodiment of the present disclosure, at least the first gate insulation layer GI1, the second gate insulation layer GI2 and the third insulation layer GI3 may be arranged at each of the sub-regions of the first region. However, the present disclosure shall not be limited thereto.
In addition,
During the implementation, the metal film layer of the TFT array layer may include a first metal layer, a second metal layer and a third metal layer. The gate line, the resetting control signal line, the light-emission control signal line, the second electrode plate of the first storage capacitor and the gate electrode of each transistor in the pixel circuit may be arranged at the first metal layer, the resetting power source line and the first electrode plate of the first storage capacitor may be arranged at the second metal layer, and the first power source line, the data line and the first electrode and the second electrode of the transistor may be arranged at the third metal layer.
In at least one embodiment of the present disclosure, the first metal layer may be the first gate metal layer, the second metal layer may be the second gate metal layer, and the third metal layer may be the source/drain metal layer. However, the present disclosure shall not be limited thereto.
The present disclosure further provides in at least one embodiment a method for manufacturing a display substrate, which includes: forming a light-shielding layer on a base substrate, the base substrate being provided with a first region, a plurality of imaging pinholes being formed in the light-shielding layer, at least a part of an orthogonal projection of the imaging pinhole onto the base substrate being located within the first region; forming a first protection layer at a side of the light-shielding layer distal to the base substrate; and forming a TFT array layer on the first protection layer in such a manner that an orthogonal projection of a metal film layer of the TFT array layer onto the base substrate is located outside the first region. An orthogonal projection of the first protection layer onto the base substrate at least may cover a part of the first region. The first region may include a pinhole region, at least a part of the orthogonal projection of the imaging pinhole onto the base substrate may be located within the pinhole region, and the orthogonal projection of the first protection layer onto the base substrate may at least cover the pinhole region.
According to the method for manufacturing the display substrate in the at least one embodiment of the present disclosure, at least a part of the orthogonal projection of the imaging pinhole in the light-shielding layer onto the base substrate may be arranged within the first region, so as to prevent each imaging pinhole from being shielded by the metal film layer of the TFT array layer, thereby to perform the fingerprint identification in a better manner. In addition, in the display substrate according to at least one embodiment of the present disclosure, through the first protection layer between the light-shielding layer and the TFT array layer, it is able to effectively prevent plasmas from being accumulated on the light-shielding layer and prevent an electric arc from breaking down the light-shielding layer, thereby to improve a fingerprint identification effect.
During the implementation, the orthogonal projection of the first protection layer onto the base substrate may at least overlap a part of the first region, so as to prevent a portion of the light-shielding layer corresponding to the first region from being broken down by the electric arc to generate the light-leakage pinhole, thereby to prevent a fingerprint imaging effect from being adversely affected by stray light penetrating through the light-leakage pinhole.
Preferably, the forming the first protection layer at the side of the light-shielding layer distal to the base substrate may include: forming the first protection layer at the side of the light-shielding layer distal to the base substrate through a low temperature process, a film-forming temperature of the first protection layer is smaller than a threshold temperature, and the threshold temperature is greater than or equal to 230° C. and smaller than or equal to 380° C.
Preferably, the first protection layer may be a low-temperature protection layer. The first protection layer may be formed through a low-temperature process after the deposition of the light-shielding layer, and then a film may be formed on the first protection layer at a high temperature and high power. Through the first protection layer, it is able to effectively prevent the plasmas from being accumulated on the light-shielding layer, thereby to prevent the occurrence of arc breakdown. A specific film-forming condition may depend on the imaging definition and the process requirements.
In at least one embodiment of the present disclosure, the forming the first protection layer at the side of the light-shielding layer distal to the base substrate through a low-temperature process may include forming the first protection layer at the side of the light-shielding layer distal to the base substrate through a low-temperature process using an inorganic material or an organic material.
The present disclosure further provides in at least one embodiment a display panel including the above-mentioned display substrate.
The present disclosure further provides in at least one embodiment a display device including the above-mentioned display panel.
The display device provided in at least one embodiment of the present disclosure may be any product or member having a display function, e.g., mobile phone, flat-panel computer, television, display, laptop computer, digital photo frame or navigator.
The above embodiments are preferable. It should be appreciated that, a person skilled in the art may make further modifications and improvements without departing from the principle of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2019/126989 | 12/20/2019 | WO | 00 |