Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, in particular to a display substrate, a method for preparing the display substrate, and a display apparatus.
An Organic Light Emitting Diode (OLED), as an active light emitting display device, has advantages such as self-luminance, wide viewing angle, high contrast, relatively low power consumption, and very quick response. With continuous development of the display technology, the OLED technology is increasingly applied to flexible display apparatuses, and flexible display apparatuses are gradually developing from a two-dimensional directional variable mode to a three-dimensional directional variable mode.
An island-bridge structure is usually used in a flexible OLED display substrate with the three-dimensional directional variable mode. The island-bridge structure is formed by providing light emitting units in pixel island areas and providing connection lines between the pixel island areas in connection bridge areas. When an external tensile force is applied, deformation mainly occurs in the connection bridge areas, and the light emitting units of the pixel island areas substantially keep their original shape, and may be prevented from being damaged. In order to increase deformability of the flexible display apparatus, the periphery of the pixel island area is further provided with a hole area having multiple microporous structures, wherein the microporous structures penetrate through a flexible base substrate.
The following is a summary of subject matters described herein in detail. The summary is not intended to limit the scope of protection of claims.
An embodiment of the present disclosure provides a display substrate, including a plurality of pixel island areas separated from one another, a plurality of hole areas and a connection bridge area connecting the plurality of pixel island areas, wherein a hole area including a base substrate and an encapsulation layer, the base substrate is provided with an aperture and provided with a barrier structure on a side of the base substrate close to the aperture, and the encapsulation layer covers the side of the base substrate close to the aperture.
In an exemplary embodiment, the barrier structure is provided as a barrier groove, a notch of the barrier groove faces the aperture, and a thickness of the encapsulation layer inside the barrier groove is smaller than a thickness of the encapsulation layer outside the barrier groove, or the encapsulation layer inside the barrier groove is discontinuous.
In an exemplary embodiment, the hole area further includes a composite insulation layer provided on the base substrate, the encapsulation layer covers the composite insulation layer, the composite insulation layer includes a first end face facing the aperture, the base substrate includes a first barrier layer, a buffer layer and a second barrier layer which are stacked, and the first barrier layer includes a second end face facing the aperture, the buffer layer includes a third end face facing the aperture, and the second barrier layer includes a fourth end face facing the aperture.
In a direction parallel to the base substrate, a distance between the second end face and the first end face is smaller than a distance between the third end face and the first end face, a distance between the fourth end face and the first end face is smaller than the distance between the third end face and the first end face, the third end face is provided as a groove bottom of the barrier groove, and opposite surfaces of the first barrier layer and the second barrier layer are provided as sidewalls of the barrier groove.
In an exemplary embodiment, the base substrate includes a first flexible base substrate layer and a second flexible base substrate layer, the first flexible base substrate layer is provided on a side of the first barrier layer away from the buffer layer, the second flexible base substrate layer is provided on a side of the second barrier layer away from the buffer layer, the first flexible base substrate layer includes a fifth end face facing the aperture, and the second flexible base substrate layer includes a sixth end face facing the aperture.
In the direction parallel to the base substrate, a distance between the fifth end face and the first end face is larger than the distance between the second end face and the first end face, larger than the distance between the fourth end face and the first end face, and smaller than the distance between the third end face and the first end face, a distance between the sixth end face and the first end face is larger than the distance between the second end face and the first end face, larger than the distance between the fourth end face and the first end face, and smaller than the distance between the third end face and the first end face.
In an exemplary embodiment, the fifth end face is flush with the sixth end face, and the second end face is flush with the third end face.
In an exemplary embodiment, the barrier groove has a depth ranging from 0.2 microns to 2 microns and a width ranging from 0.2 microns to 2 microns.
In an exemplary embodiment, in a direction perpendicular to the base substrate, a width of the barrier groove is smaller than or equal to the thickness of the encapsulation layer outside the barrier groove.
In an exemplary embodiment, the barrier structure is provided as a barrier eave, the barrier eave extends into the aperture, the barrier eave is configured to form a groove structure with the rigid substrate, a thickness of the encapsulation layer within the groove structure is smaller than a thickness of the encapsulation layer outside the groove structure, or the encapsulation layer within the groove structure is discontinuous.
In an exemplary embodiment, the base substrate includes a buffer layer and a first barrier layer provided on the buffer layer, the first barrier layer extends into the aperture and protrudes beyond the buffer layer to form an eave structure, and the barrier eave includes a portion of the first barrier layer protruding beyond the buffer layer.
In an exemplary embodiment, a length of the first barrier layer protruding beyond the buffer layer ranges from 0.2 microns to 2 microns, and a thickness of the buffer layer ranges from 0.2 microns to 2 microns.
In an exemplary embodiment, further including an organic light emitting layer and a cathode, the organic light emitting layer and the cathode of the hole area are partially provided on the barrier eave.
An embodiment of the present disclosure further provides a method for preparing a display substrate, including:
forming multiple pixel island areas separated from each other, multiple hole areas and a connection bridge area connecting the multiple pixel island areas on a base substrate, the base substrate of a hole area is provided with an aperture, and a side of the base substrate close to the aperture is provided with a barrier structure; and
forming an encapsulation layer, wherein the encapsulation layer covers a sidewall of the base substrate close to the aperture, and the barrier structure is configured to form a fracture zone on the encapsulation layer that can break when the base substrate is lifted off from the rigid substrate.
In an exemplary embodiment, forming the multiple pixel island areas separated from each other, the multiple hole areas and the connection bridge area connecting the multiple pixel island areas on the base substrate includes:
forming a first flexible base substrate layer;
sequentially depositing a first barrier thin film, a buffer thin film and a second barrier thin film on the first flexible base substrate layer, and patterning the second barrier thin film by a patterning process to form a first barrier layer, a buffer layer, a second barrier layer and a first opening which are stacked, wherein the first opening is provided in the hole area and expose the first flexible base substrate layer;
etching the buffer layer, a surface of the buffer layer facing the first opening is recessed in a direction away from the first opening with respect to surfaces of the first barrier layer and the second barrier layer facing the first opening to form a barrier groove with a notch facing the first opening, barrier groove has a depth ranging from 0.2 microns to 2 microns, and a width ranging from 0.2 microns to 2 microns.
In an exemplary embodiment, forming the multiple pixel island areas separated from each other, the multiple hole areas and the connection bridge area connecting the multiple pixel island areas on the base substrate includes:
forming a buffer layer on a rigid substrate;
depositing a first barrier thin film on the buffer layer, patterning the first barrier thin film by a patterning process to form a first barrier layer and a first aperture, wherein the first aperture is located in the hole area, the buffer layer and the first barrier layer within the first aperture are etched away to expose the rigid substrate, the first aperture includes a first hole diameter area formed in the first barrier layer and a second hole diameter area formed in the buffer layer, a hole diameter of the first hole diameter area is smaller than a hole diameter of the second hole diameter area, a barrier eave is formed at a corresponding position of the first barrier layer and the second hole diameter area, and the barrier eave forms a barrier structure.
In an exemplary embodiment, forming the multiple pixel island areas separated from each other, the multiple hole areas and the connection bridge area connecting the multiple pixel island areas on the base substrate includes:
forming a buffer layer on a rigid substrate;
depositing a first barrier thin film on the buffer layer, and patterning the first barrier thin film by a patterning process to form a first barrier layer and a via hole, wherein the via hole is located in the hole area, the via hole is an annular hole, the first barrier layer within the via hole is etched away to expose the buffer layer, and the hole diameter of the via hole ranges between 0.2 microns and 2 microns;
etching the buffer layer to form an inner enlarging hole, wherein the inner enlarging hole is formed in the hole area and corresponds to the position of the via hole, the buffer layer within the inner enlarging hole is etched away to expose the rigid substrate, the hole diameter of the inner enlarging hole is larger than that of the via hole, a barrier eave is formed at the position of the first barrier layer on two sides of the via hole corresponding to the inner enlarging hole, and the barrier eave forms a barrier structure.
An embodiment of the present disclosure further provides a display apparatus including the above display substrate of the above embodiments.
Other aspects may be understood upon reading and understanding of the accompanying drawings and detailed descriptions.
Accompanying drawings are used to provide further understanding of technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with embodiments of the present disclosure, thus do not constitute a limitation on the technical solutions of the present disclosure.
The embodiments of the present disclosure will be described in detail below with reference to the drawings. It is to be noted that implementation modes may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that embodiments and contents may be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to contents described in following implementation modes only. The embodiments in the present disclosure and features in the embodiments may be combined randomly with each other if there is no conflict.
In the drawings, a size of each constituent element, and a thickness of a layer or a region are exaggerated sometimes for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and shapes and sizes of various components in the drawings do not reflect actual scales. In addition, the drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.
Ordinal numerals such as “first”, “second”, and “third” in the specification are set to avoid confusion between constituent elements, but not to set a limit in quantity.
In the specification, for convenience, wordings indicating directional or positional relationships, such as “center”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, and “outside”, are used for illustrating positional relationships between constituent elements with reference to the drawings, and are merely for facilitating the description of the specification and simplifying the description, rather than indicating or implying that a referred apparatus or element must have a particular orientation and be constructed and operated in the particular orientation. Therefore, they cannot be understood as limitations on the present disclosure. The positional relationships between the constituent elements may be changed as appropriate according to directions according to which the constituent elements are described. Therefore, appropriate replacements may be made according to situations without being limited to the wordings described in the specification.
In the specification, unless otherwise specified and defined explicitly, terms “mount”, “mutually connect”, and “connect” should be understood in a broad sense. For example, a connection may be a fixed connection, or a detachable connection, or an integrated connection. It may be a mechanical connection or an electrical connection. It may be a direct mutual connection, or an indirect connection through middleware, or internal communication between two components. Those of ordinary skills in the art may understand meanings of the above-mentioned terms in the present disclosure according to situations.
In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above −20° and below 20°, and thus also includes a state in which the angle is above −5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80° and below 100°, and thus also includes a state in which the angle is above 85° and below 95°.
In the specification, a “film” and a “layer” are interchangeable. For example, a “conductive layer” may be replaced with a “conductive film” sometimes. Similarly, an “insulation film” may be replaced with an “insulation layer” sometimes.
In a flexible OLED display substrate, a flexible layer is usually formed on a rigid substrate, and then the flexible layer is lifted off from the rigid substrate by laser lift off (LLO) process. As for a flexible OLED display substrate with a microporous structure, when the flexible OLED display substrate is lifted off from the rigid substrate, an encapsulation layer on a sidewall of the microporous structure will break, which will then reduce the reliability of encapsulation and affect the service life of the flexible OLED display substrate.
An embodiment of the present disclosure provides a display substrate, which includes multiple pixel island areas separated from each other, multiple hole areas and a connection bridge area connecting the multiple pixel island areas. The hole area includes a base substrate and an encapsulation layer. The base substrate is provided with an aperture, a barrier structure is provided on a side of the base substrate close to the aperture, and the encapsulation layer covers a side of the base substrate facing the aperture.
Technical solutions of the embodiments of the present disclosure are exemplarily illustrated below with reference to the accompanying drawings.
-shaped and T-shaped, wherein a width of an aperture 301 ranges from 10 microns to 500 microns. The connection bridge area 200 is located between a pixel island area 100 and a hole area 300, or between adjacent hole areas 300, connected with the adjacent pixel island area 100. Namely, the connection bridge area 200 surrounds the pixel island area 100 and the hole area 300. The connection bridge area 200 may be L-shaped, or multiple L-shaped connected shapes, such as
-shaped and T-shaped. A width of the connection bridge area 200 ranges from 10 microns to 500 microns. The light emitting units of the multiple pixel island areas 100 are in signal communication through a connection line 210 in the connection bridge area 200.
In some exemplary embodiments, as shown in
In some exemplary embodiments, as shown in
In some exemplary embodiments, an inorganic encapsulation thin film is only deposited in a small amount or is not deposited at some positions in the barrier groove 106, and the encapsulation layer 24 inside the barrier groove 106 is thus thinner, even discontinuous and prone to breakage. That is to say, the encapsulation layer 24 inside the barrier groove 106 forms the fracture area, so that the encapsulation layer 24 located at a side of the barrier groove 106 close to the second flexible base substrate 105 can be effectively prevented from being torn and broken during a process of separating the base substrate 10 from the rigid substrate, thereby enhancing the reliability of encapsulation of the encapsulation layer 24 without affecting the tensile property of the device. That is, the barrier groove 106 is configured to form the fracture area of the encapsulation layer 24 and the barrier groove 106 forms a barrier structure.
In some exemplary embodiments, a depth L1 of the barrier groove 106 ranges from about 0.2 microns to 2 microns, and a width D1 of the barrier groove 106 ranges from about 0.2 microns to 2 microns. In other words, the depth of the barrier groove 106 refers to a distance from the notch to the bottom of the groove and the width of the barrier groove 106 refers to a distance between two opposite sidewalls. The barrier groove 106 with a larger depth and a smaller width facilitates restricting an inorganic packaging material into the barrier groove 106, thereby reducing amount of the inorganic packaging material deposited within the barrier groove 106.
In some exemplary embodiments, the first flexible base substrate layer 101 includes a fifth end face facing the aperture 301, and the second flexible base substrate layer 105 includes a sixth end face facing the aperture 301. In the direction parallel to the base substrate 10, a distance between the fifth end face and the first end face is larger than the distance between the second end face and the first end face, larger than the distance between the fourth end face and the first end face, and smaller than the distance between the third end face and the first end face. A distance between the sixth end face and the first end face is larger than the distance between the second end face and the first end face, larger than the distance between the fourth end face and the first end face, and smaller than the distance between the third end face and the first end face. The fifth end face is flush with the sixth end face.
A structure of the display substrate will be described below through an example of a preparation process of the display substrate. A “patterning process” mentioned in embodiments of the present disclosure includes processes such as film layer deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. The deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition. The coating may be any one or more of spray coating and spin coating. The etching may be any one or more of dry etching and wet etching. A “thin film” refers to a thin film layer prepared from a material on a base substrate by a process of deposition or coating. If a patterning process is not needed by a “thin film” throughout a whole preparation process, the “thin film” may also be referred to as a “layer”. When a patterning process is also needed by a “thin film” throughout a whole preparation process, the thin film is referred to as a “thin film” before the patterning process and referred to as a “layer” after the patterning process. The “layer” after the patterning process includes at least one “pattern”. “A and B are provided in a same layer” mentioned in the present disclosure means that A and B are simultaneously formed by a same patterning process. “An orthographic projection of A contains an orthographic projection of B” refers to that the orthographic projection of B falls within a range of the orthographic projection of A or the orthographic projection of A covers the orthographic projection of B.
(1) A base substrate is prepared on a rigid substrate 2.
A first flexible base substrate thin film is coated on the rigid substrate 2 and cured into a film to form a first flexible base substrate layer 101, as shown in
Subsequently, a first barrier thin film, a buffer thin film, and a second barrier thin film are deposited on the first flexible base substrate layer 101, and the second barrier thin film is patterned by a patterning process, thereby forming patterns of the first barrier layer 102, the buffer layer 103, and the second barrier layer 104 which are stacked and the first opening k1, as shown in
Subsequently, a second flexible base substrate thin film is coated on the base substrate on which the above patterns are formed, and cured into a film to form a second flexible base substrate layer 105, as shown in
(2) Patterns of a drive structure layer and a connection line are prepared on the base substrate. The pattern of the drive structure layer is located in the pixel island area, and the pattern of the connection line is located in the connection bridge area.
A first inorganic insulation thin film and an active layer thin film are sequentially deposited on the base substrate 10, and the active layer thin film is patterned through a patterning process to form a first insulation layer 11 covering the entire base substrate 10 and a pattern of an active layer 12 provided on the first insulation layer 11. The pattern of the active layer 12 is formed in the pixel island area 100. After this patterning process, the connection bridge area 200 and the hole area 300 include the first insulation layer 11 provided on the base substrate 10, and the active layer thin film of the connection bridge area 200 and the hole area 300 are etched away.
Then, a second inorganic insulation thin film and a first metal thin film are sequentially deposited and the first metal thin film is patterned by a patterning process to form a second insulation layer 13 covering the pattern of the active layer 12 and a pattern of a first gate metal layer provided on the second insulation layer 13. The pattern of the first gate metal layer is formed in the pixel island area 100 and includes at least a gate electrode 141 and a first capacitor electrode 142. After this patterning process, the connection bridge area 200 and the hole area 300 include the first insulation layer 11 and the second insulation layer 13 which are stacked on the base substrate 10, and the first metal thin film of the connection bridge area 200 and the hole area 300 are etched away.
Then, a third inorganic insulation thin film and a second metal thin film are sequentially deposited and the second metal thin film is patterned by a patterning process to form a third insulation layer 15 covering the first gate metal layer and a pattern of a second gate metal layer provided on the third insulation layer 15. The pattern of the second gate metal layer is formed in the pixel island area 100 and includes at least a second capacitor electrode 161. A position of the second capacitor electrode 161 corresponds to that of the first capacitor electrode 142. An orthographic projection of the second capacitor electrode 161 on the base substrate 10 at least partially overlaps with an orthographic projection of the first capacitor electrode 142 on the base substrate 10. After this patterning process, the connection bridge area 200 and the hole area 300 include the first insulation layer 11, the second insulation layer 13 and the third insulation layer 15 which are stacked on the base substrate 10, and the second metal thin film of the connection bridge area 200 and the hole area 300 are etched away.
Then, a fourth inorganic insulation thin film is deposited and patterned by a patterning process to form a pattern of a fourth insulation layer 17 covering the second gate metal layer. The fourth insulation layer 17 is provided with two first via holes k2, and the fourth insulation layer 17, the third insulation layer 15 and the second insulation layer 13 in the two first via holes k2 are etched away, exposing a surface of the active layer 13. After this patterning process, the connection bridge area 200 and the hole area 300 include the first insulation layer 11, the second insulation layer 13, the third insulation layer 15 and the fourth insulation layer 17 which are stacked on the base substrate 10.
Subsequently, a third metal thin film is deposited and patterned through the patterning process to form a pattern of a source-drain metal layer on the fourth insulation layer 17, and the pattern of the source-drain metal layer includes a source electrode 181 and a drain electrode 182 located in the pixel island area 100, and the connection line (not shown in the drawings) located in the connection bridge area 200. The source electrode 181 and the drain electrode 182 are electrically connected with the active layer 12 through the via holes k2. After this patterning process, the film layer structure of the hole area 300 remains unchanged.
So far, the preparation of the drive structure layer of the pixel island area and the connection line of the connection bridge area on the base substrate has is completed. In the drive structure layer of the pixel island area, the active layer, the gate electrode, the source electrode and the drain electrode form a thin film transistor, wherein the first capacitor electrode and the second capacitor electrode form a first storage capacitor. The connection bridge area and the hold area include the composite insulation layer provided on the base substrate, and the composite insulation layer includes the first insulation layer, the second insulation layer, the third insulation layer, and the fourth insulation layer which are stacked. The connection bridge area further includes the connection line provided on the composite insulation layer.
In an exemplary embodiment, the first insulation layer, the second insulation layer, the third insulation layer, and the fourth insulation layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and each may be of a single layer, multiple layers, or a composite layer. The first insulation layer is referred to as the buffer layer configured to improve the water oxygen resistance of the base substrate, the second and the third insulation layers are referred to as gate insulation (GI) layers, and the fourth insulation layer is referred to as a interlayer dielectric (ILD) layer. The first metal thin film, the second metal thin film and the third metal thin film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which may be in a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti. The active layer may be made of various materials, such as amorphous indium gallium zinc oxide (α-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (α-Si), polycrystalline silicon (p-Si), hexathiophene and polythiophene. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic substance technology.
(3) A planarization thin film of an organic material is coated on the base substrate on which the above patterns are formed, and a planarization layer 19 is formed in the pixel island area 100 by masking, exposure and development processes, and a pattern of a second via hole k3 is formed in the planarization layer 19. The second via hole k3 is formed in the pixel island area 100, and the planarization layer 19 in the second via hole k3 is developed away to expose a surface of the drain electrode 182 of the thin film transistor. After this process, film layer structures of the connection bridge area 200 and the hole area 300 remain unchanged.
(4) A transparent conductive thin film is deposited on the base substrate on which the above patterns are formed and patterned by a patterning process to form a pattern of an anode 20. The anode 20 is formed on the planarization layer 19 of the pixel island area 100 and is connected with the drain electrode 182 of the thin film transistor through the second via hole k3. After this patterning process, the film layer structures of the connection bridge area 200 and the hole area 300 remain unchanged. In an exemplary embodiment, the transparent conductive thin film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).
(5) A pixel definition thin film is coated on the base substrate on which the above patterns are formed, and patterns of the pixel definition layer (PDL) 21 and the isolation dam 25 are formed by masking, exposure and development processes. The pixel definition layer 21 is formed in the pixel island area 100 and the isolation dam 25 is formed in the connection bridge area 200. In a plane perpendicular to the base substrate, a cross section of the isolation dam 25 has a trapezoidal shape with a narrower upper bottom and a wider lower bottom. The pixel definition layer 21 is provided with pixel openings, and the pixel definition layer 21 within the pixel opening is developed away to expose a surface of the anode 20. In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic or polyethylene terephthalate. In some exemplary embodiments, the isolation dam 25 may be formed together with the planarization layer 19 using a single patterning process. That is, the isolation dam 25 and the planarization layer 19 may be provided in the same layer.
(6) The composite insulation layer is patterned by a patterning process on the base substrate on which the above patterns are formed, and a pattern of a second opening k4 is formed, as shown in
(7) The second flexible base substrate layer 105 is etched on the base substrate on which the above patterns are formed and a pattern of a third opening k5 is formed, as shown in
(8) The buffer layer 103 is etched on the base substrate on which the above patterns are formed. As shown in
(9) An organic light emitting material and a cathode metal thin film are sequentially evaporated on the base substrate on which the above patterns are formed, and patterns of an organic light emitting layer 22 and a cathode 23. In the pixel island area 100, the organic light emitting layer 22 is connected with the anode 20 in the pixel opening area, and the cathode 23 is provided on the organic light emitting layer 22. In the connection bridge area 200, the organic light emitting layer 22 and the cathode 23 cover the isolation dam 25. In the hole area 300, the organic light emitting layer 22 and the cathode 23 are separated by a side of the composite insulation layer facing the aperture 301 i.e. by the first end face. The organic light emitting layer mainly includes a light emitting layer (EML). In actual implementation, the organic light emitting layer may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transporting layer, and an electron injection layer provided sequentially to improve an efficiency of injecting electrons and holes into the light emitting layer. The cathode may be made of one of a metal material such as magnesium (Mg), argentum (Ag), aluminum (Al), copper (Cu), lithium (Li), or an alloy of one or more of the above metals.
(9) An inorganic encapsulation thin film is deposited on the base substrate on which the above patterns are formed, and as shown in
(10) A display substrate 1 is formed by lifting off the base substrate 10 from the rigid substrate 2 using a laser process, as shown in
the base substrate 10 including the first flexible base substrate layer 101, the first barrier layer 102, the buffer layer 103, the second barrier layer 104, and the second flexible base substrate layer 105;
the first insulation layer 11 provided on the base substrate 10;
the active layer 12 provided on the first insulation layer 11;
the second insulation layer 13 provided on the active layer 12;
the first gate metal layer 14 provided on the second insulation layer 13, wherein the first gate metal layer 14 is provided in the pixel island area 100 and includes at least the gate electrode 141 and the first capacitor electrode 142;
the third insulation layer 15 covering the first gate metal layer 14;
the second gate metal layer 16 provided on the third insulation layer 15, wherein the second gate metal layer 16 is provided in the pixel island area 100 and includes at least the second capacitor electrode 161, and the position of the second capacitor electrode 161 corresponding to the position of the first capacitor electrode 142;
the fourth insulation layer 17 covering the second gate metal layer 16, wherein the first via holes are provided on the fourth insulation layer 17, the first via holes are provided in the pixel island area 100, the first via holes expose the active layer 12, the first insulation layer 11, the second insulation layer 13, the third insulation layer 15 and the fourth insulation layer 17 form the composite insulation layer of the connection bridge area 200 and the hole area 300, and the composite insulation layer is an inorganic insulation layer;
the source-drain metal layer 18 provided on the fourth insulation layer 17, wherein the source-drain metal layer 18 at least includes the source electrode 181 and the drain electrode 182 provided in the pixel island area 100, and the connection line 210 in the connection bridge area 200, the source electrode 181 and the drain electrode 182 are connected with the active layer 12 through the first via holes, respectively, and a conductive channel is formed between the source electrode 181 and the drain electrode 182.
the planarization layer 19 covering the aforementioned structures, wherein the planarization layer 19 is provided with the second via hole exposing the drain electrode 182;
the anode 20 provided on the planarization layer 19, wherein the anode 20 is connected with the drain electrode 182 through the second via hole;
the pixel definition layer 21 and the isolation dam 25, wherein the pixel definition layer 21 is located in the pixel island area 100, the pixel definition layer 21 is provided on the anode 20, the pixel opening is provided on the pixel definition layer 21 and exposes the anode 20, and the isolation dam 25 is provided in the connection bridge area 200;
the organic light emitting layer 22 and the cathode 23 covering the aforementioned structures, wherein the organic light emitting layer 22 of the pixel island area 100 is provided in the pixel opening area and the cathode 23 is provided on the organic light emitting layer 22; the organic light emitting layer 22 and the cathode 23 of the connection bridge area 200 cover the isolation dam 25; the organic light emitting layer 22 and the cathode 23 of the hole area 300 are separated on the sidewall of the composite insulation layer facing the aperture;
the encapsulation layer 24 covering the aforementioned structures, wherein the encapsulation layer 24 covers the cathode 13 in the pixel island area 100; the encapsulation layer 24 is provided on the cathode 23 in the connection bridge area 200; the encapsulation layer 24 is provided on the cathode 23 and wraps the composite insulation layer and a side of the base substrate 10 close to the aperture 301 in the hole area 300;
wherein the composite insulation layer includes the first end face facing the aperture 301, the first barrier layer 102 includes the second end face facing the aperture 301, the buffer layer 103 includes the third end face facing the aperture 301, and the second barrier layer 104 includes the fourth end face facing the aperture 301;
In the direction parallel to the base substrate, the distance between the second end face and the first end face is smaller than the distance between the third end face and the first end face, the distance between the fourth end face and the first end face is smaller than the distance between the third end face and the first end face, the third end face is provided as the groove bottom of the barrier groove 106, and the opposite surfaces of the first barrier layer 102 and the second barrier layer 104 are provided as sidewalls of the barrier groove 106.
In the above embodiments, the isolation dam and the planarization layer may be provided in the same layer, or the isolation dam may include a first support layer and a second support layer which are stacked, wherein the first support layer and the planarization layer are formed by a same patterning process, and the second support layer and the pixel definition layer are formed by same patterning process.
As shown in
In an example, a length L2 of the barrier eave 107 ranges from about 0.2 microns to 2 microns, a thickness of the buffer layer 103 ranges from about 0.2 microns to 2 microns, and the length of the barrier eave 107 may be understood as a distance by which the second end face protrudes beyond the first end face. Thus, during the preparation process, a spacing between the barrier eave 107 and the rigid substrate 2 ranges from about 0.2 microns to 2 microns, forming a deeper and narrower groove structure, which can restrict deposition of the inorganic encapsulation thin film under the barrier eave 107, thereby forming the fracture zone of the encapsulation layer 24.
The technical solution of the display substrate of this exemplary embodiment is exemplarily described below by an example of the preparation process of the display substrate. The preparation process of the display substrate may use the following two preparation processes.
In an embodiment, the first preparation process:
(1) A base substrate 10 is prepared on a rigid substrate 2.
A buffer thin film and a first barrier thin film are deposited on the rigid substrate 2, and the first barrier thin film is patterned by a patterning process. As shown in
Subsequently, a first flexible base substrate thin film is coated on the base substrate on which the above patterns are formed, and cured into a film to form a first flexible base substrate layer 101. As shown in
Subsequently, a second barrier thin film is deposited on the base substrate on which the above patterns are formed, and the second barrier thin film is patterned by a patterning process to form a second barrier layer 104, as shown in
Subsequently, a second flexible base substrate thin film is coated on the base substrate on which the above patterns are formed and cured into a film to form a second flexible base substrate layer 105, as shown in
(2) Patterns of a drive structure layer and a connection line are prepared on the base substrate. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(3) A planarization layer is formed on the base substrate on which the above patterns are formed. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(4) Forming a pattern of an anode on the base substrate on which the above patterns are formed. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(5) Forming a pixel definition layer and an isolation dam on the base substrate on which the above patterns are formed, namely the structure as shown in
(6) Patterning a fourth insulation layer 17 on the base substrate on which the above patterns are formed by a patterning process to form a pattern of a third aperture k8, as shown in
(7) Etching the first flexible base substrate layer 101 and the second flexible base substrate layer 105 on the base substrate on which the above patterns are formed. As shown in
(8) Sequentially evaporating an organic light emitting material and a cathode metal thin film on the base substrate on which the above patterns are formed to form patterns of an organic light emitting layer 22 and a cathode 23. As shown in
(9) Depositing an inorganic encapsulation thin film on the base substrate on which the above patterns are formed. As shown in
(10) Forming a display substrate 1 as shown in
As can be seen from the preparation process of the display substrate of the present exemplary embodiment, as shown in
In another embodiment, the second preparation process is:
(1) A base substrate 10 is prepared on a rigid substrate 2.
As shown in
Subsequently, a first barrier thin film is deposited on the buffer layer 103 to form a first barrier layer 102.
Subsequently, a first flexible base substrate thin film is coated on the first barrier layer 102, and cured into a film to form a first flexible base substrate layer 101.
Subsequently, a second barrier thin film is deposited on the first flexible base substrate layer 101 to form a second barrier layer 104.
Subsequently, a second flexible base substrate thin film is coated on the second barrier layer 104, and cured into a film to form a second flexible base substrate layer 105.
In an exemplary embodiment, thicknesses of the first flexible base substrate layer and the second flexible base substrate layer range from about 2 microns to 10 microns.
(2) Patterns of a drive structure layer and a connection line are prepared on the base substrate. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(3) Planarization layer is formed on the base substrate on which the above patterns are formed. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(4) A pattern of an anode is formed on the base substrate on which the above patterns are formed. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(5) A pixel definition layer and an isolation dam are formed on the base substrate on which the above patterns are formed. For the relevant preparation process, reference may be made to the preparation process of the previous embodiments, which will not be repeated here.
(6) A fourth insulation layer is formed on the base substrate on which the above patterns are formed by a patterning process. As shown in
(7) The second flexible base substrate layer 105 is etched on the base substrate on which the above patterns are formed. As shown in
(8) The second barrier layer 104 is etched on the base substrate on which the above patterns are formed. As shown in
(9) The first flexible base substrate layer 101 is etched on the base substrate on which the above patterns are formed. As shown in
In an exemplary embodiment, steps (7) to (9) may be completed in a single etching, that is, the second flexible base substrate layer, the second barrier layer and the first flexible base substrate layer are etched in a single etch process.
(10) The first barrier layer 102 is patterned on the base substrate on which the above patterns are formed by the patterning process. As shown in
(11) The buffer layer 103 is etched on the base substrate on which the above patterns are formed. As shown in
(12) An organic light emitting material and a cathode metal thin film are sequentially evaporated on the base substrate on which the above patterns are formed to form patterns of an organic light emitting layer 22 and a cathode 23. As shown in
(13) An inorganic encapsulation thin film is deposited on the base substrate on which the above patterns are formed. As shown in
(14) A display substrate 1 as shown in
As can be seen from that preparation process of the display substrate of the present exemplary embodiment, due to the barrier of the barrier eave 107 and the continuous deposition of the inorganic encapsulation thin film, the hole diameter of the via hole k13 is gradually reduced, and a small amount of the inorganic encapsulation thin film is deposited in the inner enlarging hole k14, that is, the thickness of the encapsulation layer within the inner enlarging hole k14 is small or even discontinuous, and prone to breakage, thus forming a fracture area A by the encapsulation layer 24 formed under the barrier eave 107, and during a process of lifting off of the base substrate 10 from the rigid substrate 2, the lift-off will be cut off in the fracture zone, thus preventing the encapsulation layer 24 from being lifted off, thereby improving the reliability of the encapsulation layer and prolonging the service life of the display substrate.
An embodiment of the present disclosure further provides a method for preparing a display substrate, including:
forming multiple pixel island areas separated from each other, multiple hole areas and a connection bridge area connecting the multiple pixel island areas on a base substrate, wherein the base substrate of a hole area is provided with an aperture, and a side of the base substrate close to the aperture is provided with a barrier structure;
forming an encapsulation layer, wherein the encapsulation layer covers a sidewall of the base substrate close to the aperture, and the barrier structure is configured to form a fracture zone on the encapsulation layer that can break when the base substrate is lifted off from the rigid substrate.
In an exemplary embodiment, forming the multiple pixel island areas separated from each other, the multiple hole areas and the connection bridge area connecting the multiple pixel island areas on the base substrate includes:
forming a first flexible base substrate layer;
sequentially depositing a first barrier thin film, a buffer thin film and a second barrier thin film on the first flexible base substrate layer, and patterning the second barrier thin film by a patterning process to form a first barrier layer, a buffer layer, a second barrier layer and a first opening which are stacked, wherein the first opening is provided in a hole area and exposes the first flexible base substrate layer;
etching the buffer layer, with respect to surfaces of the first barrier layer and the second barrier layer facing the first opening, a surface of the buffer layer facing the first opening is recessed in a direction away from the first opening to form a barrier groove with a notch facing the first opening, a depth of the barrier groove ranges from 0.2 microns to 2 microns, and a width of the barrier groove ranges from 0.2 microns to 2 microns.
In an exemplary embodiment, forming the multiple pixel island areas separated from each other, the multiple hole areas and the connection bridge area connecting the multiple pixel island areas on the base substrate includes:
forming a buffer layer on a rigid substrate;
depositing a first barrier thin film on the buffer layer, patterning the first barrier thin film by a patterning process to forming a first barrier layer and a first aperture, wherein the first aperture is located in the hole area, the buffer layer and the first barrier layer within the first aperture are etched away to expose the rigid substrate, the first aperture includes a first hole diameter area formed in the first barrier layer and a second hole diameter area formed in the buffer layer, a hole diameter of the first hole diameter area is smaller than a hole diameter of the second hole diameter area, a barrier eave is formed at the corresponding position of the first barrier layer and the second hole diameter area, and the barrier eave forms a barrier structure.
In an exemplary embodiment, forming the multiple pixel island areas separated from each other, the multiple hole areas and the connection bridge area connecting the multiple pixel island areas on the base substrate includes:
forming a buffer layer on a rigid substrate;
depositing a first barrier thin film on the buffer layer, and patterning the first barrier thin film by a patterning process to form a first barrier layer and a via hole, wherein the via hole is located in the hole area, the via hole is an annular hole, the first barrier layer within the via hole is etched away to expose the buffer layer, and the hole diameter of the via hole ranges between 0.2 microns and 2 microns; and
etching the buffer layer to form an inner enlarging hole, wherein the inner enlarging hole is formed in the hole area and corresponds to the position of the via hole, the buffer layer within the inner enlarging hole is etched away to expose the rigid substrate, the hole diameter of the inner enlarging hole is larger than that of the via hole, a barrier eave is formed at the position of the first barrier layer on two sides of the via hole corresponding to the inner enlarging hole, and the barrier eave forms a barrier structure.
An embodiment of the present disclosure further provides a display apparatus including the display substrate of the aforementioned embodiments.
The display apparatus may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, or a navigator.
Although the embodiments disclosed in the present disclosure are as above, the described contents are only embodiments used for convenience of understanding the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art to which the present disclosure pertains may make any modification and variation in implementation forms and details without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of the present disclosure is still subject to the scope defined by the appended claims.
Number | Date | Country | Kind |
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202010973170.3 | Sep 2020 | CN | national |
The present application is a U.S. National Phase Entry of International PCT Application No. PCT/CN2021/111580, having an international filing date of Aug. 9, 2021, which claims priority to Chinese patent application No. 202010973170.3, entitled “display substrate, preparation method therefor, and display apparatus”, filed to the CNIPA on Sep. 16, 2020, and the contents disclosed in the above-mentioned applications are hereby incorporated as a part of this application.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2021/111580 | 8/9/2021 | WO |