Patent Grant
12213356
The present application is a U.S. National Phase of International Application No. PCT/CN2021/097448, entitled “SPLICING DISPLAY UNIT AND DISPLAY SCREEN”, and filed on May 31, 2021. The entire contents of each of the above-listed applications are hereby incorporated by reference for all purposes.
The present application relates to the field of display technologies, and in particular, to display substrates and display devices.
In the related art, Organic Light Emitting Diode (OLED) display substrates have a wide range of applications in fields of smart phones, televisions, VR (Virtual Reality) devices, wearable devices, etc. due to their excellent display effect, and characteristics such as thinness, flexibility, excellent shock resistance, and suitability for wearable products. As requirements on screen-to-body ratios of display substrates of terminal devices with cameras, such as mobile phones, is getting higher and higher, disposing the cameras under the display substrates is one of the best solutions to meet such requirements. However, disposing the cameras under the display substrates places higher requirements on the performance of the display substrates, especially on their light transmittance. High light transmittance of regions for enabling the cameras to capture images on the display substrates is a basic condition for applying this solution. Therefore, how to improve the light transmittance of the display substrates is a technical problem that needs to be solved.
The present disclosure provides display substrates and display devices.
According to a first aspect of examples of the present disclosure, there is provided a display substrate, including: a display region including a first display sub-region and a second display sub-region, where a light transmittance of the first display sub-region is higher than that of the second display sub-region; the display substrate further including: a plurality of first-type sub-pixels and a plurality of power lines, where
In an example, the plurality of first-type sub-pixels are divided into a plurality of sub-pixel groups, and a sub-pixel group includes at least one of: at least two adjacent first-type sub-pixels in the row direction or at least two adjacent first-type sub-pixels in the column direction.
In an example, a sub-pixel group includes two adjacent first-type sub-pixels in the row direction and two adjacent first-type sub-pixels in the column direction.
In an example, in a same row of sub-pixel groups, a distance between two adjacent sub-pixel groups is higher than or equal to a width of the sub-pixel group in the row direction;
In an example, orthographic projections of sub-pixel groups in an (i+2)th row on sub-pixel groups in an ith row are located outside orthographic projections of sub-pixel groups in an (i+1)th row on the sub-pixel groups in the ith row, orthographic projections of sub-pixel groups in an (i+3)th row on the sub-pixel groups in the ith row overlaps the orthographic projections of sub-pixel groups in the (i+1)th row on the sub-pixel groups in the ith row, and the orthographic projections of sub-pixel groups in the (i+3)th row on the sub-pixel groups in the ith row are located outside the orthographic projections of sub-pixel groups in the (i+2)th row on the sub-pixel groups in the ith row, where i is a positive integer;
In an example, the number of the first-type power lines is smaller than the number of rows of the array.
In an example, the number of the first-type power lines is equal to 0.25 time the number of rows of the array, pixel circuits of first-type sub-pixels in a same sub-pixel group are connected to just a same first-type power line, and the same first-type power line is connected to pixel circuits of first-type sub-pixels in sub-pixel groups in two adjacent rows.
In an example, the number of the second-type power lines is smaller than the number of columns of the array.
In an example, the number of the second-type power lines is equal to 0.5 time the number of columns of the array, and the number of the second-type power lines is equal to a number of columns of the sub-pixel groups;
In an example, a first-type power line exists between pixel circuits of first-type sub-pixels in sub-pixel groups in two adjacent rows, and the pixel circuits of the first-type sub-pixels in the sub-pixel groups in two adjacent rows are connected to a same first-type power line; pixel circuits of first-type sub-pixels in a same sub-pixel group are connected to two adjacent first-type power lines.
In an example, the number of the second-type power lines is 0.
In an example, the plurality of power lines further include third-type power lines, and the third-type power lines are connected to at least one type of the first-type power lines or the second-type power lines;
In an example, the third-type power lines have a ring shape.
In an example, when the third-type power lines are connected to the first-type power lines and the second-type power lines, the third-type power lines include first conductive portions and second conductive portions, the first conductive portions are connected to the second conductive portions, the first conductive portions extend along the row direction, and the second conductive portions extend along the column direction; the first-type power lines include third conductive portions, and the third conductive portions extend along the row direction; the second-type power lines extend along the column direction; the first conductive portions are connected to the third conductive portions, and the second-type power lines are connected to the first conductive portions or the second conductive portions;
In an example, a sub-pixel group includes three adjacent first-type sub-pixels in the row direction.
In an example, the number of the first-type power lines is equal to the number of rows of the array;
In an example, the number of the second-type power lines is smaller than the number of columns of the array.
In an example, the number of the second-type power lines is equal to ⅓ times the number of columns of the array, and the number of the second-type power lines is equal to a number of columns of the sub-pixel groups;
In an example, the second display sub-region includes a plurality of second-type sub-pixels, and the plurality of second-type sub-pixels are arranged in an array along the row direction and the column direction;
In an example, the plurality of power lines further include fourth power lines and fifth power lines, the fourth power lines are configured to be connected to pixel circuits of the second-type sub-pixels arranged along the row direction, and the fifth power lines are configured to be connected to pixel circuits of the second-type sub-pixels arranged along the column direction;
According to a second aspect of the examples of the present disclosure, there is provided a display device, including the above-described display substrate and photosensitive elements, where projections of the photosensitive elements on the display substrate are located within a first display sub-region.
In order to make the above objectives, features and advantages of the present disclosure more clearly understood, specific examples of the present disclosure will be described in detail below with reference to the accompanying drawings.
An example of the present disclosure provides a display substrate. A display substrate 1, as shown in
In this example, as shown in
In this example, the plurality of first-type sub-pixels 21 and the plurality of power lines VDD are located in the first display sub-region 111. The plurality of first-type sub-pixels 21 are arranged in an array along a row direction X and a column direction Y. The first-type sub-pixel 21 includes a light emitting element and a pixel circuit for driving the light emitting element to emit light. A plurality of power lines 22 are connected to one another. The plurality of power lines 22 include at least one type of first-type power lines 221 or second-type power lines 222. The first-type power lines 221 are configured to be connected to pixel circuits of the first-type sub-pixels 21 arranged along the row direction X. The second-type power lines 222 are configured to be connected to pixel circuits of the first-type sub-pixels 21 arranged along the column direction Y A sum of a number of the first-type power lines 221 and a number of the second-type power lines 222 is smaller than a sum of a number of rows and a number of columns of the array.
In this example, the plurality of power lines in the first display sub-region 111 include at least one type of the first-type power lines 221 or the second-type power lines 222, and the sum of the number of the first-type power lines 221 and the number of the second-type power lines 222 is smaller than the sum of the number of rows and the number of columns of the array formed by the first-type sub-pixels 21, where the first-type power lines 221 are configured to be connected to the pixel circuits of the first-type sub-pixels 21 arranged along the row direction X, and the second-type power lines 222 are configured to be connected to the pixel circuits of the first-type sub-pixels 21 arranged along the column direction Y Therefore, there is at least one row of first-type sub-pixels 21 near which no first-type power lines 221 are disposed, and there is at least one column of first-type sub-pixels 21 near which no second-type power lines 222 are disposed, which can reduce the number and the occupied area of the power lines, and can be beneficial to improve the light transmittance of the first display sub-region 111.
The display substrate provided by examples of the present disclosure has been briefly introduced above. The display substrate provided by the examples of the present disclosure will be described in detail below.
An example of the present disclosure provides a display substrate. As shown in
In this example, as shown in
In this example, as shown in
In this example, as shown in
In this example, as shown in
In this example, the second display sub-region 112 includes a plurality of second-type sub-pixels, and the plurality of second-type sub-pixels are arranged in an array along the row direction X and the column direction Y A density of the first-type sub-pixels 21 in the first display sub-region 111 is smaller than that of the second-type sub-pixels in the second display sub-region 112. For example, the density of the first-type sub-pixels 21 in the first display sub-region 111 may be ½ of that of the second-type sub-pixels in the second display sub-region 112.
In this example, as shown in
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For example, when i is 1, orthographic projections of sub-pixel groups 31 in a third row on sub-pixel groups 31 in a first row are located outside orthographic projections of sub-pixel groups 31 in a second row on the sub-pixel groups 31 in the first row, orthographic projections of sub-pixel groups 31 in a fourth row on the sub-pixel groups 31 in the first row overlaps the orthographic projections of sub-pixel groups 31 in the second row on the sub-pixel groups 31 in the first row, and the orthographic projections of sub-pixel groups 31 in the fourth row on the sub-pixel groups 31 in the first row are located outside the orthographic projections of sub-pixel groups 31 in the third row on the sub-pixel groups 31 in the first row.
In this example, as shown in
For example, when j is 1, orthographic projections of sub-pixel groups 31 in a third column on sub-pixel groups 31 in a first column are located outside orthographic projections of sub-pixel groups 31 in a second column on the sub-pixel groups 31 in the first column, orthographic projections of sub-pixel groups 31 in a fourth column on the sub-pixel groups 31 in the first column overlaps the orthographic projections of sub-pixel groups 31 in the second column on the sub-pixel groups 31 in the first column, and the orthographic projections of sub-pixel groups 31 in the fourth column on the sub-pixel groups 31 in the first column are located outside the orthographic projections of sub-pixel groups 31 in the third column on the sub-pixel groups 31 in the first column.
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In this example, a sum of the number of the first-type power lines 221 and the number of the second-type power lines 222 is smaller than a sum of the number of rows and the number of columns of the array. Therefore, there is at least one row of first-type sub-pixels 21 near which no first-type power lines 221 are disposed, and at least one column of first-type sub-pixels 21 near which no second-type power lines 222 are disposed, which reduces the number and an occupied area of the power lines, and is beneficial to improve the light transmittance of the first display sub-region 111.
In this example, the plurality of power lines 22 further include fourth power lines and fifth power lines. The fourth power lines and the fifth power lines may be located in the second display sub-region 112. The first-type power lines 221, the second-type power lines 222, the third-type power lines 223, the fourth power lines, and the fifth power lines are connected to one another.
In this example, the fourth power lines are configured to be connected to pixel circuits of the second-type sub-pixels arranged along the row direction X, and the fifth power lines are configured to be connected to pixel circuits of the second-type sub-pixels arranged along the column direction Y.
In this example, in the second display sub-region, a number of the fourth power lines is the same as a number of rows of the array. Pixel circuits of second-type sub-pixels in the same row are connected to the same fourth power line, and the same fourth power line is connected to pixel circuits of second-type sub-pixels in the same row.
In this example, in the second display sub-region, a number of the fifth source lines is the same as a number of columns of the array. Pixel circuits of second-type sub-pixels in the same column are connected to the same fifth power line, and the same fifth power line is connected to pixel circuits of second-type sub-pixels in the same column.
In this example, a density of the power lines in the first display sub-region 111 is smaller than that in the second display sub-region 112. Since the density of the power lines in the first display sub-region 111 is smaller than that in the second display sub-region 112, the light transmittance of the first display sub-region 111 can be improved.
A structure of the display substrate in this example has been shown above briefly in
A structure of a pixel circuit will be first introduced. As shown in
As shown in
In this example, the drive transistor T1 is used to provide a drive current for the light emitting element D. A gate electrode of the drive transistor T1 is connected to a first electrode of the capacitor C, a first electrode of the threshold compensation transistor T3, and a second electrode of the first reset transistor T6. A first electrode of the drive transistor T1 is connected to a second electrode of the threshold compensation transistor T3 and a second electrode of the first light emission control transistor T5. A second electrode of the drive transistor T1 is connected to a first electrode of the second light emission control transistor T4 and a second electrode of the data writing transistor T2. A first electrode of the data writing transistor T2 is configured to be electrically connected to a data line Vd to receive data signals. A gate electrode of the data writing transistor T2 is electrically connected to a first scan signal line Ga1 to receive scan signals, and the first electrode of the data writing transistor T2 is electrically connected to the data line Vd to receive the data signals. A gate electrode of the threshold compensation transistor T3 is electrically connected to a second scan signal line Ga2 to receive compensation control signals. A gate electrode of the second light emission control transistor T4 is electrically connected to a first light emission control signal line EM1 to receive first light emission control signals, and a second electrode of the second light emission control transistor T4 is connected to a second electrode of the capacitor and the power line VDD. A gate electrode of the first light emission control transistor T5 is electrically connected to a second light emission control signal line EM2 to receive second light emission control signals, and a first electrode of the first light emission control transistor T5 is connected to a first electrode of the second reset transistor T7 and a positive electrode of the light emitting element D. A gate electrode of the first reset transistor T6 is electrically connected to a first reset control signal line Rst1 to receive first sub-reset control signals, and a first electrode of the first reset transistor T6 is electrically connected to a first reset power supply terminal Vinit1 to receive first reset signals. A gate electrode of the second reset transistor T7 is electrically connected to a second reset control signal line Rst2 to receive second sub-reset control signals, and a second electrode of the second reset transistor T7 is electrically connected to a second reset power supply terminal Vinit2 to receive second reset signals.
In this example, the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emission control transistor T4, the first light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7 are P-type transistors, their first electrodes are source electrodes, and their second electrodes are drain electrodes. In other examples, one or more of the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emission control transistor T4, the first light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7 may be N-type transistors.
In this example, a voltage of power supply signals provided by the power line VDD is higher than that provided by the power line VSS. The voltage of the power supply signals provided by the power line VDD is a positive voltage, and the voltage of the power supply signals provided by the power line VSS may be 0 or a negative voltage. For example, a voltage of power supply signals provided by the power line VSS when being grounded is 0. However, in other examples, the voltage of the power supply signals provided by the power line VDD may be smaller than that provided by the power line VSS.
In this example, the first light emission control signals may be the same as the second light emission control signals, and the gate electrode of the second light emission control transistor T4 and the gate electrode of the first light emission control transistor T5 may be connected to the same light emission control signal line EM, where the light emission control signal line EM is the first light emission control signal line EM1 or the second light emission control signal line EM2. Similarly, the first sub-reset control signals may be the same as the second sub-reset control signals, and the gate electrode of the first reset transistor T6 and the gate electrode of the second reset transistor T7 may be connected to the same reset control signal line Rst, where the reset control signal line Rst may be the first reset control signal line Rst1 or the second reset control signal line Rst2. When the first reset signals are the same as the second reset signals, the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 are connected to the same reset signal line VINIT.
The structure of a pixel circuit has been described above. Structures of layers of pixel circuits will be described below with reference to
As shown in
It should be noted that an active layer may include an integrally formed low-temperature polysilicon layer, and a source region and a drain region may be subjected to conductor processing by doping or the like to achieve electrical connection between structures. That is, an active semiconductor layer of transistors of each first-type sub-pixel 21 is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source region and a drain region) and an active layer pattern. Active layers of different transistors are separated by doped structures.
In this example, the active semiconductor layers 61 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the source regions and the drain regions may be regions doped with N-type or P-type impurities.
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In this example,
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In this example,
It should be noted that a horizontal conductive portion does not refer to that the conductive portion extends along a row direction X, but is used to be connected with pixel circuits of first-type sub-pixels 21 arranged along the row direction X. A vertical conductive portion may refer to that the conductive portion extends along a column direction Y.
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An example of the present disclosure provides a display substrate. As shown in
In this example, as shown in
In this example, as shown in
In this example, a density of power lines in a first display sub-region 111 is smaller than that in a second display sub-region 112. Since the density of the power lines in the first display sub-region 111 is smaller than that in the second display sub-region 112, a light transmittance of the first display sub-region 111 can be improved.
An example of the present disclosure provides a display substrate. As shown in
In this example, as shown in
In this example, a density of first-type sub-pixels 21 in a first display sub-region 111 is smaller than that of second-type sub-pixels in a second display sub-region 112. In this way, a light transmittance of the first display sub-region 111 can be improved.
In this example, as shown in
In this example, a number of second-type power lines 222 is smaller than a number of columns of the array. In this way, the number of second-type power lines 222 can be reduced, and the light transmittance of the first display sub-region 111 can be improved.
In this example, as shown in
In this example, as shown in
An example of the present disclosure provides a display device, which includes photosensitive elements, and further includes a display substrate according to any of the above examples. Projections of the photosensitive elements on the display substrate are located within a first display sub-region 111.
In this example, the photosensitive elements may be image sensors, ambient light sensors or distance sensors, but they are not limited thereto.
It should be noted that the display device in this example may be any product or component having a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.
It should be pointed out that in the drawings, sizes of layers and areas may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on other element, or an intermediate layer may be present. In addition, it will be understood that when an element or layer is referred to as being “below” another element or layer, it can be directly below other element, or more than one intermediate layer or element may be present. It will also be understood that when a layer or element is referred to as being “between” two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may be present. Similar reference signs indicate similar elements throughout.
In the present disclosure, terms “first” and “second” are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance. Terms “plurality” and “multiple” refer to two or more, unless expressly defined otherwise.
Other embodiments of the present disclosure will be readily apparent to those skilled in the art after considering the specification and practicing the contents disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principle of the present disclosure and include common knowledge or conventional technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as illustrative only. The true scope and spirit of the present disclosure are pointed out by the following claims.
It is to be understood that the present disclosure is not limited to the precise structures that have described and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the disclosure is to be limited only by the appended claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/097448 | 5/31/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2022/252064 | 12/8/2022 | WO | A |
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| Entry |
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| PCT/CN2021/097448 international search report and written opinion. |
| EP219434404 extended European search report. |
| CN202180001369.2—First Office Action mailed on Oct. 24, 2024, 24 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20240155890 A1 | May 2024 | US |
