Patent Application
20190325808
The disclosure generally relates to a display system, a driver, and a method thereof, and more particularly relates to display system, a driver, and a method thereof that are capable of biasing an operational amplifier according to a random bit stream.
Operational amplifiers are a basic component of electronic circuits and are applied to a wide variety of purposes. Real operational amplifiers are suffered by voltage offsets which cause drifts in the operational amplifiers. The voltage offset may be classified to a systematic voltage offset and a random voltage offset according to factors that generate the voltage offsets such as manufacturing process, a circuit design, a size and type of transistors and the operating temperature. Since an operational amplifier may produce the output signals that are typically hundreds or thousands of times larger than the difference between its input terminals, the voltage offsets may severely influence to the output signal of the operational amplifier.
For example, in a field of display panel, the voltage offsets of the operational amplifiers may cause the errors or noises on the driving signals, and may create visual artifacts on the display.
Therefore, it would be desirable to mitigate the influences of voltage offsets of the operational amplifier, and to achieve effect of smooth displaying on the display panel.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present disclosure.
A display system, a driver of a display panel, and a method thereof are introduced herein.
The driver of the display panel includes an operational amplifier and a bias control circuit. The operational amplifier outputs an output signal to drive the display panel according to a bias voltage. The bias control circuit is coupled to the operational amplifier and is configured to output the bias voltage to the operational amplifier. The bias control circuit may generate the bias voltage according to a random bit stream.
The bias voltage may be used to adjust a systematic voltage offset of the operational amplifier; and the bias voltage is changed according to signal levels of the random bit stream.
The method adapted to a driver of a display panel includes steps of providing a random bit stream; generating a bias voltage according to the random bit stream, wherein the bias voltage is configured to bias an operational amplifier; and outputting an output signal according to the bias voltage, wherein the output signal is configured to drive the display panel.
The display system includes a display panel and a driver. The display panel is configured to display image data according to an output signal. The driver is coupled the display panel, and the driver includes an operational amplifier and a bias control circuit. The operational amplifier outputs an output signal to drive the display panel according to a bias voltage. The bias control circuit is coupled to the operational amplifier and is configured to output the bias voltage to the operational amplifier. The bias control circuit may generate the bias voltage according to a random bit stream.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless limited otherwise, the terms “connected,” “coupled,” and “mounted,” and variations thereof herein are used broadly and encompass direct and indirect connections, couplings, and mountings.
Referring to
The driver 120 is coupled to the display panel 110 and configured to drive the display panel to display data according to at least one driving signal. Also, the driver 120 may receive at least one sensing signal. The driver circuit 120 may include a signal receiver 121, a digital-to-analog converter (DAC) 123, a driving circuit 125, a signal transmitter 122, an analog-to-digital converter (ADC) 124 and a sampler 126. The signal receiver 121 is configured to receive at least one digital signal from the image processing circuit 130 through the driving line DL. The DAC 123 is coupled to the signal receiver 121 and is configured to convert the at least one digital signal received from the signal receiver 121 to an analog signal and to output the analog signal to the driving circuit 125. The driving circuit 125 receives the analog signal from the DAC 123 and then outputs the analog signal (e.g., driving signals) to the display panel 110. The driver circuit 120 may have a plurality of channels, where each of the channel may include an operational amplifier.
The sampler 126 is coupled to the display panel 110 to receive at least one analog signal (e.g., sensing signal) from the display panel 110. The ADC 124 is coupled to the sampler 126 and is configured to converts the at least one analog signal received from the sampler 126 to a digital signal. The digital signal is provided to the signal transmitter 122, and then outputted to the image processing circuit 130 through the sensing line SL. The image processing circuit 130 is configured to perform various calculation operations related to images and signals. The disclosure is not limited to any specific structure, type or architecture of the image processing circuit 130.
Referring to
It should be noted that the operation amplifier 203 may have voltage offsets which include a systematic voltage offset and a random voltage offset. The systematic voltage offset is caused by mismatches of cascaded stages of the operational amplifier 203 and is based on imperfect circuit designs; and random voltage offset is caused by imperfect manufacturing process such as an error in the size of a transistor or variations in threshold voltage.
The operational amplifier 203 is coupled to the bias control circuit 201. The bias control circuit 201 receives a signal S and generate a bias voltage VB according to the received signal S to bias the operational amplifier 203. In an embodiment of the disclosure, the signal S is a random bit stream which has different level values (e.g., high level value and low level value). The bias control circuit 201 may generate the bias voltage VB according to the level values of the random bit stream.
The random bit stream may be generated using linear feedback shift registers (LFSRs), but any other method and/or circuit for generating the random bit stream falls within the scope of the disclosure. Beside a random bit stream, the signal S can be a specific signal or any kind of signal that is used for the bias control circuit 201 to generate the bias voltage VB. In an embodiment of the disclosure, the bias signal S may be used for biasing ratio control of the operational amplifier 203.
Referring to
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The bias circuit 301 may further include a transistor M1′ which is coupled to another current source I. The bias circuit 301 receives a signal S2 which may be a random bit stream and generates a bias voltage VB2 according level of the signal S2. The signals S1 and S2 provided to the bias circuit 301 may be the same or different; and the current sources of the bias circuit 301 may be the same or different.
The operational amplifier 303 may include a differential difference amplifier which includes transistors M2 to M4. The drain terminal of the transistor M4 is coupled to the source terminals of transistor M2 and M3; the source terminal of the transistor M4 is coupled to the ground; and the control terminal of the transistor M4 is coupled to the bias circuit 301 to receive the bias voltage VB1.
The differential difference amplifier of the operational amplifier 303 may further include transistors M2′ to M4′. The drain terminal of the transistor M4′ is coupled to the source terminals of transistor M2′ and M3′; the source terminal of the transistor M4′ is coupled to the supply voltage; and the control terminal of the transistor M4 is coupled to the bias circuit 301 to receive the bias voltage VB2.
As shown in
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In
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From the above embodiments, a signal S (e.g., a random bit stream) is provided to a bias control circuit so that the bias control circuit generates a bias voltage according to the signal S. The bias voltage is used to bias an operational amplifier, thereby adjusting a systematic voltage offset of the operational amplifier. In this way, the issues due to voltage offsets of the operational amplifier are mitigated, and the display quality of the display panel is improved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
