Patent Grant
10008151
The present disclosure relates to a display unit having a current-driving display element, to a drive unit and a driving method used in such a display unit, and to an electronic apparatus including such a display unit.
In recent years, in a field of display units performing image display, a display unit (an organic electro luminescence (EL) display unit) using, as a light emitting element, a current-driving optical element whose light emission luminance is varied in response to a value of a flowing current, for example, an organic EL element, has been developed and commercialization thereof is progressing. Unlike a liquid crystal element or the like, the light emitting element is a self light-emitting element, and a light source (a backlight) is unnecessary. Therefore, the organic EL display unit has characteristics of high visibility of an image, low power consumption, high response speed of an element, etc., as compared with a liquid crystal display unit demanding a light source.
In the display unit, drive circuits control pixels arranged in a matrix. For example, in PTL 1, a display panel including a pixel array section and a control line driving section that is configured of a shift register and a plurality of buffer circuits is disclosed. The control line drive section supplies a control signal to each pixel through a control line. Two or more voltages (VDD/VSS) are supplied to the buffer circuits, and one of these voltages is selected and output based on a set signal and a reset signal that are supplied from outside.
PTL 1: Japanese Unexamined Patent Application Publication No. 2009-223092
Incidentally, typically, an electronic circuit desirably has a simple configuration in terms of cost, arrangement area of circuits, flexibility of circuit layout, and the like, and a drive circuit in a display unit is also expected to have a simple configuration.
Therefore, it is desirable to provide a display unit, a drive unit, a driving method, and an electronic apparatus that are each adapted to achieve a simple circuit configuration.
A display unit according to an embodiment of the disclosure includes: a unit pixel, a switch, and a non-linear element. The switch is configured to perform ON-OFF control between a second terminal supplied with a DC signal and a third terminal connected to the unit pixel, based on a pulse signal applied to a first terminal. The non-linear element is interposed between the first terminal and the third terminal.
A drive unit according to an embodiment of the disclosure includes a switch and a non-linear element. The switch is configured to perform ON-OFF control between a second terminal supplied with a DC signal and a third terminal connected to the unit pixel, based on a pulse signal applied to a first terminal. The non-linear element is interposed between the first terminal and the third terminal.
A driving method according to an embodiment of the disclosure includes: performing ON-OFF control between a second terminal supplied with a DC signal and a third terminal connected to a unit pixel, based on a pulse signal applied to a first terminal; and performing non-linear operation between the first terminal and the third terminal.
An electronic apparatus according to an embodiment of the disclosure includes the above-described display unit, and examples of the electronic apparatus may include a television apparatus, a digital camera, a personal computer, a video camera, and a mobile terminal device such as a mobile phone.
According to the display unit, the drive unit, the driving method, and the electronic apparatus according to the respective embodiments of the disclosure, the signal is applied to the unit pixel based on the pulse signal. At this time, the switch is controlled to be turned on or turned off between the second terminal supplied with the DC signal and the third terminal connected to the unit pixel, based on the pulse signal applied to the first terminal, and non-linear operation is performed between the first terminal and the third terminal by the non-linear element.
According to the display unit, the drive unit, the driving method, and the electronic apparatus according to the respective embodiments of the disclosure, the switch that performs the ON-OFF control between the second terminal supplied with the DC signal and the third terminal connected to the unit pixel, based on the pulse signal applied to the first terminal, and the non-linear element that is interposed between the first terminal and the third terminal are provided. Therefore, it is possible to achieve a simple circuit.
Embodiments of the disclosure will be described in detail below with reference to drawings. Note that description thereof will be given in the following order.
1. First embodiment
2. Second embodiment
3. Application examples
The display section 10 is configured of a plurality of pixels Pix arranged in a matrix. Each of the pixels Pix includes red, green, and blue sub-pixels 11. The display section 10 includes a plurality of scan lines WSL and a plurality of power lines PL that extend in a row direction, and a plurality of data lines DTL that extend in a column direction. An end of each of the scan lines WSL, the power lines PL, and the data lines DTL is connected to the drive section 20. Each of the above-described sub-pixels 11 is disposed at an intersection of each of the scan lines WSL and each of the data lines DTL.
The write transistor WSTr and the drive transistor DRTr may be each configured of, for example, an N-channel metal oxide semiconductor (MOS) thin film transistor (TFT). A gate of the write transistor WSTr is connected to the scan line WSL, a source thereof is connected to the data line DTL, and a drain thereof is connected to a gate of the drive transistor DRTr and one end of the capacitor Cs. The gate of the drive transistor DRTr is connected to the drain of the write transistor WSTr and the one end of the capacitor Cs, a drain thereof is connected to the power line PL, and a source thereof is connected to the other end of the capacitor Cs and an anode of the organic EL element OLED, and the like.
The one end of the capacitor Cs is connected to the gate of the drive transistor DRTr and the like, and the other end thereof is connected to the source of the drive transistor DRTr and the like. One end of the capacitor Csub is connected to the anode of the organic EL element OLED, and the other end thereof is connected to a cathode of the organic EL element OLED. In other words, in this example, the capacitor Csub is connected in parallel to the organic EL element OLED. The organic EL element OLED is a light emitting element emitting light of color (red, green, or blue) corresponding to each of the sub-pixels 11, and the anode thereof is connected to the source of the drive transistor DRTr and the like, and the cathode thereof is supplied with a cathode voltage Vcath by the drive section 20.
The drive section 20 drives the display section 10 based on a picture signal Sdisp and a synchronization signal Ssync that are supplied from outside. The drive section 20 includes a picture signal processing section 21, a timing generation section 22, a scan line drive section 23, a power line drive section 26, and a data line drive section 27, as illustrated in
The picture signal processing section 21 performs predetermined signal processing on the picture signal Sdisp supplied from the outside to generate a picture signal Sdisp2. Examples of the predetermined signal processing may include gamma correction and overdrive correction.
The timing generation section 22 is a circuit that supplies a control signal to each of the scan line drive section 23, the power line drive section 26, and the data line drive section 27, based on the synchronization signal Ssync supplied from the outside, and controls these sections to operate in synchronization with one another.
The scan line drive section 23 sequentially applies a scan signal WS to the plurality of scan lines WSL according to the control signal supplied from the timing generation section 22, to sequentially select the sub-pixels 11 on the row basis.
The power line drive section 26 sequentially applies a power signal DS to the plurality of power lines PL according to the control signal supplied from the timing generation section 22, to control light emission operation and light extinction operation of the sub-pixels 11 on the row basis. The power signal DS transits between a voltage Vccp and a voltage Vini. As will be described later, the voltage Vini is a voltage to initialize the sub-pixels 11, and the voltage Vccp is a voltage to allow the current Ids to flow through the drive transistor DRTr to allow the organic EL element OLED to emit light.
The voltage generation section 31 generates the voltage Vccp. The voltage generation section 31 supplies the voltage Vccp to each of the drive circuits 33 through the wiring L1.
The shift register 32 generates a plurality of scan signals Ss that are used to select a pixel line to be driven, based on the control signal (not illustrated) supplied from the timing generation section 22. Each of the scan signals Ss corresponds to each of the pixel lines in the display section 10. Specifically, for example, k-th scan signal Ss(k) corresponds to k-th pixel line. Each of the scan signals Ss is a signal transiting between a high level voltage VH and a low level voltage VL. The low level voltage VL is a voltage (Vini−Vth) lower than the voltage Vini by an amount of a threshold voltage Vth of a transistor 35 (described later) of the drive circuit 33. For example, the shift register 32 may supply the scan signal Ss(k) to k-th drive circuit 33(k) through k-th wiring L2(k).
Each of the drive circuits 33 generates the power signal DS based on the voltage Vccp supplied from the voltage generation section 31 and the scan signal Ss supplied from the shift register 32. Each of the drive circuits 33 is provided corresponding to each of the pixel lines in the display section 10. Specifically, for example, the k-th drive circuit 33(k) generates k-th power signal DS(k) based on the voltage Vccp and the k-th scan signal Ss(k). Then, the drive circuit 33(k) applies the power signal DS(k) to the power line PL(k) in the k-th pixel line.
Each of the drive circuits 33 includes transistors 34 and 35. Each of the transistors 34 and 35 may be configured of, for example, an N-channel MOSTFT similar to the write transistor WSTr and the drive transistor DRTr. In the drive circuit 33(k), a gate of the transistor 34 is connected to a source of the transistor 35 and the wiring L2(k), a drain thereof is connected to the wiring L1, and a source thereof is connected to a drain and a gate of the transistor 35 and the power line PL(k). In the drive circuit 33(k), a drain of the transistor 35 is connected to the gate of the transistor 35, the source of the transistor 34, and the power line PL(k), the source thereof is connected to the gate of the transistor 34 and the wiring L2(k). In other words, the transistor 35 is so-called diode-connected. The transistor 34 is formed to have a channel width W larger than a channel width W of the transistor 35.
With this configuration, in the drive circuit 33(k), when the voltage of the scan signal Ss(k) is the high level voltage VH, the transistor 34 is turned on and the transistor 35 is turned off. Accordingly, the drive circuit 33(k) outputs the voltage Vccp as the power signal DS(k). In addition, when the voltage of the scan signal Ss(k) is the low level voltage VL, the transistor 34 is turned off and the transistor 35 is transiently turned on. Accordingly, the drive circuit 33(k) outputs the voltage Vini that is higher than the low level voltage VL (=Vini−Vth) by an amount of the threshold voltage Vth of the transistor 35, as the power signal DS(k).
The gate (a gate part GP) of each of the transistors 34 and 35 is configured of the lower layer metal M1, and the drain and the source of each of the transistors 34 and 35 are connected to the upper layer metal M2. The wiring L1 is formed of the upper layer metal M2 and is connected to the drain of the transistor 34. The wiring L2 is formed of the upper layer metal M2 in a part other than a part intersecting with the wiring L1, and is formed of the lower layer metal M1 in the part intersecting with the wiring L1. The wiring L2 is connected to the gate (the gate part GP) of the transistor 34, and is connected to the upper layer metal M2 that is connected to the source of the transistor 35, through a contact CT. The power line PL is formed of the upper layer metal M2, is connected to the source of the transistor 34 and the drain of the transistor 35, and is connected to the gate of the transistor 35 through a contact CT.
In
With this configuration, as will be described later, the drive section 20 performs correction (the Vth correction) to suppress influence of the element variation of the drive transistor DRTr to the image quality, on the sub-pixels 11. After that, the drive section 20 performs writing of the pixel voltage Vsig on the sub-pixels 11 and performs μ (mobility) correction different from the above-described Vth correction. Then, thereafter, the organic EL element OLED of each of the sub-pixels 11 emits light with luminance corresponding to the written pixel voltage Vsig.
Here, the sub-pixel 11 corresponds to a specific but non-limiting example of “unit pixel” in the disclosure. The capacitor Cs corresponds to a specific but non-limiting example of “first capacitor” in the disclosure. The capacitor Csub corresponds to a specific but non-limiting example of “second capacitor” in the disclosure. The organic EL element OLED corresponds to a specific but non-limiting example of “display element” in the disclosure. The transistor 34 corresponds to a specific but non-limiting example of “switch” in the disclosure. The transistor 35 corresponds to a specific but non-limiting example of “non-linear element” in the disclosure. The scan signal Ss corresponds to a specific but non-limiting example of “pulse signal” in the disclosure. The wiring L2 corresponds to a specific but non-limiting example of “first wiring” in the disclosure, and the wiring L1 corresponds to a specific but non-limiting example of “second wiring” in the disclosure. The high level voltage VH corresponds to a specific but non-limiting example of “first voltage” in the disclosure, and the low level voltage VL corresponds to a specific but non-limiting example of “second voltage” in the disclosure. The voltage Vini corresponds to a specific but non-limiting example of “third voltage” in the disclosure, and the voltage Vccp corresponds to a specific but non-limiting example of “fourth voltage” in the disclosure. The voltage Vofs corresponds to a specific but non-limiting example of “reset voltage” in the disclosure.
(Operation and Function)
Subsequently, operation and function of the display unit 1 according to the present embodiment is described.
(General Operation Outline)
First, with reference to
(Detailed Operation)
The scan line drive section 23 of the drive section 20 sequentially applies the scan signal WS having two pulses PP1 and PP2 to each of the scan lines WSL ((A) of
In this way, the drive section 20 drives the sub-pixels 11 in the k-th line during one horizontal period (for example, from timing t1 to timing t7), and drives the sub-pixels 11 in the (k+1)-th line during next horizontal period (for example, from timing t7 to timing t8). Then, drive section 20 drives all of the sub-pixels 11 of the display section 10 during one frame period.
The drive section 20 performs initialization of the sub-pixels 11 (initialization period P1), performs the Vth correction to suppress influence of the element variation of the drive transistor DRTr to the image quality (Vth correction period P2), and performs writing of the pixel voltage Vsig to the sub-pixels 11 and the μ correction (writing and μ correction period P3) during one horizontal period (1H). Then, thereafter, the organic EL element OLED of each of the sub-pixels 11 emits light with luminance corresponding to the written pixel voltage Vsig (emission period P4).
Here, the initialization period P1 corresponds to a specific but non-limiting example of “first sub-period” in the disclosure, the Vth correction period P2 corresponds to a specific but non-limiting example of “second sub-period” in the disclosure.
The detail thereof is described below.
First, the power line drive section 26 varies the power signal DS from the voltage Vccp to the voltage Vini at timing t0 prior to the initialization period P1 ((B) of
Next, the drive section 20 initializes the sub-pixels 11 during the period from the timing t1 to the timing t2 (initialization period P1). Specifically, at the timing t1, the data line drive section 27 sets the signal Sig to the voltage Vofs ((C) of
Next, the drive section 20 performs the Vth correction during the period from the timing t2 to the timing t3 (Vth correction period P2). Specifically, the power line drive section 26 varies the power signal DS from the voltage Vini to the voltage Vccp at the timing t2 ((B) of
Next, the scan line drive section 23 varies the voltage of the scan signal WS from high level to low level at the timing t3 ((A) of
Then, the drive section 20 performs writing of the pixel voltage Vsig to the sub-pixels 11 and performs the μ correction during the period from timing t5 to timing t6 (writing and μ correction period P3). Specifically, the scan line drive section 23 varies the voltage of the scan signal WS from low level to high level at the timing t5 ((A) of
Then, the drive section 20 allows the sub-pixels 11 to emit light during a period after the timing t6 (emission period P4). Specifically, the scan line drive section 23 varies the voltage of the scan signal WS from high level to low level at the timing t6 ((A) of
After that, in the display unit 1, after a predetermined period (one frame period) is elapsed, transition from the emission period P4 to the initialization period P1 occurs. The drive section 20 performs driving so as to repeat the series of operation.
In this way, in the display unit 1, both the Vth correction and the μ correction are performed. Therefore, it is possible to suppress degradation of image quality caused by element variation of the drive transistor DRTr. In addition, in the display unit 1, the source voltage Vs is allowed to increase according to the element variation of the organic EL element OLED during the emission period P4. Therefore, it is possible to suppress degradation of image quality caused by the element variation of the organic EL element OLED.
(Operation of Drive Circuit 33)
Next, detailed operation of the drive circuit 33 is described. The drive circuit 33 generates the power signal DS based on the voltage Vccp supplied from the voltage generation section 31 and the scan signal Ss supplied from the shift register 32.
First, the voltage of the scan signal Ss varies from the low level voltage VL to the high level voltage VH at timing t11 ((A) of
Then, the voltage of the scan signal Ss varies from the high level voltage VH to the low level voltage VL (=Vini−Vth) at timing t12 ((A) of
The drive circuit 33 repeats the above operation. As a result, each of the sub-pixels 11 connected to the power line PL repeats the series of operation from initialization to light emission.
As described above, in the display unit 1, the drive circuit 33 is configured using the transistor 34 that functions as a switch and the transistor 35 that functions as a non-linear element (diode). Therefore, it is possible to simplify the circuit configuration of the power line drive section 26 as will be described with comparative example.
Moreover, in the drive circuit 33, the channel width W of the transistor 34 is made larger than the channel width W of the transistor 35. Therefore, it is possible to facilitate driving of the sub-pixels 11, and to suppress the circuit area of the drive circuit 33. Specifically, the drive circuit 33 turns on the transistor 34 to supply a current to the sub-pixels 11 during the Vth correction period P2, the writing and μ correction period P3, and the emission period P4. In particular, during the emission period P4, the drive circuit 33 supplies the drive current allowing the organic EL element OLED to emit light. The drive current increases as the emission luminance of the organic EL element OLED is high. Therefore, the on resistance of the transistor 34 may be desirably sufficiently low, and the channel width W of the transistor 34 may be desirably wide. On the other hand, the drive circuit 33 applies the voltage Vini to the power line PL to set the source voltage Vs of the sub-pixels 11 to the voltage Vini, during the initialization period P1. In this case, the current transiently flows through the transistor 35 but the current does not flows through the transistor 35 constantly. Therefore, it is possible to decrease the channel width W of the transistor 35. This configuration facilitates driving of the sub-pixels 11 and makes it possible to suppress the circuit area of the drive circuit 33.
Also, as illustrated in
Moreover, as illustrated in
Next, a power line drive section 26R according to a comparative example is described. In the present comparative example, a voltage generation section 31R generates the voltages Vccp and Vini, and a drive circuit 33R selects and outputs one of the voltages Vccp and Vini. Other configurations thereof are similar to those in the present embodiment (
The voltage generation section 31R generates the voltage Vccp to supply the voltage Vccp to each of the drive circuits 33R thorough the wiring L1, and generates the voltage Vini to supply the voltage Vini to each of the drive circuits 33R through a wiring L3.
The shift register 32RA generates a plurality of scan signals SsA used to select a pixel line to be driven, based on the control signal (not illustrated) supplied from the timing generation section 22. For example, the shift register 32RA may supply the scan signal SsA(k) to k-th drive circuit 33R(k) through k-th wiring L2A(k). Likewise, the shift register 32RB generates a plurality of scan signals SsB used to select a pixel line to be driven, based on the control signal (not illustrated) supplied from the timing generation section 22. For example, the shift register 32RB may supply the scan signal SsB(k) to the k-th drive circuit 33R(k) through k-th wiring L2B(k).
Each of the drive circuits 33R generates the power signal DS, based on the voltages Vccp and Vini that are supplied from the voltage generation section 31R, the scan signal SsA supplied from the shift register 33RA, and the scan signal SsB supplied from the shift register 33RB. Each of the drive circuits 33R includes a transistor 35R. The transistor 35R may be configured of, for example, an N-channel MOSTFT similarly to the transistor 34 and the like. In the drive circuit 33R(k), a drain of the transistor 35R is connected to the source of the transistor 34 and the power line PL(k), a gate thereof is connected to the wiring L2B(k), and a source thereof is connected to a wiring L3.
First, the voltage of the scan signal SsB varies from the high level voltage VH to the low level voltage VL at timing t21 ((B) of
Next, the voltage of the scan signal SsA varies from the high level voltage VH to the low level voltage VL at timing t23 ((A) of
In this way, in the power line drive section 26R, the voltage generation section 31R generates the voltages Vccp and Vini, and the drive circuit 33R selects and outputs one of the voltages Vccp and Vini, based on the two scan signals SsA and SsB that are respectively generated by the shift resisters 32RA and 32RB.
In the power line drive section 26R according to the comparative example, the drive circuit 33R is configured using the two transistors 34 and 35R that functions as switches in this way. Therefore, it is necessary for the power line drive section 26R to have the two shift registers 32RA and 32RB that performs ON-OFF control of the two transistors 34 and 35R and the two wirings L1 and L3 that respectively transmit the voltages Vccp and Vini. As a result, the circuit size of the power line drive section 26R is increased, the arrangement area of the circuits and the wirings is increased, and thus flexibility of the circuit layout may be impaired. Moreover, the flexibility of product design as the entire display unit may be impaired. Specifically, in recent years, a panel having narrow bezel is desired in terms of product design. However, since the power line drive section 26R is formed in a so-called bezel region similarly to the case of
On the other hand, in the power line drive section 26 according to the present embodiment, the drive circuit 33 is configured using the transistor 34 that functions as a switch and the transistor 35 that functions as a non-linear element (diode). As a result, in the power line drive section 26, simple configuration configured of one shift resister 34 and one wiring L1 is achievable, and the function equivalent to the power line drive section 26R is achievable. Accordingly, in the power line drive section 26, it is possible to decrease the circuit size, to decrease the arrangement area of the circuits and the wirings, and to enhance flexibility of the circuit layout. In addition, since a panel having narrow bezel region is achievable, which makes it possible to enhance flexibility of product design of the entire display unit.
(Effects)
As described above, in the present embodiment, the drive circuit is configured using the transistor that functions as a switch and the transistor that functions as a non-linear element (diode). Therefore, it is possible to simplify the configuration of the power line drive section. As a result, it is possible to decrease the circuit size, to decrease the arrangement area of the circuits and the wirings, and to enhance flexibility of the circuit layout, as well as to enhance flexibility of product design as the entire display unit.
Moreover, in the present embodiment, the channel width W of the transistor 34 is made lager than the channel width W of the transistor 35. This facilitates driving of the sub-pixels, and makes it possible to suppress the circuit area of the drive circuit.
Moreover, in the present embodiment, the wiring L1 is formed of the upper layer metal that has low sheet resistance. Therefore, it is possible to decrease the resistance value of the wiring L1, and to facilitate driving of the sub-pixels.
Further, in the present embodiment, the wiring L1 is disposed between the drive circuits and the shift register. Therefore, it is possible to facilitate driving of the sub-pixels.
Moreover, in the present embodiment, the display section is configured only using an NMOS transistor without using a PMOS transistor. Therefore, it is possible to manufacture the display section even by the process that is not possible to manufacture a PMOS transistor as with the oxide TFT (TOSTFT) process.
(Modification 1-1)
In the above-described embodiment, the diode-connected transistor 35 is provided in each of the drive circuits 33. However, this is not limitative, and alternatively, for example, as illustrated in
(Modification 1-2)
In the above-described embodiment, each of the transistors 34 and 35 of the drive circuit is configured of an N-channel MOSTFT. However, the transistor is not limited thereto, and for example, as illustrated in
With this configuration, in the drive circuit 33C(k), when the voltage of the scan signal Ss(k) is the low level voltage VL, the transistor 37 is turned on and the transistor 36 is turned off. As a result, the drive circuit 33C(k) outputs the voltage Vini as the power signal DS(k). Moreover, when the voltage of the scan signal Ss(k) is the high level voltage VH, the transistor 37 is turned off and the transistor 36 is transiently turned on. As a result, the drive circuit 33C(k) outputs the voltage Vccp lower than the high level voltage VH (=Vccp+|Vth|) by the absolute value |Vth| of the threshold voltage of the transistor 36, as the power signal DS(k). In this example, for example, the channel width (W) of the transistor 36 may be larger than the channel width (W) of the transistor 37.
(Modification 1-3)
In the above-described embodiment, the power line drive section 26 is configured using the drive circuits 33. However, the configuration is not limited thereto, and alternatively or in addition thereto, for example, the scan line drive section 23 may be configured using the drive circuits 33. In this case, it is possible to simplify the configuration of the scan line drive section 23.
(Modification 1-4)
In the above-described embodiment, the technology is applied to the display unit using the organic EL element. However, the application is not limited thereto, and alternatively, for example, the technology may be applied to a display unit using a liquid crystal display element. Specifically, for example, the technology may be applied to a circuit selecting pixels to which the pixel voltage is written (corresponding to the scan line drive section 23 in the above-described embodiment).
(Modification 1-5)
In the above-described embodiment, as illustrated in
Likewise, in the above-described embodiment, as illustrated in
Next, a display unit 2 according to a second embodiment is described. In the present embodiment, the voltage Vofs is written to the sub-pixels 11 to perform extinction operation before initialization of the sub-pixels 11. Note that like numerals are used to designate substantially like components of the display unit 1 according to the above-described first embodiment, and the description thereof is appropriately omitted.
As illustrated in
The scan line drive section 43 of the drive section 40 applies the pulse PP0 to one scan line WSL in one horizontal period (1H), and applies the two pulses PP1 and PP2 to the scan line WSL in next one horizontal period (1H). Specifically, the scan line drive section 23 according to the first embodiment applies the two pulses PP1 and PP2 to one scan line WSL in one horizontal period (1H), however the scan line drive section 43 according to the present embodiment further applies the pulse PP0 to the scan line WSL in one horizontal period (1H) prior to the one horizontal period (1H). Specifically, the pulse PP0 is applied during a predetermined period (for example, from timing t31 to timing t32) in a period in which the signal Sig indicates the voltage Vofs and the power signal DS relating to the pixel line to be supplied with the pulse PP0 indicates the voltage Vccp.
First, the drive section 40 performs the extinction operation in a period from the timing t31 to the timing t32 (extinction operation period P0) prior to the initialization period P1. Specifically, at the timing t31 in the period in which the data line drive section 27 applies the voltage Vofs to the data signal line DTL, the scan line drive section 43 varies the voltage of the scan signal WS from low level to high level ((A) and (C) of
Here, the extinction operation period P0 corresponds to a specific but non-limiting example of “third sub-period” in the disclosure.
After that, at the timing t32, the scan line drive section 43 varies the voltage of the scan signal WS from high level to low level ((A) of
Next, at the timing t0, the power line drive section 26 varies the power signal DS from the voltage Vccp to the voltage Vini, similarly to the first embodiment ((B) of
In
The shift register 32 of the power line drive section 26 varies the voltage of the scan signal Ss from the high level voltage VH to the low level voltage VL at the timing t0 ((B) of
After that, the drive section 40 performs initialization of the sub-pixels 11 (initialization period P1), performs the Vth correction (Vth correction period P2), and performs writing of the pixel voltage Vsig to the sub-pixels 11 and performs the μ correction (writing and μ correction period P3), similarly to the drive section 20 according to the first embodiment. Then, thereafter, the organic EL elements OLED of the sub-pixels 11 emit light with luminance corresponding to the written pixel voltage Vsig (emission period P4).
In this way, in the display unit 2, the voltage Vofs is written to the sub-pixels 11 to perform the extinction operation before the initialization of the sub-pixels 11. Therefore, it is possible to decrease the power signal DS from the voltage Vccp to the voltage Vini, in the period from the timing t0 to the timing t2 in substantially same manner irrespective of the pixel voltage Vsig written one frame period before. As a result, in the display unit 2, it is possible to reduce possibility of degradation of image quality.
In other words, if the extinction operation is not performed before the initialization of the sub-pixels 11, the sub-pixels 11 perform emission operation immediately before the timing t0. At this time, the gate voltage Vg and the source voltage Vs of the drive transistor DRTr of each of the sub-pixels 11 are voltages corresponding to the pixel voltage Vsig written one frame period before, and a current corresponding to the pixel voltage Vsig flows through the organic EL element OLED. Therefore, variation of the voltage of the power signal DS after the timing t0 may be varied depending on the pixel voltage Vsig written one frame period before. In other words, for example, when the pixel voltage Vsig written one frame period before is sufficiently low, a current hardly flows through the organic EL element OLED immediately before the timing t0. Therefore, the voltage of the power signal DS varies with a certain time constant as illustrated by the waveform W1 in (C) of
On the other hand, in the display unit 2 according to the present embodiment, the voltage Vofs is written to the sub-pixels 11 before the initialization of the sub-pixels 11. Therefore, the power signal DS decreases from the voltage Vccp toward the voltage Vini in substantially same manner irrespective of the pixel voltage Vsig written one frame period before, during the period from the timing t0 to the timing t2. Also, since the extinction operation is performed before the initialization of the sub-pixels 11, the current hardly flows through the organic EL element OLED immediately before the timing t0. Therefore, the power signal DS is allowed to decrease from the voltage Vccp toward the voltage Vini with a short time constant. As a result, it is possible to reduce possibility of degradation of image quality in the display unit 2.
As described above, in the present embodiment, the predetermined voltage is written to the sub-pixels before initialization of the sub-pixels. Therefore, it is possible to reduce possibility of degradation of image quality.
Moreover, in the present embodiment, the extinction operation is performed before the initialization of the sub-pixels. Therefore, it is possible to reduce possibility of degradation of image quality.
Other effects are similar to those in the above-described first embodiment.
(Modification 2-1)
In the above-described embodiment, as illustrated in
(Modification 2-2)
In the above-described embodiment, the voltage Vofs is applied to the gate of the drive transistor DRTr through the write transistor WSTr during the extinction operation period P0 prior to the initialization period P1. However, this is not limitative. For example, as with a sub-pixel 11A illustrated in
Incidentally, in this example, the voltage Vofs is applied to the gate of the drive transistor DRTr through the control transistor CTr. However, this is not limitative, and a voltage different from the voltage Vofs may be applied to the gate of the drive transistor DRTr. Moreover, in this example, the control transistor CTr is used for the extinction operation. However, this is not limitative, and the control transistor CTr may be used for one or more of the extinction operation, the initialization operation in the initialization period P1, and the Vth correction operation in the Vth correction period P2.
(Other Modification)
Any of the modifications of the above-described first embodiment may be applied to the display unit 2 according to the above-described embodiment.
Next, application examples of the display units described in the above-described embodiments are described. Any of the display units according to the above-described embodiments is applicable to display units of electronic apparatuses in various fields that display an externally input picture signal or an internally generated picture signal as an image or a picture, for example, a television apparatus, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, a video camera, and the like.
Any of the above-described display units may be incorporated in electronic apparatuses according to application examples described below, for example, as a module illustrated in
Hereinbefore, although the technology has been described with referring to the embodiments, the modifications, and the application examples to the electronic units, the technology is not limited to the embodiments and the like, and various modifications may be made. Since a panel having a narrow bezel region may be achievable by the technology, it is possible to enhance flexibility of product design of electronic apparatuses.
For example, in each of the above-described embodiments, the capacitor Csub is provided in the sub-pixel 11. However, the configuration is not limited thereto, and alternatively, for example, the capacitor Csub may be omitted as with a sub-pixel 11D illustrated in
Note that the technology may be configured as follows.
(1) A display unit including:
a unit pixel;
a switch configured to perform ON-OFF control between a second terminal and a third terminal, based on a pulse signal applied to a first terminal, the second terminal being supplied with a DC signal, and the third terminal being connected to the unit pixel; and
a non-linear element interposed between the first terminal and the third terminal.
(2) The display unit according to (1), wherein
the non-linear element is a first transistor including a drain, a gate, and a source, the drain and the gate being connected to the third terminal, and the source being connected to the first terminal, and
the switch is a second transistor having a channel width larger than a channel width of the first transistor.
(3) The display unit according to (2), wherein a conductivity type of the first transistor is same as a conductivity type of the second transistor.
(4) The display unit according to (1), wherein the non-linear element is a diode that has an anode connected to the third terminal and a cathode connected to the first terminal.
(5) The display unit according to any one of (1) to (4), further including:
a first wiring connected to the first terminal, and configured to transmit the pulse signal; and
a second wiring connected to the second terminal and intersecting with the first wiring, and configured to transmit the DC signal.
(6) The display unit according to (5), wherein the second wiring has sheet resistance lower than sheet resistance of the first wiring at an intersection of the first wiring and the second wiring.
(7) The display unit according to any one of (1) to (6), wherein the pulse signal transits between a first voltage and a second voltage, the first voltage turning on the switch and turning off the non-linear element, and the second voltage turning off the switch.
(8) The display unit according to (7), wherein
the unit pixel includes a display element and a drive transistor supplying a drive current to the display element, and
the switch supplies the drive current to the drive transistor.
(9) The display unit according to (8), wherein
the unit pixel further includes a first capacitor and a write transistor,
the drive transistor includes a gate, a source connected to the display element, and a drain connected to the third terminal,
the first capacitor is interposed between the gate and the source of the drive transistor, and
the write transistor is turned on to apply a reset voltage to the gate of the drive transistor during a writing preparation period and to apply a pixel voltage to the gate of the drive transistor during a writing period.
10. The display unit according to (9), wherein
the writing preparation period includes a first sub-period and a second sub-period that is disposed after the first sub-period, and
the pulse signal is at the second voltage during the first sub-period and is at the first voltage during the second sub-period and the writing period.
(11) The display unit according to (10), wherein
the non-linear element applies a third voltage corresponding to the second voltage, to the unit pixel during the first sub-period, and
the switch applies a fourth voltage indicated by the DC signal, to the unit pixel during the second sub-period and the writing period.
(12) The display unit according to (11), wherein
the non-linear element sets a source voltage of the drive transistor to the third voltage through the drive transistor during the first sub-period, and
the switch allows a current to flow through the drive transistor to vary the source voltage of the drive transistor during the second sub-period.
(13) The display unit according to any one of (10) to (12), wherein
the writing preparation period includes a third sub-period disposed before the first sub-period,
the pulse signal is at the first voltage during the third sub-period, and
the switch applies a fourth voltage indicated by the DC signal, to the unit pixel during the third sub-period.
(14) The display unit according to (13), wherein the drive transistor decreases an amount of the drive current to be supplied to the display element during the third sub-period.
(15) The display unit according to (8), wherein
the unit pixel further includes a first capacitor and a control transistor,
the drive transistor includes a gate, a source connected to the display element, and a drain connected to the third terminal,
the first capacitor is interposed between the gate and the source of the drive transistor, and
the control transistor is turned on to apply a reset voltage to the gate of the drive transistor during one or more of a plurality of sub-periods that are included in a writing preparation period disposed before a writing period.
(16) The display unit according to any one of (9) to (15), wherein
the unit pixel further includes a second capacitor connected to the source of the drive transistor.
(17) A drive unit including:
a switch configured to perform ON-OFF control between a second terminal and a third terminal, based on a pulse signal applied to a first terminal, the second terminal being supplied with a DC signal, and the third terminal being connected to a unit pixel; and
a non-linear element interposed between the first terminal and the third terminal.
(18) A driving method including:
performing ON-OFF control between a second terminal and a third terminal, based on a pulse signal applied to a first terminal, the second terminal being supplied with a DC signal, and the third terminal being connected to a unit pixel; and
performing non-linear operation between the first terminal and the third terminal.
(19) An electronic apparatus provided with a display unit and a control section configured to perform operation control on the display unit, the display unit including:
a unit pixel;
a switch configured to perform ON-OFF control between a second terminal and a third terminal, based on a pulse signal applied to a first terminal, the second terminal being supplied with a DC signal, and the third terminal being connected to a unit pixel; and
a non-linear element interposed between the first terminal and the third terminal.
This application is based upon and claims the benefit of priority of the Japanese Patent Application No. 2013-473, filed on Jan. 7, 2013, and the Japanese Patent Application No. 2013-239191, filed on Nov. 19, 2013, both filed with the Japan Patent Office, the entire contents of these applications are incorporated herein by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-000473 | Jan 2013 | JP | national |
| 2013-239191 | Nov 2013 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/083962 | 12/18/2013 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2014/106929 | 7/10/2014 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20050001830 | Osame et al. | Jan 2005 | A1 |
| 20050162354 | Osame | Jul 2005 | A1 |
| 20050162355 | Yamazaki | Jul 2005 | A1 |
| 20080252574 | Sakai et al. | Oct 2008 | A1 |
| Number | Date | Country |
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| 2005-031598 | Feb 2005 | JP |
| 2005-202372 | Jul 2005 | JP |
| 2005-242323 | Sep 2005 | JP |
| 2008-268263 | Nov 2008 | JP |
| 2009-223092 | Oct 2009 | JP |
| Entry |
|---|
| Japanese Office Action for JP2013-239191 dated Jul. 25, 2017. |
| Number | Date | Country | |
|---|---|---|---|
| 20150294623 A1 | Oct 2015 | US |
