DISPLAY UNIT, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

CROSS REFERENCES TO RELATED APPLICATIONS

The present application claims priority to Japanese Priority Patent Application JP 2013-073053 filed in the Japan Patent Office on Mar. 29, 2013, the entire content of which is hereby incorporated by reference.

BACKGROUND

The present disclosure relates to a display unit having a structure in which a wiring layer is laminated together with an organic insulating layer on a substrate, a manufacturing method thereof, and an electronic apparatus including the display unit.

An organic EL (Electro Luminescence) display unit as one type of display units is a display device that controls luminance through a current that flows in an organic light-emitting diode. Therefore, there is an issue in that a characteristic irregularity of a low-temperature polysilicon TFT (Thin Film Transistor) generally used for a switching element appears easily as a display irregularity.

To solve such an issue, a method has been reported of solving a characteristic irregularity of TFT by taking a drive circuit into consideration to improve a display performance in the organic EL display unit. On the other hand, the organic EL display unit tends to become complicated in circuit due to an increase in the number of TFTs used or the number of wiring circuits as compared with those of a liquid crystal display unit, or due to an increase in the area of a capacitor.

In recent years, a larger size and higher definition of a display region have been demanded in the organic EL display unit. However, when the display region is increased in size, a delay of signal occurs by a load due to a wiring resistance and a parasitic capacitance. When the display region is made higher in definition, a density of drive wiring or a wiring layer that forms a signal line is increased along with an increase in the number of pixels, which may cause a short-circuit failure to reduce a yield in manufacturing.

To solve such issues, for example, Japanese Unexamined Patent Application Publication No. 2004-342457 discloses a method in which a failure part, causing a line defect or a luminescent spot being a significant defect for the display unit, is disconnected from a wiring by laser light to allow the failure part to be a normal part or a black spot to thereby improve a yield in manufacturing. Further, for example, Japanese Unexamined Patent Application Publication No. 2012-54510 discloses to solve the high density of the wiring layer by forming a wiring layer, which forms various wirings, to be a multilayer, and by, in order to avoid a delay of signal attributable to such multilayer, forming an insulating layer made of an organic resin or the like having a low dielectric constant between wiring layers. Further, Japanese Unexamined Patent Application Publication No. 2012-54510 also discloses a method of disconnecting and restoring a short-circuit part of the multilayered wirings by disconnecting a lower wiring without damaging an organic resin layer using laser light having permeability to an organic resin.

SUMMARY

In the method disclosed in Japanese Unexamined Patent Application Publication No. 2012-54510, however, a preferable insulation property is obtained for a wiring provided at an upper layer of an organic resin (e.g. a wiring provided on an organic resin), although it is difficult to obtain a desired insulation property for a wiring provided at a lower layer of the organic resin.

It is desirable to provide a display unit capable of achieving both a display quality and a yield in manufacturing, a manufacturing method thereof, and an electronic apparatus.

A display unit according to an embodiment of the present application includes: a laminated structure including two first wirings, a first insulating layer, and a concave part, in which the first wirings are adjacent to each other, the first insulating layer is provided on the first wirings and is made of an organic material, and the concave part penetrates, between the first wirings, from the first insulating layer to the first wirings in a laminated direction; and a second insulating layer provided in the concave part and on the laminated structure.

A method of manufacturing a display unit according to an embodiment of the present application includes: forming a laminated structure including, in recited order, two first wirings and a first insulating layer, in which the first wirings is adjacent to each other and the first insulating layer is made of an organic material; forming a concave part that penetrates from the first insulating layer to the first wirings in a laminated direction, by applying laser light from a side on which the first insulating layer is provided to a short-circuit part formed between the first wirings; performing half-ashing on an irradiation surface of the laser light and a peripheral region that includes the irradiation surface; and forming a second insulating layer in the concave part and on the laminated structure after the performing the half-ashing.

An electronic apparatus according to an embodiment of the present application is provided with a display unit. The display unit includes: a laminated structure including two first wirings, a first insulating layer, and a concave part, in which the first wirings are adjacent to each other, the first insulating layer is provided on the first wirings and is made of an organic material, and the concave part penetrates, between the first wirings, from the first insulating layer to the first wirings in a laminated direction; and a second insulating layer provided in the concave part and on the laminated structure.

In the display unit, the manufacturing method thereof, and the electronic apparatus according to the above-described embodiments of the present application, the laser light is applied to a predetermined position of the laminated structure in which the first insulating layer (e.g., organic insulating layer) made of an organic material is formed on the two first wirings that are adjacent to each other. Thereby, the concave part that penetrates from the first insulating layer to the first wirings is formed. Then, the half-ashing is performed on the irradiation region of the laser light and the peripheral region thereof, following which the concave part is embedded by the second insulating layer (e.g., a planarizing layer). As a result, it is possible to perform electrical disconnection of any position (e.g., a short-circuit part) of the two wirings that are covered with the organic insulating layer.

According to the display unit, the manufacturing method thereof, and the electronic apparatus in the above-described embodiments in the present application, the laser light is applied to a predetermined position of the laminated structure having the organic insulating layer on the two wirings that are adjacent to each other. Thereafter, the half-ashing is performed on the peripheral region including the irradiation surface. Thereby, the concave part that penetrates from the organic insulating layer to the wiring between the two wirings and that is electrically disconnected as well is formed. Therefore, it is possible to provide the display unit that achieves both a display quality and a yield in manufacturing, and the electronic apparatus including such a display unit.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed.

Additional features and advantages are described herein, and will be apparent from the following Detailed Description and the figures.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the specification, serve to describe the principles of the technology.

FIG. 1 is a cross-sectional view illustrating a configuration of a display unit according to an embodiment of the present disclosure.

FIG. 2 illustrates an overall configuration of the display unit illustrated in FIG. 1.

FIG. 3 illustrates one example of a pixel drive circuit illustrated in FIG. 2.

FIG. 4 is a schematic view illustrating a plan view (A) and a cross-sectional view (B) of a short-circuit part of a wiring layer.

FIG. 5 is a schematic view illustrating a plan view (A) and a cross-sectional view (B) at the time of disconnecting the short-circuit part illustrated in FIG. 4.

FIG. 6 is a flowchart illustrating a process order of a part of a method of manufacturing the display unit illustrated in FIG. 1.

FIG. 7 is a characteristic diagram illustrating a relationship between an applied voltage and an inter-terminal current.

FIG. 8 is a characteristic diagram illustrating a relationship of an incidence rate of dielectric breakdown in a disconnection part between an Example and a comparative example of the present disclosure.

FIG. 9 is a characteristic diagram illustrating a relationship between a half-ashing time and an average leakage current.

FIG. 10 illustrates one example of a wiring layout of the display unit according to an embodiment of the present disclosure.

FIG. 11 illustrates another example of the wiring layout of the display unit according to an embodiment of the present disclosure.

FIG. 12 is a cross-sectional view of a contact part of the display unit according to an embodiment of the present disclosure.

FIG. 13A is a cross-sectional view for describing a disconnection process of the contact part illustrated in FIG. 12.

FIG. 13B is a cross-sectional view in which the contact part illustrated in FIG. 12 is embedded by a pixel electrode material.

FIG. 14 is a cross-sectional view illustrating a configuration of the display unit according to a modification example of the present disclosure.

FIG. 15 is a flowchart illustrating a process order of a part of a method of manufacturing the display unit according to the modification example of the present disclosure.

FIG. 16A is a schematic view illustrating a process of a first laser application illustrated in FIG. 15.

FIG. 16B is a schematic view illustrating a process of a second laser application illustrated in FIG. 15.

FIG. 17 is a characteristic diagram illustrating a relationship between the half-ashing time and the average leakage current of the embodiment and the modification example of the present disclosure.

FIG. 18A is a perspective view illustrating an appearance as viewed from a front side of an application example 1 of the display unit according to any of the embodiment and the like.

FIG. 18B is a perspective view illustrating an appearance as viewed from a rear side of the application example 1 of the display unit according to any of the embodiment and the like.

FIG. 19 is a perspective view illustrating an appearance of an application example 2.

FIG. 20A is a perspective view illustrating an appearance as viewed from a front side of the application example 3.

FIG. 20B is a perspective view illustrating an appearance as viewed from a rear side of the application example 3.

FIG. 21 is a perspective view illustrating an appearance of an application example 4.

FIG. 22 is a perspective view illustrating an appearance of an application example 5.

FIG. 23A is a front view, a left side view, a right side view, a top view, and a bottom view in a closed state of an application example 6.

FIG. 23B is a front view and a side view in an opened state of the application example 6.

DETAILED DESCRIPTION

Hereinafter, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The description will be given in the following order.

1. Embodiment (Example where a short-circuit part is disconnected by a laser application and half-ashing)

1-1. Overall Configuration of Display Unit

1-2. Manufacturing Method

1-3. Function and Effect

2. Modification Example (Example where a laser application is repeated plural times)

3. Application Examples (Examples of a display unit and an electronic apparatus)

1. First Embodiment
1-1. Overall Configuration

FIG. 1 illustrates a cross-sectional configuration of a display unit (display unit 1) according to an embodiment of the present disclosure. The display unit 1 may be used, for example, as an organic EL television set, etc. and a display region 110A is provided on a substrate 11 as illustrated in FIG. 2. In the display region 110A, a plurality of pixels (a red pixel 2R, a green pixel 2G, and a blue pixel 2B) are arranged in a form of a matrix. Further, in a peripheral region 110B located in the periphery (the outer edge side and the outer peripheral side) of the display region 110A, a signal line drive circuit 120 and a scanning line drive circuit 130 being a driver (a peripheral circuit 12B to be hereinafter described) for displaying an image are provided.

In the display region 110A, a pixel drive circuit 140 is provided. FIG. 3 illustrates one example (one example of a pixel circuit of the red pixel 2R, the green pixel 2G, or the blue pixel 2B) of the pixel drive circuit 140. The pixel drive circuit 140 is an active drive circuit formed at a lower layer of a pixel electrode 31 to be hereinafter described. The pixel drive circuit 140 has a driving transistor Tr1, a writing transistor Tr2, and a capacitor (holding capacitor) Cs provided between the transistors Tr1 and Tr2. The pixel drive circuit 140 further includes a light-emitting element 10 connected in series to the driving transistor Tr1 between a first power supply line (Vcc) and a second power supply line (GND). That is, in each of the red pixel 2R, the green pixel 2G, and the blue pixel 2B, the corresponding light-emitting element 10 (any one of a red light-emitting element 10R, a green light-emitting element 10G, and a blue light-emitting element 10B, or a white light-emitting element 10W) is provided. The driving transistor Tr1 and the writing transistor Tr2 are each configured by a thin-film transistor (TFT) in general, and a configuration thereof may be an inverted-staggered structure (of a so-called bottom gate type) or a staggered structure (of a so-called top gate type), and is not particularly limited.

In the pixel drive circuit 140, a plurality of signal lines 120A are arranged in a column direction and a plurality of scanning lines 130A are arranged in a row direction. Further, an intersection of each of the signal lines 120A and each of the scanning lines 130A corresponds to any one of the red pixel 2R, the green pixel 2G, and the blue pixel 2B. Each of the signal lines 120A is connected to the signal line drive circuit 120, and an image signal is supplied to a source electrode of the writing transistor Tr2 from the signal line drive circuit 120 through the signal line 120A. Each of the scanning lines 130A is connected to the scanning line drive circuit 130, and a scanning signal is sequentially supplied to a gate electrode of the writing transistor Tr2 from the scanning line drive circuit 130 through the scanning line 130A.

As illustrated in FIG. 1, in the display region 110A of the display unit 1 according to the present embodiment, a semiconductor layer 20 and a display layer 30 are laminated in this order on the substrate 11. The semiconductor layer 20 has, as a wiring layer, a multilayer wiring structure in which, in addition to a wiring layer 21 including a gate electrode 21A, a wiring layer 25 including a channel layer 23 and a pair of source and drain electrodes (a source electrode 25A, a drain electrode 25B, and wiring 25C), and so forth, a wiring layer 27 is laminated on the wiring layer 25 with an inter-layer insulating layer 26 made of an organic material interposed in between.

In the present embodiment, in the multilayer wiring structure, a concave part, namely, a disconnected part A may be formed, for example, at the wiring 25C (first wiring) of the wiring layer 25 covered with the inter-layer insulating layer 26 (first insulating layer), by disconnecting the wiring 25C together with the inter-layer insulating layer 26 continuously. As described later, the disconnected part A is formed through a laser application and half-ashing.

Part (A) and Part (B) of FIG. 4 illustrate a plane configuration (A) before the formation of the disconnected part A and a cross-sectional configuration (B) taken along a I-I line in Part (A) of FIG. 4, respectively. The wiring 25C may be configured, for example, by two linear wirings 25C₁and 25C₂that are adjacent to each other, and a short-circuit part 25X is generated between the wirings 25C₁and 25C₂. FIG. 1 illustrates a structure in which the disconnected part A is formed at a position where the wirings 25C₁and 25C₂are joined by the short-circuit part 25X.

Part (A) and Part (B) of FIG. 5 each illustrate a subsequent state in which the disconnected part A is formed from a state illustrated in Part (A) and Part (B) of FIG. 4 by the laser application and the half-ashing. Part (A) of FIG. 5 illustrates a plane configuration, and Part (B) of FIG. 5 illustrates a cross-sectional configuration taken along a II-II line in Part (A) of FIG. 5. The disconnected part A is obtained by continuously disconnecting the inter-layer insulating layer 26 and the wiring layer 25C that serve as upper layers as described above. Further, as illustrated in FIG. 1 and Part (B) of FIG. 5, the disconnected part A is formed as the concave part that reaches the substrate 11 through lower layers, specifically, an inter-layer insulating layer 24 and a gate insulating layer 22. As can be understood by comparing Part (B) of FIG. 4 with Part (B) of FIG. 5, as a result of forming the concave part through processes of the laser application and the half-ashing, a part of a surface of the inter-layer insulating layer 26 is removed and thus a step 26A is formed beneath the wiring layer 27 serving as an upper layer thereof.

Hereinafter, the semiconductor layer 20 and the display unit 30 are described.

(Configuration of Semiconductor Layer)

The semiconductor layer 20 provided on the substrate 11 is formed with the above-described driving transistor Tr1 and writing transistor Tr2, and various wirings. Further, a planarizing insulating layer 28 is provided on the transistors Tr1 and Tr2 and the wirings. The transistors Tr1 and Tr2 (hereinafter, referred to as a thin-film transistor 20A) may be of any of a top gate type and a bottom gate type. Here, the bottom gate type thin-film transistor 20A is described as an example. The thin-film transistor 20A is provided with the gate electrode 21A, the gate insulating layer 22, an organic semiconductor film forming a channel region (the channel layer 23), the inter-layer insulating layer 24, and the pair of source and drain electrodes (the source electrode 25A and the drain electrode 25B) in this order from the substrate 11 side. Further, the thin-film transistor 20A includes the inter-layer insulating layer 26 and the wiring layer 27 as a multilayer wiring layer.

Examples of the substrate 11 may include, besides a glass substrate, a plastic substrate made of a plastic such as polyether sulfone, polycarbonate, polyimides, polyamides, polyacetals, polyethylene terephthalate, polyethylene naphthalate, polyethyl ether ketone, and polyolefins, and a metal foil substrate made of a metal such as aluminum (Al), nickel (Ni), copper (Cu), and stainless and to which an insulation treatment is applied to a surface thereof. Alternatively, the substrate 11 may be made of paper. Further, a functional film such as a buffer layer for improving adhesion or flatness, and a barrier film for improving a gas barrier property may be formed on such a substrate. Further, an inexpensive plastic film may be used for the substrate 11, so long as a film of the channel layer 23 is formed without heating the substrate 11, such as using a sputtering method.

The gate electrode 21A serves to apply a gate voltage to the thin-film transistor 10 and control a carrier density in the channel layer 23 through the gate voltage. The gate electrode 21A is provided at a selective region of the substrate 11, and may be made of a metal simple substance such as platinum (Pt), titanium (Ti), ruthenium (Ru), molybdenum (Mo), copper (Cu), tungsten (W), nickel (Ni), aluminum (Al), and tantalum (Ta), or an alloy thereof. Alternatively, two or more thereof may be laminated.

The gate insulating layer 22 may be provided between the gate electrode 21A and the channel layer 23 at a thickness in a range from 50 nm to 1 μm, for example. The gate insulating layer 22 may be formed, for example, by an insulating film including one or more of a silicon oxide film (SiO), silicon nitride film (SiN), silicon oxynitride film (SiON), hafnium oxide film (HfO), aluminum oxide film (AlO), aluminum nitride film (AlN), tantalum oxide film (TaO), zirconium oxide film (ZrO), hafnium oxynitride film, hafnium silicon oxynitride film, aluminum oxynitride film, tantalum oxynitride film, and zirconium oxynitride film. The gate insulating layer 22 may have a single layer structure, or a laminated structure that uses two or more materials such as SiN and SiO. When the gate insulating layer 22 has a laminated structure, an interface property between the gate insulating layer 22 and the channel layer 23 is improved and entry of impurities (e.g., moisture) to the channel layer 23 from outside air is suppressed effectively. The gate insulating layer 22 is patterned to a predetermined shape through etching after the formation by coating. Alternatively, depending on a material used therefor, a pattern thereof may be formed using a printing technique such as ink jet printing, screen printing, offset printing, and gravure printing.

The channel layer 23 is provided on the gate insulating layer 22 in an island shape, and has a channel region 24C at a position that faces the gate electrode 21A between the source electrode 25A and the drain electrode 25B. A thickness of the channel layer 23 may be, for example, in a range from 5 nm to 100 nm. The channel layer 23 may be made of an organic semiconductor material such as peri-Xanthenoxanthene (PXX) derivatives. Examples of the organic semiconductor material may include: polythiophene, poly-3-hexylthiophene [P3HT] in which a hexyl group is introduced into polythiophene, pentacene[2,3,6,7-dibenzoanthracene], polyanthracene, naphthacene, hexacene, heptacene, dibenzopentacene, tetrabenzopentacene, chrysene, perylene, coronene, terylene, ovalene, quaterrylene, circumanthracene, benzopyrene, dibenzopyrene, triphenylene, polypyrrole, polyaniline, polyacetylene, polydiacetylene, polyphenylene, polyfuran, polyindole, polyvinylcarbazole, polyselenophene, polytellurophene, polyisothianaphthene, polycarbazole, polyphenylene sulfide, polyphenylene vinylene, polyphenylene sulphide, polyvinylene sulphide, polythienylene vinylene, polynaphthalene, polypyrene, polyazulene, phthalocyanine represented by copper phthalocyanine, merocyanine, hemicyanine, polyethylenedioxythiophene, pyridazine, naphthalenetetracarboxylic acid diimide, poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonate) [PEDOT/PSS], 4,4′-biphenyl dithiol (BPDT), 4,4′-diisocyanobiphenyl, 4,4′-diisocyano-p-terphenyl, 2,5-bis(5′-thioacetyl-2′-thiophenyl)thiophene, 2,5-bis(5′-thioacetoxyl-2′-thiophenyl)thiophene, 4,4′-diisocyanophenyl, benzidine(biphenyl-4,4′-diamine), TCNQ (tetracyanoquinodimethane), a charge-transfer complex represented by a tetrathiafulvalene (TTF)-TCNQ complex, by a bisethylenetetrathiafulvalene (BEDTTTF)-perchloric acid complex, by a BEDTTTF-iodine complex, and by a TCNQ-iodine complex, a biphenyl-4,4′-dicarboxylic acid, 24-di(4-thiophenylacetylinyl)-2-ethylbenzene, 24-di(4-isocyanophenylacetylinyl)-2-ethylbenzene, dendrimer, fullerene such as C60, C70, C76, C78, and C84, 24-di(4-thiophenylethynyl)-2-ethylbenzene, 2,2″-dihydroxy-1,1′:4′,1″-terphenyl, 4,4′-biphenyl diethanal, 4,4′-biphenyldiol, 4,4′-biphenyldiisocyanate, 24-diasetynylbenezene, diethylbiphenyl-4,4′-dicarboxylate, benzo[22-c; 3,4-c′; 5,6-c″]tris[22]dithiol-24,7-trithione, alpha-sexithiophene, tetrathiotetracene, tetraselenotetracene, tetratellurium tetracene, poly(3-alkylthiophene), poly(3-thiophene-β-ethanesulfonic acid), poly(N-alkyl pyrrole), poly(3-alkyl pyrrole), poly(3,4-dialkylpyrrole), poly(2,2′-thienylpyrrole), poly(dibenzothiophene sulfide), and quinacridone. In addition, a compound selected from the group of a condensed polycyclic aromatic compound, a porphyrin-based derivative, a phenylvinylidene-based conjugated oligomer, and a thiophene-based conjugated oligomer may be used. Further, organic semiconductor materials and insulating high-polymer materials may be mixed.

The channel layer 23 may be formed using a vacuum evaporation method. Alternatively, for example, the above-described material may be preferably dissolved into an organic solvent to obtain an ink solution, to form the channel layer 23 using a coating/printing process. One reason is that the cost associated with the coating/printing process is reduced as compared to that of the vacuum evaporation method, and is effective in improving a throughput. Specific examples of the coating/printing process may include methods such as cast coating, spin coating, spray coating, ink jet printing, letterpress printing, flexographic printing, screen printing, gravure printing, and gravure offset printing.

The inter-layer insulating layers 24 and 26 prevent short-circuit between wirings that are provided in different layers, such as between the channel layer 23 and the source and drain electrodes 25A and 25B, or between the wiring 27A and the source and drain electrodes 25A and 25B. A material of each of the inter-layer insulating layers 24 and 26 may be a material having an insulation property, which may be the inorganic insulating material described above with reference to the gate insulating layer 22. Note that when a wiring layer has a multilayer structure as in the present embodiment, an insulating material having a low dielectric constant may be preferably used in order to avoid a delay of signal. Specifically, a photosensitive resin material which may be, for example, polyimide-based, polyacrylate-based, epoxy-based, or cresol novolak-based resin material, or an organic material which may be polystyrene-based, polyamide-based, or fluorine-based organic material may be preferably used.

The source and drain electrodes 25A and 25B are provided away from each other on the channel layer 23, and are electrically connected to the channel layer 23. A material configuring the source and drain electrodes 25A and 25B may include a metal material, a semimetal, or an inorganic semiconductor material. Specifically, besides the conductive film materials described above with reference to the gate electrode 21A, examples of the material may include aluminum (Al), gold (Au), silver (Ag), indium tin oxide (ITO), molybdenum oxide (MoO), and an alloy thereof. The source and drain electrodes 25A and 25B may be each configured by the above-described metal simple substance or an alloy thereof, and may be a single layer or may have a laminated structure that includes two or more thereof. The laminated structure may include, for example, a Ti/Al/Ti configuration, a Mo/Al configuration, or any other suitable configuration. Also, the wiring 27A may have the same configuration as those of the source and drain electrodes 25A and 25B.

The planarizing insulating layer 28 serves to planarize a surface of the substrate 11 on which the thin-film transistor 20A is formed. Examples of constituent material of the planarizing insulating layer 13 may include the above-described organic material such as polyimide, and an inorganic material such as a silicon oxide (SiO₂).

As described above, a configuration of the semiconductor layer 20 is described with reference to the components of the thin-film transistor 20A. Note that wirings that are formed in the same layers as those of various wirings 21A, 25A, 25B, and 27A configuring the thin-film transistor 20A may be formed using the same materials through the same processes, irrespective of positions thereof.

(Configuration of Display Layer)

The display layer 30 includes the light-emitting element 10, and is provided on the semiconductor layer 20, specifically, on the planarizing insulating layer 28. The light-emitting element 10 has a configuration in which the pixel electrode 31 as an anode, an inter-electrode insulating film 32 (partition wall), an organic layer 33 including a light-emitting layer, and a counter electrode 34 as a cathode are laminated in this order from the semiconductor layer 20 side. A sealing substrate 36 is bonded to the counter electrode 34 through a sealing layer 35. The thin-film transistor 20A and the light-emitting element 10 are electrically connected to the pixel electrode 31 through a connection hole 28A provided on the planarizing insulating layer 28.

The pixel electrode 31 has a function as a reflective layer as well, and may desirably have a reflectivity as high as possible in order to increase luminous efficiency. In particular, when the pixel electrode 31 is used as an anode, the pixel electrode 31 may be desirably made of a material having a high hole injection property. Examples of the material of such a pixel electrode 31 may include a simple substance of a metal element such as aluminum (Al), chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tungsten (W), or silver (Ag), and an alloy thereof. A transparent electrode having a large work function may be preferably laminated on a surface of the pixel electrode 31. In the present embodiment, a case is described as an example where the pixel electrode 31 has a laminated structure of a layer (reflective electrode film 31A) made of a material having a reflecting function such as Al, and a layer (transparent electrode film 31B) made of a transparent conductive material such as an indium tin oxide (ITO).

The inter-electrode insulating film 32 secures an insulation property between the pixel electrode 31 and the counter electrode 34, and serves to allow a light-emitting region to have a desired shape. For example, the inter-electrode insulating film 32 may be made of a photosensitive resin. The inter-electrode insulating film 32 is provided only around the pixel electrode 31, and a region exposed from the inter-electrode insulating film 32 of the pixel electrode 31 serves as a light-emitting region. Note that although the organic layer 33 and the counter electrode 34 are provided also on the inter-electrode insulating film 32, a region where the emission of light occurs is only the light-emitting region.

The organic layer 33 may have, for example, a configuration in which a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are laminated in order from the pixel electrode 31 side. These layers may be provided on an as-necessary basis. The layers configuring the organic layer 33 may have respective configurations different from one another, depending on luminescent colors of the light-emitting elements 10R, 10G, and 10B. The hole injection layer serves to increase a hole injection efficiency and serves also as a buffer layer for preventing a leakage. The hole transport layer serves to increase a hole transport efficiency to the light-emitting layer. The light-emitting layer is applied with an electrical field to cause recombination of holes and electrons, by which light is generated therein. The electron transport layer serves to increase an electron transport efficiency to the light-emitting layer. The electron injection layer serves to increase an electron injection efficiency.

The counter electrode 34 may be made of, for example, an alloy of aluminum (Al), magnesium (Mg), calcium (Ca), or sodium (Na). In particular, an alloy of magnesium and silver (Mg—Ag alloy) is preferable in that electrical conductivity in a thin film and small absorption are both achieved. A ratio of magnesium and silver in the Mg—Ag alloy may be preferably in a range of Mg:Ag=20:1 to 1:1 in film thickness ratio, although the ratio is not particularly limited. Further, a material of the counter electrode 34 may be an alloy of aluminum (Al) and lithium (Li) (an Al—Li alloy).

The sealing layer 35 may have a laminated structure of a layer including silicon nitride (SiN_X), a silicon oxide (SiO_X), or a metal oxide, and a layer including a thermosetting resin or an ultraviolet setting resin. For example, the sealing substrate 36 provided with a light-shielding film and a color filter may be bonded on the sealing layer 35.

1-2. Manufacturing Method

The semiconductor layer 20 and the display layer 30 may be formed using methods in general to be hereinafter described. First, for example, by using the sputtering method or the vacuum evaporation method, a metal film which eventually serves as the gate electrode 21A is formed over an entire surface of the substrate 11. Subsequently, the metal film may be patterned, for example, by using the photolithography method and the etching method to form the wiring layer 21. Then, a film of the gate insulating layer 22 and that of the channel layer 23 are formed in order over the entire surfaces of the substrate 11 and the gate electrode 21A. Specifically, for example, by using the spin coating method, the above-described gate insulating film material such as a PVP (Polyvinylpyrrolidone) solution may be coated over the entire surface of the substrate 11 and then dried. Thereby, the gate insulating layer 22 is formed. Subsequently, an organic semiconductor material such as a PXX compound solution may be coated on the gate insulating layer 22. Thereafter, the coated organic semiconductor material is heated to form the channel layer 23 on the gate insulating layer 22.

Then, the inter-layer insulating layer 24 is formed on the channel layer 23, following which metal films are formed on the channel layer 23 and the inter-layer insulating layer 24. For example, a laminated film of Mo/Al/Mo may be formed using the sputtering method. Next, for example, through the etching method using the photolithography method, the wiring layer 25 including the source and drain electrodes 25A and 25B and the wiring 25C is formed.

Then, the inter-layer insulating layer 26 is formed on the inter-layer insulating layer 24 and the wiring layer 25, following which the wiring layer 27 including the wiring 27A is formed on the wiring layer 25 and the inter-layer insulating layer 26 using a method similar to that described above. Then, a photosensitive resin such as polyimide is coated on the inter-layer insulating layer 26 and the wiring layer 27, following which exposure and development are performed to carry out patterning of the planarizing insulating layer 28 into a predetermined shape, followed by the formation of the connection hole 28A and firing. Then, for example, by using the sputtering method, a metal film having, for example, an Al/ITO configuration is formed on the planarizing insulating layer 28, following which, for example, by using the wet etching method, the metal film at a predetermined position is selectively removed to form the pixel electrodes 31 that are separated for the respective light-emitting elements 10R, 10G, and 10B.

Then, a film of the organic layer 33 including the light-emitting layer and that of the counter electrode 34 are formed, for example, by using an evaporation method. Thereafter, the sealing substrate 36 is bonded to the organic layer 33 and the counter electrode 34 with the sealing layer 35 interposed in between. Finally, FPC for providing connection with an external circuit is implemented to thereby complete the display unit 1.

As illustrated in FIG. 1, in a highly-densified wiring layer in which a plurality of wirings are provided in one layer, a failure in a film formation process of the wiring layer may cause a short-circuit part X (short-circuit part 25X) between the wirings (e.g., between the wirings 25C₁and 25C₂) as illustrated in FIG. 4. This may cause circuit abnormality since the wirings 25C₁and 25C₂are in a short-circuit state electrically. Therefore, it is necessary to detect the short-circuit part 25X through a detection such as an optical inspection, and to disconnect and remove the detected short-circuit part 25X to thereby restore a circuit to be in a normal state.

As described above, the short-circuit part X is disconnected and removed using laser light. Note that, in order to detect the short-circuit part X, it is preferable that the circuit including the thin-film transistor 20A be completed. Therefore, it is desirable that the presence or absence of the short-circuit part X be inspected in a state (in the present embodiment, up to a state where the wiring layer 27 is arranged) where all of the wiring layers to be formed in the semiconductor layer are arranged, and that further short-circuit part X be laser-processed in a state where the wiring layer is covered with the insulating layer. For this purpose, as described in the above-described Japanese Unexamined Patent Application Publication No. 2012-54510, a method may be considered in which wiring layers are covered with an organic insulating layer (organic resin) and only a lower wiring layer is disconnected without damaging the organic resin using laser light having permeability to the organic resin. However, in such a method, it is difficult to obtain a desired insulation property, because a part to be disconnected is covered with the organic insulating layer and thereby a metal melted by the laser application is not removed.

On the other hand, when laser light of a wavelength having large absorption by the organic resin is used to disconnect the lower wiring layer together with the organic insulating layer, the short-circuit part X is disconnected using the laser light of a fixed output or more as illustrated in FIG. 7. However, it has been confirmed that a small leakage current occurs in such a disconnected part, by which a display defect such as a thin line defect occurs, and in a worse case, a dielectric breakdown occurs during the driving due to an insufficient withstand voltage. This may be attributable to attachment of soot, generated during the laser application by the organic resin configuring the organic insulating layer, to a bottom surface and side surfaces of the disconnected part A.

Referring to a flowchart of FIG. 6, to address such issues, in the present embodiment, a laminated structure of the wiring layer and the organic insulating layer is formed (Step S101), and thereafter, the optical inspection or the like is performed to inspect the presence or absence of the short-circuit part X. When the short-circuit part X is detected at the wiring layer, the short-circuit part X is first disconnected together with the organic insulating layer through the laser application (Step S102-1). Thereafter, a bottom surface and side surfaces of the disconnected part A may be exposed to, for example, oxygen plasma to perform half-ashing (Step S102-2). For example, the half-ashing may be performed under the conditions of RF source: 1000 W, RF bias: 0 W, pressure: 1 Pa, gas: oxygen 400 sccm, and processing time: 300 seconds. The half-ashing process removes a leakage source such as soot attached to the bottom surface or the side surfaces of the disconnected part A, making it possible to obtain the disconnected part A having a high insulation property (Step S102). Finally, as described above, the wiring layer 27 is formed on the inter-layer insulating layer 26, following which the disconnected part A is embedded by the planarizing insulating layer 28 arranged thereafter (Step S103). Note that the optical inspection may be performed after the wiring layer is formed.

FIG. 8 illustrates a result of performing the half-ashing after the laser application (shown as “Example”). It was confirmed that as compared to a case where the disconnected part was formed only by the laser application (shown as “comparative example”), the half-ashing performed after the laser application reduced the leakage current, and an incidence rate of the dielectric breakdown was reduced.

As for the laser light L used in the formation process of the disconnected part A, the laser light L of a wavelength having large absorption by the organic material configuring the inter-layer insulating layer, which may be in a range from 10 nm to 400 nm, may be preferably used. Further, as for the laser light L, pulsed laser light having a pulse width of less than 100 ns may be preferably used. One reason is that, because a level of a thermal effect in the laser processing is proportional to a square root of a pulse width, the excessively long pulse width may cause an adverse effect thermally, such as excessive fusion, on the vicinity of the irradiation region S₁of the laser light, thereby making it difficult to restore the short-circuit part X. The laser light L may be applied (the number of shots: one pulse) by a single shot, or repeatedly applied (the number of shots: plural pulses) while setting a repetition frequency to less than 1 MHz. Setting the repetition frequency to less than 1 MHz makes it possible to avoid a heat accumulation effect between pulses.

Widths D1 and D2 of the irradiation region S1 of the laser light may be adjusted, for example, so that the laser light L is applied to a part or all of the short-circuit part 25X. On the occasion, the width D1 (length D1 in an extending direction of the short-circuit part 25X) of the irradiation region S1 of the laser light may be preferably made shorter than the width D25 of the short-circuit part 25X. Note that, when the width D1 is excessively narrowed, the laser light may not be properly collected due to a diffraction limit; hence, a lower limit of the width D1 may be preferably set to around the wavelength of the laser light L used. The same is applicable to the width D2 (length D2 in a width direction of the short-circuit part 25X) of the irradiation region S1 of the laser light. Also, the width D2 of the irradiation region S1 of the laser light may be preferably the same as the width D25 of the short-circuit part 25X, or larger than the width D25 of the short-circuit part 25X. One reason is that, when the width D2 of the irradiation region S1 of the laser light is narrower than the width D25 of the short-circuit part 25X, an unprocessed part may occur to make it difficult to restore the short-circuit part 25X.

In the present embodiment, the disconnected part A is formed linearly; however, a shape of the disconnected part A is not limited thereto. For example, the short-circuit part 25X may be cut in a zigzag pattern. Further, the wiring layer (e.g., the wiring layer 25) to be disconnected by the laser application and the wiring layer (e.g., the wiring layer 21) serving as a lower layer thereof may be formed of the same material as one another, or may be formed of materials different from one another.

In the half-ashing, for example, oxygen plasma may be preferably used. One reason is that soot (e.g., amorphous carbon) attached to the disconnected part A is oxidized and efficiently removed, for example, as carbon dioxide (CO₂). Further, besides the oxygen plasma, fluorine plasma or chlorine-based plasma may be used.

FIG. 9 illustrates respective average leakage currents of a case where the short-circuit part 25X is disconnected only through the laser application (comparative example) and a case where the half-ashing is performed after the laser application (Example) in the disconnecting and restoring the short-circuit part 25X of the wirings 25C₁and 25C₂. It can also be seen from FIG. 9 that an insulation property of the disconnected part A is improved by the half-ashing. Further, preferably, a half-ashing time may be so set that, for example, a surface of the inter-layer insulating layer 26 provided with the wiring layer 25 is removed within a fixed range. FIG. 9 also illustrates an amount of removal of resin (e.g., the inter-layer insulating layer 26) for each half-ashing time. In the Example, the half-ashing time was set to 60, 120, 180, 240, and 300 seconds, and the respective average leakage currents were measured. The amount of removal of a resin surface around the disconnected part A was increased in proportion to a length of each half-ashing time. Specifically, the amounts of removal were 56 nm, 107 nm, 156 nm, 204 nm, and 253 nm. It can be seen therefrom that as the amount of removal of resin more increases, namely, the depth H of the step 26A in FIG. 5 is more deepened, the average leakage current in the disconnected part A is more reduced. From this result, it can be understood that the half-ashing time may be preferably longer than or equal to the time by which the soot attached to the disconnected part A is sufficiently removed. An upper limit of the half-ashing time may be determined in consideration of a film thickness by which the insulating layer (here, the inter-layer insulating layer 26) covering the wiring layer is capable of maintaining an insulation performance or a surface property.

In the present embodiment, the short-circuit part 25X generated at the wiring 25C provided in the same layer as the source and drain electrodes 25A and 25B provided on the inter-layer insulating layer 24 is disconnected and restored. However, a location at which the short-circuit part 25X generates is not particularly limited. For example, when the short-circuit part 25X is generated in the source electrode 25A or the drain electrode 25B, it is also possible to disconnect and restore the short-circuit part 25X similarly. Also, it is possible to disconnect and restore the short-circuit parts 21X and 27X similarly when the short-circuit parts 21X and 27X are generated in a layer of the gate electrode 21A or that of the wiring layer 27. Further, other than the wiring layers 21, 25, and 27, the disconnection and the restoration may be applied also to the channel layer 23.

Using the above-described method of disconnecting and restoring the short-circuit part makes it possible to improve a yield in manufacturing of the display unit. In addition thereto, taking a wiring layout of the display unit into consideration makes it possible to further improve the yield in manufacturing.

Specifically, the disconnection and the restoration between the wirings that are arranged in the same layer one another, as in the disconnection and the restoration of the short-circuit part 25X as described above, achieve a high insulation property by a plasma treatment and by taking a disconnection layout into consideration. However, an inter-layer leakage may occur when disconnecting a portion in which wirings are laminated with the inter-layer insulating layer interposed in between. Therefore, the wirings (wirings provided in the same layer, such as the source electrode 25A, the drain electrode 25B, and the wiring 25C) arranged in the same layer as one another may be preferably laid out to be side-by-side with respect to one another. The wirings (wirings provided in different layers, such as the wiring layers 21 and 25, and the wiring layers 25 and 27) arranged in different layers from one another may be preferably laid out to be orthogonal with respect to one another (e.g., FIGS. 10 and 11).

FIG. 10 illustrates one example of a wiring layout in which the transistors Tr1 and Tr2, the signal line 120A, the scanning line 130A, and the power supply line (Vcc and GND) of the display unit 1 are configured by three layers of the wiring layers 21 and 25 and the channel layer 23. FIG. 11 illustrates one example of a wiring layout in which the transistors Tr1 and Tr2, the signal line 120A, the scanning line 130A, and the power supply line (Vcc and GND) of the display unit 1 are configured by four layers of the wiring layers 21, 25, and 27 and the channel layer 23.

As described above, a line defect and a luminescent spot are significant failures that largely impair an appearance of a display unit. For example, the line defect failure occurs when the signal line 120A and the power supply line (GND) are short-circuited. To cure such a failure, a method may be employed in which the short-circuit part X between the signal line 120A and GND (disconnected part A) is disconnected. Alternatively, a method may be employed in which a light-emitting element is caused to be a black spot by disconnecting GNDs around the short-circuit part X (disconnected part B) to make the disconnected part B to be a part of the signal line 120A along with the short-circuit part X, to allow the corresponding light-emitting element 10W to be in an electrically floating state. The disconnected part A and the disconnected part B correspond respectively to an O-O line (disconnected part A), and a P-P line and a Q-Q line (disconnected part B) of FIGS. 3 and 11.

When causing the light-emitting element 10W to be a black spot, it is necessary to separate a contact hole to which a common potential line such as GND is connected and a contact hole serving as an anode or a cathode for connecting the pixel drive circuit 140 and the light-emitting element 10W, from their respective connection destinations (such as the contact holes that are denoted by ▪ (black square) in FIGS. 10 and 11). As a method of separating the contact holes, as illustrated in FIGS. 13A and 13B, laser light may be applied to a contact region to form an opening P (FIG. 13A), following which the opening P may be embedded by an insulating material such as an organic resin (FIG. 13B). As illustrated in FIG. 13A, when any of the wiring layers 21, 25, and 27 and the channel layer 23 is present under the contact hole at the time of forming the opening P by the laser light, an inter-layer short-circuit may occur. Therefore, as for the driving side contact holes, a wiring that has caused an inter-layer short circuit is separated from the scanning line 120A. Also, as for an under region of a separation part of the scanning line 120A and an under region of the contact hole in a common potential line, such a layout may be employed in which the wiring layers 21, 25, and 27 or the channel layer 23, or both, is/are not present at the disconnected part in order to avoid the inter-layer short-circuit. Thereby, the light-emitting element 10W is allowed to be in an electrically floating state, and thus to be a black spot.

As described above, the wirings may be laid out so that the wirings located in the same layer become side-by-side with respect to one another, and that the wirings located in the different layers from one another become orthogonal with respect to one another, thereby making it possible to increase a region in which the disconnection and the restoration of the short-circuit part X generated at the wiring of each layer are possible. Further, the wirings may be laid out so that one or both of the wiring layers (wiring layers 21 and 25) and the channel layer 23 is/are not arranged under the common potential line, thereby making it possible to disconnect an R-R line, an S-S line, and so forth, in addition to the O-O line, the P-P line, and the Q-Q line. That is, it is possible to increase a region in which the disconnection and the restoration of the short-circuit part X generated in the wiring of each layer are possible, in substantially an entire region of the display region 110A (and the peripheral region 110B), and to further improve the yield in manufacturing.

1-3. Function and Effect

As described above, in the display unit 1 and the manufacturing method thereof according to the present embodiment, the laser light L is applied to a predetermined position of the wiring layer in which the wiring 25C and an organic insulating layer such as the inter-layer insulating layer 26 are laminated. Then, the half-ashing is performed on a peripheral region including the irradiation region S1 of the laser light L. That is, the application of the laser light L and the half-ashing may be performed, for example, on the short-circuit part 25X generated between the two wirings 25C₁and 25C₂that are adjacent to each other, to electrically disconnect the short-circuit part 25X and to form the disconnected part A that penetrates from the inter-layer insulating layer 26 to the wirings 25C₁and 25C₂. Thereby, it is possible to electrically disconnect any position of the wiring layer that is covered with the organic insulating layer.

According to the present embodiment, the laser light L is applied to a predetermined position of the wiring layer, following which the half-ashing is performed on the peripheral region including the irradiation region S1 of the laser light L. Thus, it is possible to electrically disconnect the wiring layer in which the organic insulating layer is laminated. Therefore, it is possible to provide the display unit 1 that achieves both the display quality and the yield in manufacturing.

Hereinafter, a modification example of the embodiment is described. The same components as those of the embodiment described above are denoted with the same reference numerals, and the description thereof is omitted where appropriate.

2. Modification Example

FIG. 14 illustrates a cross-sectional configuration of a display unit (display unit 1A) according to a modification example of the embodiment described above. FIG. 15 illustrates a flowchart of a disconnection process of a wiring layer according to the present modification example. The present modification example differs from the embodiment described above, in that a laser application process in performing the disconnection and the restoration on a predetermined position of the wiring layer in the display unit 1A, such as the short-circuit part 25X of the wirings 25C (wirings 25C₁and 25C₂), is performed two times (first laser application and second laser application).

In the present modification example, the laser light L1 and laser light L2 are applied continuously to the short-circuit part 25X and then the half-ashing is performed, in a manner similar to that described above. Specifically, as illustrated in FIG. 16A, the laser light L1 is applied to the short-circuit part 25X (Step S202-1) to form a disconnected part B1, following which the laser light L2 having a narrower irradiation width than that of the laser light L1 may be applied to a bottom surface of the disconnected part B1 and to a laser application start point Is and a laser application end point Ie (Step S202-2). Thereafter, the bottom surface and side surfaces of the disconnected part B1 may be exposed to, for example, oxygen plasma to perform the half-ashing (Step S202-3). As a result, the disconnected part B having a high insulation property is formed.

FIG. 17 is a characteristic diagram illustrating a relationship between the half-ashing time and the average leakage current in the disconnected part A (Example 1) of the embodiment and the disconnected part B (Example 2) of the present modification example in which the laser application process was performed two times. As can be seen from FIG. 17, in the disconnected part B of the present modification example, the average leakage current was reduced, i.e., withstand voltage characteristics were secured, even though the half-ashing time was shortened to half. This may be due to a fact that powder of a metal, configuring the short-circuit part 25X and left on a bottom of the disconnected part B1 or scattered to the laser application start point Is and the laser application end point Ie by the first laser application, is removed by the second laser application. Note that a width D3 in an irradiation region S2 of the laser light L2 may be preferably shorter than the width D1 of the irradiation region S1.

As described above, the laser application process is performed two times (the first laser application and the second laser application) on a predetermined position (e.g., the short-circuit part 25X of the wirings 25C) of the wiring layer in the display unit 1A. Thereby, it is possible to shorten the half-ashing time. Further, it is possible to suppress the amount of removal of the insulating layer (e.g., the inter-layer insulating layer 26) on which the wiring layer is arranged. Therefore, it is possible to improve use efficiency of material of the insulating layer, and to provide a display unit in which a surface property of the insulating layer is maintained and having excellent quality of appearance.

3. Application Examples

Each of the display units 1 and 1A described in the embodiment and the modification example may be suitably used for any of electronic apparatuses to be hereinafter described, for example.

Application Example 1

FIG. 18A illustrates an appearance of a smartphone from a front side, and FIG. 18B illustrates an appearance of the smartphone from a rear side. The smartphone may have, for example, a display section 610 (display unit 1) and a non-display section (casing) 620, and an operating section 630. The operating section 630 may be provided on a front face of the non-display section 620 as illustrated in FIG. 18A, or on an upper face as illustrated in FIG. 18B.

Application Example 2

FIG. 19 illustrates an appearance of a television set according to application example 2. The television set may have, for example, an image display screen section 200 including a front panel 210 and a filter glass 220, and the image display screen section 200 corresponds to any of the display units described above.

Application Example 3

FIG. 20A illustrates an appearance of a digital camera according to application example 3 from a front side, and FIG. 20B illustrates an appearance of the digital camera from a rear side. The digital camera may have, for example, a flash light-emitting section 310, a display section 320 serving as any of the display units described above, a menu switch 330, and a shutter button 340.

Application Example 4

FIG. 21 illustrates an appearance of a notebook personal computer according to application example 4. The notebook personal computer may have, for example, a main body 410, a keyboard 420 for an input operation of characters, etc., and a display section 430 serving as any of the display units described above.

Application Example 5

FIG. 22 illustrates an appearance of a video camera according to application example 5. The video camera may have, for example, a main body section 510, a lens 520 for shooting an object provided on a front side face of the main body section 510, a start/stop switch 530 during shooting, and a display section 540 serving as any of the display units described above.

Application Example 6

FIG. 23A illustrates a front view, a left side view, a right side view, a top view, and a bottom view in a closed state of a mobile phone according to application example 6. FIG. 23B illustrates a front view and a side view in an opened state of the mobile phone. The mobile phone may have a configuration in which, for example, an upper body 710 and a lower body 720 are connected through a connection part (hinge part) 730, and may have a display 740, a sub-display 750, a picture light 760, and a camera 770. The display 740 or the sub-display 750 corresponds to any of the display units described above.

As described above, the present disclosure is described with reference to the example embodiment, the modification example, and the application examples. However, contents of the present disclosure are not limited to those of the embodiments and the like described above, and the embodiments and the like may be variously modified. For example, the above-described material and thickness of each layer, or the film formation methods and the film formation conditions described in the embodiments and the like are non-limiting. Other materials and thicknesses may be used, or other film formation methods and film formation conditions may be used.

Furthermore, the technology encompasses any possible combination of some or all of the various embodiments described herein and incorporated herein.

It is possible to achieve at least the following configurations from the above-described example embodiments of the disclosure.

(1) A display unit including:

a laminated structure including two first wirings, a first insulating layer, and a concave part, the first wirings being adjacent to each other, the first insulating layer being provided on the first wirings and being made of an organic material, and the concave part penetrating, between the first wirings, from the first insulating layer to the first wirings in a laminated direction; and

a second insulating layer provided in the concave part and on the laminated structure.

(2) The display unit according to (1), further including a second wiring provided between the first insulating layer and the second insulating layer,

wherein the first insulating layer includes a step between a lower part of the second wiring and a region of the first insulating layer excluding the lower part.

(3) The display unit according to (1) or (2), wherein one or both of the first wirings is a gate electrode, is a source electrode, a drain electrode, or both, or is a plurality of metal layers configuring a multilayer wiring layer.

(4) The display unit according to (3), wherein

the multilayer wiring layer includes an inter-layer insulating layer made of an organic material, and

the metal layers are arranged to be substantially orthogonal with respect to each other with the inter-layer insulating layer interposed in between.

(5) The display unit according to any one of (1) to (4), wherein the concave part is formed at a short-circuit part of the first wirings.

(6) The display unit according to any one of (1) to (5), wherein the second insulating layer is made of an organic material.

(7) A method of manufacturing a display unit, the method including:

forming a laminated structure including, in recited order, two first wirings and a first insulating layer, the first wirings being adjacent to each other and the first insulating layer being made of an organic material;

forming a concave part that penetrates from the first insulating layer to the first wirings in a laminated direction, by applying laser light from a side on which the first insulating layer is provided to a short-circuit part formed between the first wirings;

performing half-ashing on an irradiation surface of the laser light and a peripheral region that includes the irradiation surface; and

forming a second insulating layer in the concave part and on the laminated structure after the performing the half-ashing.

(8) The method of manufacturing the display unit according to (7), further including, after the forming the concave part, applying laser light having a narrower irradiation width than an irradiation width of the laser light to a bottom surface of the concave part, to a start point of the laser application, and to an end point of the laser application.

(9) The method of manufacturing the display unit according to (7) or (8), wherein the performing the half-ashing includes performing a plasma treatment.

(10) The method of manufacturing the display unit according to (9), wherein oxygen is used in the plasma treatment.

(11) The method of manufacturing the display unit according to any one of (7) to (10), wherein the laser light has a wavelength in a range from about 10 nm to about 400 nm.

(12) An electronic apparatus provided with a display unit, the display unit including:

a second insulating layer provided in the concave part and on the laminated structure.

It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present subject matter and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims.

DISPLAY UNIT, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

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