Patent Grant
8072446
This application claims the priority benefit of Taiwan application serial no. 96126885, filed on Jul. 24, 2007. All disclosure of the Taiwan application is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display driving control technology, and more particularly, to a driving control technology with power-saving function.
2. Description of Related Art
With the development of technology, displays have been very widely used. Based on the persistence of vision, when the display consecutively updates the images of the display panel such that more than twenty-four frames are presented per second, the human eye will be given an illusion that the displayed images are animated images. The time for the display to present one frame is usually referred to as one frame time, which is about 16.6 ms. The operation of the display to display the frames is further described below.
During the period of displaying the frame 100 by the LCD 10, the timing controller 20 may also output a timing control signal to a gate buffer 70 to enable the gate buffer 70 to timely turn on the corresponding transistors (not shown) of the display panel 60. In addition, the timing controller 20 may also output a timing control signal to a common electrode buffer 80 to enable the common electrode buffer 80 to provide positive or negative common electrode voltage to the display panel 60. Operation of the LCD 10 to display other frames (i.e., frame 101 or the like) may be substantially the same as those described above and is therefore not repeated herein.
It should be noted that, during the period of displaying each frame, the LCD 10 is constantly in a displaying mode. In the displaying mode, all of the memory voltage VSRAM, digital to analog converting voltage VDAC, source voltage VSP, common electrode high voltage VCOMH, common electrode low voltage VCOML, gate high voltage VGH and gate low voltage VGL are maintained at a fixed value. Furthermore, the oscillation frequency of the oscillator (not shown) inside the timing controller 20 is maintained at a fixed value. In other words, the conventional LCD 10 does not have a power-saving function during the displaying period of each frame.
The present invention is directed to a display with reduced power consumption.
The present invention is also directed to a driving control method for a display that can achieve a power-saving function.
The present invention provides a driving control method for a display comprising a driving control module. The driving control method comprises displaying a plurality of frames. The step of displaying each of the frames comprises, during a first period, entering a displaying mode of the display; and during a second period, entering a power-saving mode of the display by adjusting operating parameters of the driving control module.
According to an embodiment of the present invention, the step of entering the power-saving mode of the display by adjusting operating parameters of the driving control module comprises stopping providing an operating voltage or a bias current to at least one of a source buffer, a digital to analog converter, a common electrode buffer and a gate buffer of the display.
According to an embodiment of the present invention, the step of entering the power-saving mode of the display by adjusting operating parameters of the driving control module comprises decreasing an operating voltage or a bias current provided to at least one of a source buffer, a digital to analog converter, a common electrode buffer and a gate buffer of the display.
According to an embodiment of the present invention, the step of entering a power-saving mode of the display by adjusting operating parameters of the driving control module comprises decreasing the oscillation frequency of an oscillator of the display. In another embodiment, the display is configured to display at least twenty-four frames per second. In another embodiment, a power-consumption of the display is decreased with decreasing of the length ratio of the first period to the second period. In still another embodiment, the display is a hold-type display.
In another aspect, the present invention provides a driving control method for a display comprising a driving control module. The driving control method comprises, during a first period, entering a displaying mode of the display to display a first frame; during a second period, entering a power-saving mode of the display by adjusting operating parameters of the driving control module and maintaining the first frame; and during a third period, entering the displaying mode of the display to display a second frame.
According to an embodiment of the present invention, the length of the first period is the same as the length of the third period, and the ratio of the first period to the second period is a fixed value.
In another aspect, the present invention provides a display comprising a display panel, a driving control module and a power-saving control module. The display panel is configured to display a plurality of frames. The driving control module is coupled to the display panel and configured to provide a driving signal of each of the frames to the display panel. The power-saving control module is coupled to the driving control module. A displaying period of each of the frames comprises a first period and a second period. During the first period, the display enters a displaying mode to display a first frame, and during the second period, the power-saving control module adjusts operating parameters of the driving control module such that the display enters a power-saving mode.
According to an embodiment of the present invention, the power-saving control module decreases one of an operating voltage or a bias current provided to the driving control module when the display enters the power-saving mode. In another embodiment, the power-saving control module stops providing one of an operating voltage and a bias current to the driving control module when the display enters the power-saving mode. In another embodiment, the display further comprises a timing controller coupled to the driving control module and the power-saving control module, the timing controller configured to provide a timing control signal and a power-saving switch signal. In another embodiment, the timing controller comprises an oscillator configured to generate an operating frequency of the timing controller according to the power-saving switch signal. In still another embodiment, the oscillator decreases the operating frequency when the display enters the power-saving mode.
According to an embodiment of the present invention, the driving control module comprises a common electrode buffer, a gate buffer, a source buffer, a digital to analog converter and a display data memory. The common electrode buffer, the gate buffer and the source buffer are all coupled to the display panel, the timing controller and the power-saving control module. The digital to analog converter is coupled to the source buffer, the timing controller and the power-saving control module. The display data memory is coupled to the digital to analog converter, the timing controller and the power-saving control module.
According to an embodiment of the present invention, the power-saving control module comprises first, second and third power switches. The first power switch is coupled to the common electrode buffer and configured to output one of a common electrode high voltage or a common electrode low voltage to the common electrode buffer according to the power-saving switch signal and the timing control signal. The second power switch is coupled to the source buffer and configured to determine whether to provide a source voltage to the source buffer according to the power-saving switch signal. The third power switch is coupled to the digital to analog converter and configured to determine whether to provide a digital-to-analog converting voltage to the digital to analog converter according to the power-saving switch signal.
A first power regulator is coupled to the display data memory. The first power regulator is configured to provide a memory voltage to the display data memory and to determine whether to decrease the memory voltage according to the power-saving switch signal. A second power regulator is coupled to the gate buffer. The second power regulator is configured to provide one of the gate high voltage and the gate low voltage to the gate buffer and to determine whether to decrease the one of a gate high voltage and a gate low voltage according to the power-saving switch signal and the timing control signal.
The display of the present invention displays multiple frames, and the displaying period of each frame includes a first period and a second period. During the first period, the display enters a displaying mode. During a second period, the display enters a power-saving mode by adjusting operating parameters of a driving control module. As a result, the power consumption of the display can be significantly reduced.
In order to make the aforementioned and other features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Conventionally, the display is always in a displaying mode during a frame is being displayed and therefore has a high power consumption. To solve this problem, in the embodiments of the present invention, the displaying period of each frame is divided into a first period and a second period. During the first period, the display enters a displaying mode to display the frame. The display enters a power-saving mode by adjusting operating parameters of a driving control module during the second period, and the display maintains the displayed frame during the second period. As such, the power consumption of the display can be significantly reduced. The configuration of the display is described below in greater detail.
The display panel 60 is used to display a plurality of frames. The driving control module 410 is coupled to the display panel 60, for providing a driving signal of each frame to the display panel 60. The power-saving control module 400 is coupled to the driving control module 410 to adjust operating parameters of the driving control module 410. Specifically, the power-saving control module 400 is used to control or adjust an operating voltage or a bias current that is provided to various devices of the driving control module 410. The timing controller 20 is coupled to the driving control module 410 and the power-saving control module 400, for providing a timing control signal STC and a power-saving switch signal SPS. The timing control signal STC is used to control operation timing of various devices of the LCD 11 to match the timing of displaying each frame. The power-saving switch signal SPS is used to control the LCD 11 to enter the displaying mode or the power-saving mode. The timing controller 20 includes an oscillator 22. The oscillation frequency of the oscillator 22 may be used as the operation frequency of the timing controller 20 and may be adjusted according to the power-saving signal SPS.
The driving control module 410 includes a common electrode buffer 80, a gate buffer 70, a source buffer 50, a digital to analog converter 40 and a display data memory 30.
On the other hand, the power-saving control module 400 includes power switches 421, 422 and 423 and power regulators 431 and 432. When the LCD 11 enters the power-saving mode, the power-saving control module 400 may stop supplying the operation voltages or bias currents to parts of the devices of the driving control module 410, or adjust the operation voltages or bias currents provided to the part of the devices of the driving control module 410, thereby reducing the power consumption of the LCD 11.
The power switch 421 is coupled to the common electrode buffer 80 to receive the common electrode high and low voltage VCOMH and VCOML, and may determine whether to output the common electrode high voltage VCOMH or the common electrode low voltage VCOML to the common electrode buffer 80 according to the signals SPS and STC. The power switch 422 is coupled to the source buffer 50 to receive the source voltage VSP, and may determine whether to output the voltage VSP to the source buffer 50 according to the signal SPS. The power switch 423 is coupled to the digital to analog converter 40 to receive the digital-to-analog converting voltage VDAC, and may determine whether to output the voltage VDAC to the digital to analog converter 40 according to the signal SPS.
The power regulator 431 is coupled to the display data memory 30 to receive the memory voltage VSRAM, and may determine whether to adjust the memory voltage VSRAM of the display data memory 30 according to the signal SPS. The power regulator 432 is coupled to the gate buffer 70 to receive the voltage VGP, and may supply the gate high voltage VGH or the gate low voltage VGL to the gate buffer 70 according to the signal SPS. The operation of the LCD 11 is described below in greater detail.
Displaying of the frame 100 by the LCD 11 is described first below. First, during period 100a, the LCD 11 enters the displaying mode (S501). In the displaying mode, the scan frequency of the LCD 11 may be increased such that the scan action of the frame 100 is completed during the period 100a.
The timing controller 20 may output the image information of the frame 100 to the display data memory 30 according to the timing. Afterwards, the digital to analog converter 40 converts the image information of the frame 100 stored in the display data memory 30 into an analog voltage. The source buffer 50 then outputs the voltage into corresponding transistors (not shown) of the display panel 60.
Besides, during the period 100a, the timing controller 20 may also output the signal STC to the gate buffer 70, so that the gate buffer 70 can timely turn on corresponding transistors (not shown) of the display panel 60, allowing the corresponding transistors to receive the analog voltage outputted from the source buffer 50. In addition, the timing controller 20 may also output the signal STC to the common electrode buffer 80, so that the common electrode buffer 80 can provide positive or negative common electrode voltage to the display panel 60 for polarity inversion. With the cooperative operation of the devices described above, the display panel 60 can display the frame 100.
It should be noted that, during the period 100b, the operating parameters of the driving control module 410 may be adjusted by the power-saving control module 400 so that the LCD 11 enters the power-saving mode (step S502). Generally speaking, the penetrability of the liquid crystal (not shown) light valve of the display panel 60 is usually controlled by voltage. In other words, the liquid crystal light valve of the display panel 60 will maintain its previous penetrability when no control voltage is received. Thus, even if the LCD 11 enters the power-saving mode during the period 100b, the display panel 60 can maintain the frame 100 without significantly affecting the image quality.
During the power-saving mode, the power switch 421 may selectively switch off one of the voltage VCOMH′ and VCOML′ according to polarity of the signal STC. Specifically, when the signal STC is positive, the display panel 60 needs only the voltage VCOMH′, and the voltage VCOML′ can be turned off. On the contrary, when the signal STC is negative, the display panel 60 needs only the voltage VCOML′, and the voltage VCOMH′ can be turned off.
In addition, the source buffer 50 and the digital to analog converter 40 need not provide the image information of the frame 100 to the display panel 60, and the gate buffer 70 need not switch on or off the transistors of the display 60 during the power-saving mode. Therefore, the power switch 422 may stop providing the voltage VSP to the source buffer 50, the power switch 423 may stop providing the voltage VDAC to the digital to analog converter 40, and the power regulator 432 may stop providing the voltage VGH and decrease the voltage VGL′.
Further, during the power-saving mode, the oscillator 22 may lower the operating frequency of the timing controller 20, and the power regulator 431 may also decrease the voltage VSRAM to the display data memory 30, so that the timing controller 20 can pre-store the frame 101 into the display data memory 30. It should be understood that those skilled in the art would be able to understand operation of the LCD 11 to display the frame 101 and later frames as described above with respect to the displaying of the frame 100 and, thus, the displaying of the frame 101 and later frames is not repeated herein.
Compared to the prior art, the embodiment of the present invention increases the scan frequency so as to complete the scan action of the frame 100 during the period 100a. As a result, the voltage or current provided to the driving control module 410 can be decreased or turned off during the period 100b, thereby significantly reduce the power consumption of the LCD 11. In addition, one frame time of the embodiment of the present invention is the same as that of the prior art and, therefore, the display of the embodiment of the present invention can also display twenty-four or more frames per second. That is to say, the embodiment of the present invention can also ensure the fluency of the images.
A possible embodiment of the display and the driving control method are described above. It should be understood, however, that the design of the display and the driving control method could vary with different companies and, thus, the present invention should not be limited to the possible embodiment described above. In other words, the display may be implemented in another form as long as the display can enter the displaying mode during a first period to display a frame and can enter a power-saving mode during a second period by adjusting operating parameters of the driving control module to maintain the displayed frame. More examples are described below to comprehensively illustrate the present invention.
For example, in the power-saving mode, it should be understood that the present invention may decrease or stop providing the operating voltage or bias current to other devices of the display. Examples of the other devices include, but are not limited to, a shift register, level shifter, digital buffer, or the like.
In addition, though the displaying period of each frame is divided into first and second periods, it should be understood, however, that the displaying period of each frame could be divided into multiple periods such that the displaying mode and power-saving mode are alternately arranged.
In summary, during a first period of displaying a frame, the display of the present invention enters a displaying mode. During a second period of displaying the frame, the display enters a power-saving mode by adjusting operating parameters of a driving control module. As a result, the power consumption of the display can be significantly reduced. In addition, the present invention has at least the following advantages.
1. In the power-saving mode, the power-saving control module is operable to decrease the operating voltage or bias current provided to the devices of the driving control module, thereby significantly reducing the power consumption without influencing the image quality.
2. In the power-saving mode, the power-saving control module is operable to stop providing the operating voltage or bias current to the devices of the driving control module, thereby ensuring the image quality as usual, and also significantly reducing the power consumption.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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