Display with Silicon Gate Drivers and Semiconducting Oxide Pixels

Abstract

A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Description

BACKGROUND

This relates generally to electronic devices with displays and, more particularly, to display driver circuitry for displays such as organic light-emitting diode (OLED) displays.

Electronic devices often include displays. For example, cellular telephones, tablets, wrist-watches, and portable computers typically include displays for presenting image content to users. OLED displays have an array of display pixels based on light-emitting diodes. In this type of display, gate driver circuitry is used to provide control signals to respective rows in the array of display pixels. It can be challenging to design the gate driver circuitry.

SUMMARY

An electronic device may include a display having an array of display pixels. The display pixels may be organic light-emitting diode display pixels. Each display pixel may include an organic light-emitting diode (OLED) that emits light, one or more storage capacitor, and only semiconducting oxide transistors such as n-type semiconducting oxide transistors. The array of display pixels can be driven using a chain of gate driver circuits. The gate driver circuits can be implemented using only silicon transistors such as p-type low-temperature polysilicon transistors. Implementing all of the pixel transistors as semiconducting oxide transistors can enable low refresh rate operations such as display refresh rates lower than 10 Hz or as low as 1 Hz or less, whereas implementing all of the gate driver transistors as silicon transistors can help improve the robustness of the gate drivers.

Each of the gate driver circuits can include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit can be configured to receive first and second shift register clock signals, to receive a carry in signal, and to generate a carry out signal. The output buffer subcircuit can be configured to receive an output buffer clock signal and to generate a corresponding gate output signal. The output buffer subcircuit can include: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and having a second source-drain terminal at which the gate output signal is generated; a second transistor having a first source-drain terminal coupled to the second source-drain terminal of the first transistor and having a second source-drain terminal coupled to a power supply line; and a third transistor having a first source-drain terminal coupled to a gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register subcircuit, and a gate terminal configured to receive the second shift register clock signal.

In some embodiments, the output buffer subcircuit can include a first capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal configured to receive the first shift register clock signal, a fourth transistor coupled between a carry output port of the shift register subcircuit on which the carry out signal is generated and a gate terminal of the first transistor, a fifth transistor having a first source-drain terminal configured to receive an additional gate output signal and having a second source-drain terminal coupled to the gate terminal of the first transistor, a second capacitor coupled between the second source-drain terminal of the fifth transistor and the gate terminal of the first transistor, and a third capacitor coupled between the gate terminal of the first transistor and the power supply line.

In some embodiments, the output buffer subcircuit can include a fourth transistor coupled between a carry output port of the shift register subcircuit on which the carry out signal is generated and a gate terminal of the first transistor and a second capacitor coupled across the gate terminal and the second source-drain terminal of the first transistor.

In some embodiments, the output buffer subcircuit can include a fourth transistor coupled between a gate terminal of the first transistor and a node in the shift register subcircuit, a fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a first source-drain terminal configured to receive the first shift register clock signal, and a second source-drain terminal, a sixth transistor coupled between the second source-drain terminal of the fifth transistor and an additional power supply line, and a second capacitor coupled across the gate terminal and the second source-drain terminal of the fifth transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an illustrative electronic device having a display in accordance with some embodiments.

FIG. 2 is a diagram of an illustrative display having an array of organic light-emitting diode display pixels coupled to gate driver circuitry in accordance with some embodiments.

FIG. 3 is a circuit diagram of an illustrative display pixel in accordance with some embodiments.

FIG. 4 is a timing diagram illustrating short gate pulses that are used for successive data loading operations in accordance with some embodiments.

FIG. 5A is a circuit diagram of an illustrative gate driver circuit having a shift register subcircuit and an output buffer subcircuit in accordance with some embodiments.

FIG. 5B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 5A in accordance with some embodiments.

FIG. 5C is a block diagram showing multiple gate driver circuits coupled together in a chain in accordance with some embodiments.

FIG. 5D is a timing diagram showing various clock signal waveforms that can be used to control multiple gate driver circuits connected in a chain in accordance with some embodiments.

FIG. 6A is a circuit diagram of an illustrative gate driver circuit that includes additional isolation transistors for mitigating coupling from an output buffer clock signal in accordance with some embodiments.

FIG. 6B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 6A in accordance with some embodiments.

FIG. 7A is a circuit diagram of an illustrative gate driver circuit having a shift-register subcircuit and an output buffer subcircuit powered using different ground voltages in accordance with some embodiments.

FIG. 7B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 7A in accordance with some embodiments.

FIG. 8A is a circuit diagram of an illustrative gate driver circuit having a shift-register subcircuit that generates a carry out signal and having an output buffer subcircuit that receives the carry out signal and a gate output signal from another gate driver circuit in a preceding row in accordance with some embodiments.

FIG. 8B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 8A in accordance with some embodiments.

FIG. 8C is a block diagram showing multiple gate driver circuits of the type shown in FIG. 8A coupled together in a chain in accordance with some embodiments.

FIG. 9A is a circuit diagram of an illustrative gate driver circuit having a shift-register subcircuit that generates a carry out signal and having an output buffer subcircuit that does not receive the carry out signal in accordance with some embodiments.

FIG. 9B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 9A in accordance with some embodiments.

FIG. 10A is a circuit diagram of an illustrative gate driver circuit having a shift-register subcircuit that generates a carry out signal and having an output buffer subcircuit that does not receive the carry out signal in accordance with some embodiments.

FIG. 10B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 10A in accordance with some embodiments.

FIG. 11A is a circuit diagram of another implementation of an illustrative gate driver circuit in accordance with some embodiments.

FIG. 11B is a timing diagram showing illustrative waveforms involved in operating the gate driver circuit shown in FIG. 11A in accordance with some embodiments.

FIG. 11C is a block diagram showing multiple gate driver circuits of the type shown in FIG. 11A coupled together in a chain in accordance with some embodiments.

FIG. 12 is a circuit diagram of another implementation of an illustrative gate driver circuit in accordance with some embodiments.

FIG. 13 is a circuit diagram of another implementation of an illustrative gate driver circuit configured to receive a reset signal in accordance with some embodiments.

DETAILED DESCRIPTION

An illustrative electronic device of the type that may be provided with a display is shown in FIG. 1. As shown in FIG. 1, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10. The storage and processing circuitry may include storage such as hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Processing circuitry in control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

Input-output circuitry in device 10 such as input-output devices 12 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scrolling wheels, touch pads, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 12 and may receive status information and other output from device 10 using the output resources of input-output devices 12.

Input-output devices 12 may include one or more displays such as display 14. Display 14 may be a touch screen display that includes a touch sensor for gathering touch input from a user or display 14 may be insensitive to touch. A touch sensor for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, a light-based touch sensor, or other suitable touch sensor arrangements.

Control circuitry 16 may be used to run software on device 10 such as operating system code and applications. During operation of device 10, the software running on control circuitry 16 may display images on display 14 using an array of pixels in display 14. Device 10 may be a tablet computer, laptop computer, a desktop computer, a display, a cellular telephone, a media player, a wristwatch device or other wearable electronic equipment, or other suitable electronic device.

Display 14 may be an organic light-emitting diode display or may be a display based on other types of display technology. Configurations in which display 14 is an organic light-emitting diode (OLED) display are sometimes described herein as an example. This is, however, merely illustrative. Any suitable type of display may be used in device 10, if desired.

Display 14 may have a rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular peripheral edge that runs around the rectangular footprint) or may have other suitable shapes. Display 14 may be planar or may have a curved profile.

A top view of a portion of display 14 is shown in FIG. 2. As shown in FIG. 2, display 14 may have an array of pixels 22 formed on a substrate 36. Substrate 36 may be formed from glass, metal, plastic, ceramic, porcelain, or other substrate materials. Pixels 22 may receive data signals over signal paths such as data lines D (sometimes referred to as data signal lines, column lines, etc.) and may receive one or more control signals over control signal paths such as horizontal control lines G (sometimes referred to as gate lines, scan lines, emission lines, row lines, etc.). There may be any suitable number of rows and columns of pixels 22 in display 14 (e.g., tens or more, hundreds or more, or thousands or more).

Each pixel 22 may have a light-emitting diode 26 that emits light 24 under the control of a pixel control circuit formed from thin-film transistor circuitry such as thin-film transistors 28 and thin-film capacitors). Thin-film transistors 28 may be polysilicon thin-film transistors, semiconducting oxide thin-film transistors such as indium zinc gallium oxide transistors, or thin-film transistors formed from other semiconductors. Pixels 22 may contain light-emitting diodes of different colors (e.g., red, green, and blue) to provide display 14 with the ability to display color images.

Display 14 may also include source driver circuit 30 and gate driver circuitry 34 formed on substrate 36. Source driver circuitry 30 and gate driver circuitry 34 may be used in controlling the operation of pixels 22. The source driver circuitry 30 may be formed from integrated circuits, thin-film transistor circuits, or other suitable electronic circuitry. Source driver circuitry 30 of FIG. 2 may contain communications circuitry for communicating with system control circuitry such as control circuitry 16 of FIG. 1 over path 32. Path 32 may be formed from traces on a flexible printed circuit or other cable. During operation, the control circuitry (e.g., control circuitry 16 of FIG. 1) may supply circuitry 30 with information on images to be displayed on display 14.

To display the images on display pixels 22, source driver circuitry 30 may supply image data to data lines D (e.g., data lines that run down the columns of pixels 22) while issuing clock signals and other control signals to support other display driver circuitry such as gate driver circuitry 34 over path 38. If desired, source driver circuitry 30 may also supply clock signals and other control signals to additional gate driver circuitry such as gate driver circuitry 34′ on an opposing edge of display 14 (e.g., the gate driver circuitry may be formed on more than one side of the display pixel array). If desired, gate driver circuitry can be formed along three different edges of the pixel array or can be formed along four different edges of the pixel array.

Gate driver circuitry 34 (sometimes referred to as horizontal line control circuitry or row driver circuitry) may be implemented as part of an integrated circuit and/or may be implemented using thin-film transistor circuitry. Horizontal/row control lines G in display 14 may carry gate line signals (scan line control signals or scan signals), emission enable control signals (emission signals), and/or other horizontal control signals for controlling the pixels in each row. There may be any suitable number of horizontal control signals per row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.). Gate driver circuitry 34 may include multiple gate driver circuits connected in a chain. For example, each gate driver may be configured to generate one or more scan signals and/or carry signals that are fed forward to a succeeding gate driver in the chain or that are fed back to a preceding gate driver in the chain.

The active components within display 14 may be implemented using thin-film transistors such as semiconducting oxide transistors and silicon transistors. “Semiconducting oxide” transistors can be defined herein as thin-film transistors having a channel region formed from semiconducting oxide material (e.g., indium gallium zinc oxide or IGZO, indium tin zinc oxide or ITZO, indium gallium tin zinc oxide or IGTZO, indium tin oxide or ITO, or other semiconducting oxide material) and are generally n-type (n-channel) transistors. In contrast, “silicon transistors” can be defined herein as thin-film transistors having a channel region formed from silicon material such as polysilicon deposited using a low temperature process. Silicon transistors having such type of polysilicon active material deposited using a low temperature process are thus sometimes referred to as LTPS (low temperature polysilicon) transistors.

In accordance with an embodiment, pixels 22 within the active area of display 14 can be implemented using only semiconducting oxide (e.g., n-type) transistors. In other words, pixels 22 do not include any silicon transistors. Semiconducting oxide transistors exhibit lower leakage than silicon transistors, so implementing pixels 22 using only semiconducting oxide transistors can be beneficial and technically advantage by helping to reduce flicker (e.g., by preventing current from leaking away from one or more storage nodes within pixel 22) and by enabling display 14 to operate at low refresh rates. For example, implementing pixels 22 using only semiconducting oxide transistors can enable display 14 to operate using refresh rates lower than 60 Hz, lower than 30 Hz, lower than 10 Hz, at 1 Hz, at 2 Hz, at 1-10 Hz, or less than 1 Hz. The example of FIG. 2 in which pixel 22 includes only semiconducting oxide transistors is illustrative. If desired, each pixel 22 can include one or more semiconducting oxide transistors and/or can include one or more silicon transistors.

In contrast to pixels 22, gate driver circuitry 34 formed along a peripheral edge of display 14 can be implemented using only silicon (e.g., LTPS) transistors. In other words, gate driver circuitry 34 does not include any semiconducting oxide transistors. As an example, gate driver circuitry 34 can be implemented using only p-type metal-oxide-semiconductor (PMOS) silicon transistors. As another example, gate driver circuitry 34 can be implemented using only n-type metal-oxide-semiconductor (NMOS) silicon transistors. As another example, gate driver circuitry 34 can be implemented using both PMOS and NMOS silicon transistors. Silicon transistors offer improved reliability and robustness compared to semiconducting oxide transistors, so implementing gate driver circuitry 34 using only silicon transistors can be beneficial and technically advantageous by prolonging the lifetime of gate driver circuitry 34 where a lot of switching activity takes place and where leakage is not as big of a concern relative to pixels 22. The example of FIG. 2 in which pixel 22 includes only silicon transistors is illustrative. If desired, gate driver circuitry 34 can include one or more silicon transistors and/or can include one or more semiconducting oxide transistors.

FIG. 3 is a circuit diagram of an illustrative display pixel 22 within display 14. As shown in FIG. 3, display pixel 22 may include a light-emitting element such as an organic light-emitting diode 26, one or more capacitors such as storage capacitor Cst, and thin-film transistors such a drive transistor Tdrive and a data loading transistor Tdata. Light-emitting diode 26 may have an associated diode capacitance Coled (not shown). As described above, all of the transistors within pixel 22 such as transistors Tdrive and Tdata can be implemented as semiconducting oxide transistors.

Drive transistor Tdrive has a gate terminal G, a drain terminal D, and a source terminal S. The terms “source” and “drain” terminals that are used to describe current-conducting terminals of a transistor are sometimes interchangeable and may sometimes be referred to herein as “source-drain” terminals. For example, the drain terminal D of the drive transistor can be referred to as a first source-drain terminal, whereas the source terminal S of the drive transistor can be referred to as a second source-drain terminal, or vice versa. Transistor Tdrive and light-emitting diode 26 can be coupled in series between a positive power supply line and a ground power supply line. In the example of FIG. 3, storage capacitor Cst may be coupled across the gate and source terminals of drive transistor Tdrive. Data loading transistor Tdata may have a first source-drain terminal coupled to the gate terminal of transistor Tdrive, a second source-drain terminal coupled to a data line D (e.g., a column line carrying a data signal), and a gate terminal configured to receive a gate driver output signal GOUT from a gate line G. Gate output signal GOUT is therefore sometimes referred to as a gate line signal or a scan control signal.

Display pixel 22 shown in FIG. 3 is illustrative. If desired, pixel 22 can include additional transistors such as one or emission transistors (e.g., a transistor that is activated during an emission phase of pixel 22), one or more initialization transistors (e.g., a transistor that is activated during an initialization phase to initialize an internal node of pixel 22 to an initialization voltage level or a reference voltage level), one or more anode reset transistors (e.g., a transistor that is activated during a reset phase to reset the anode terminal of diode 26 to a reset voltage level), one or more biasing transistors (e.g., a transistor that is activated during a threshold voltage sampling phase or an on-bias stress phase to bias an internal node of pixel 22 to a known voltage level), one or more additional capacitors (e.g., a capacitor configured to boost a drive current that flows through the drive transistor during the emission phase), and/or other additional components. If desired, pixel 22 can be controlled using one or more scan (row control) signals, two or more scan signals, three or more scan signals, one or more emission (row control) signals, two or more emission signals, other row control or column control signals, or other global control signal(s).

FIG. 4 is a timing diagram illustrating short gate pulses that can be used for loading data signals into successive rows of pixels 22. In FIG. 4, gate output signal GOUT(n) can be used to control the data loading transistors in pixels 22 in row n of the display pixel array, and gate output signal GOUT(n+1) can be used to control the data loading transistors in pixels 22 in row (n+1) of the display pixel array. As shown in FIG. 4, gate output signal GOUT(n) can be pulsed high to load data signals D(1) into a row of pixels, and gate output signal GOUT(n+1) can be subsequently pulsed high to load data signals D(2) into a succeeding row of pixels. Each of the gate pulses can have a pulse width that is fixed to one row time or less (e.g., the pulse width can be less than 1 H). The timing of signals GOUT that are used to control the data loading transistors (sometimes referred to as data loading scan signals or data programming control signals) is most critical since it has a tightest timing margin. Since the time duration for the data loading GOUT pulse can be fixed to one row time (1 H) or less, the gate driver circuit that generates these GOUT pulses must exhibit sufficient driving capability to drive signals GOUT high and low at the requisite speed of display 14.

In accordance with an embodiment, FIG. 5A is a circuit diagram of an illustrative gate driver circuit 40 configured to generate gate output signals GOUT with fast rise and/or fall times. As shown in FIG. 5A, gate driver 40 may include a logic subcircuit 42 and an output buffer subcircuit 44. The logic subcircuit 42 portion of gate driver 40 can receive a carry in signal CR_IN from a gate driver in a preceding row and can output a carry out signal CR_OUT to a gate driver in a succeeding row. Operated in this way, the logic subcircuit 42 is sometimes referred to and defined herein a “shift register” subcircuit 42. As an example, all of the transistors within gate driver circuit 40 are implemented as silicon transistors (e.g., all of transistors within gate driver 40 can be implemented as PMOS LTPS thin-film transistors).

Shift register subcircuit 42 may include transistors T1-T7 and TA and capacitors C_Q1 and C_QB1. Transistors T1-T8 and TA are therefore sometimes referred to as logic or shift register transistors. Transistor T1 may have a gate terminal coupled to node Q1, a drain terminal configured to receive a logic (shift register) clock signal CLK_B, and a source terminal coupled to a carry output port on which carry out signal CR_OUT is generated. Signal CR_OUT can be fed to one or more succeeding gate driver stages in the chain of gate drivers. Capacitor C_Q1 may be coupled across the gate and source terminals of transistor T1. Transistor T2 may have a drain terminal coupled to the carry output port, a gate terminal coupled to node QB1, and a source terminal coupled to high (positive) power supply voltage VGH. Capacitor C_QB1 may be coupled across the gate and source terminals of transistor T2. Voltage VGH may be 5 V, 6 V, 7 V, 3 to 10 V, greater than 10 V, greater than 15 V, 20 V, 15-25 V, greater than 20 V, or any suitable positive power supply voltage level.

Transistor TA may have a first source-drain terminal coupled to node Q1, a second source-drain terminal coupled to node Q0, and a gate terminal configured to receive low (ground) power supply voltage VGL. Power supply voltage VGL may be 0 V, −2 V, −4, −6V, less than −8 V, −10V, −5 to −15 V, less than −10 V, or any suitable ground or negative power supply voltage level.

Transistors T3, T7, and T6 may be coupled in series. In particular, transistor T3 may have a source terminal coupled to node Q0, a drain terminal configured to receive a carry in signal from a preceding stage via a feedforward path (e.g., to receive signal CR_IN from a previous gate driver stage in the chain), and a gate terminal configured to receive logic (shift register) clock signal CLK_A. Transistor T7 may have a drain terminal coupled to node Q0, a gate terminal configured to receive clock signal CLK_B, and a source terminal. Transistor T6 may have a drain terminal coupled to the source terminal of transistor T7, a gate terminal coupled to node QB1, and a source terminal coupled to high voltage VGH.

Transistor T5 may have a drain terminal coupled to power supply voltage VGL, a gate terminal configured to receive clock signal CLK_A, and a source terminal coupled to node QB1. Transistor T4 may have a first source-drain terminal coupled to node QB1, a second source-drain terminal configured to receive clock signal CLK_A, and a gate terminal coupled to node Q0.

Output buffer subcircuit 44 may include transistor T8 coupled in series with transistor T9. Transistors T8 and T9 in output buffer subcircuit 44 are sometimes referred to as output buffer transistors. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q1, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44 may also include transistor T11 and capacitor C_QB2. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive shift register clock signal CLK_B. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal configured to receive shift register clock signal CLK_A. Connected in this way, transistor T11 and capacitor C_QB2 can be used to ensure that node QB2 is less than VGL when output buffer transistor T9 needs to be turned on.

The shift register clock signals CLK_A and CLK_B controlling logic subcircuit portion 42 of gate driver 40 are separate and isolated from the output buffer clock signal CLK_BUF controlling the output buffer portion 44 of gate driver 40. Having isolated clock signals to control the two different portions of gate driver 40 allows the shift register subcircuit 42 to operate with more process margin and longer lifetime (e.g., by allowing the internal nodes within subcircuit 42 enough time to settle/stabilize) while enabling the output buffer subcircuit 44 to operate independently at a faster speed to satisfy the more stringent timing constraints dictated by the data programming phase. In general, the pulse width for the shift register (logic) clock signals can be as long as needed, whereas the pulse width for the output buffer clock signals can be as short as needed.

FIG. 5B is a timing diagram illustrating the operation of gate driver 40 of the type shown in FIG. 5A. As shown in FIG. 5B, clock signal CLK_B may be a delayed version of clock signal CLK_A (or vice versa). The shift register clock signals CLK_A and CLK_B also have a wider pulse width than the output buffer clock signal CLK_BUF, which allows time for the internal nodes within subcircuit 42 such as nodes Q1 and QB1 to settle.

At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node QB2 to fall from VGL to (2VGL−VGH) due to the capacitive coupling through capacitor C_QB2. At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped back up to VGL via capacitor C_QB2.

At time t3, signal CLK_B may be pulsed low (from time t3 to t6), which causes carry out signal CR_OUT to be pulsed low through transistor T1. At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL-VGH) by coupling through capacitor C_Q1. At time t3, node QB2 can be pull up (e.g., from VGL to VGH) using transistor T11.

At time t4, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t5, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level.

At time t6, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1.

At time t7, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40 is able to generate gate output signal GOUT having sufficiently fast rise and fall times.

FIG. 5C is a block diagram showing multiple gate driver circuits 40 of the type described in connection with FIGS. 5A and 5B coupled together in a chain. As shown in FIG. 5C, gate driver circuitry 34 may include a chain of gate drivers 40 such as gate drivers 40-1, 40-2, 40-3, and 40-4. Although only four gate drivers 40 are shown in FIG. 5C, gate driver circuitry 34 may include hundreds, or thousands of gate drivers 40 connected in a chain. Gate driver 40-1 can be configured to generate first gate output signal GOUT(4n+1). Gate driver 40-2 can be configured to generate second gate output signal GOUT(4n+2). Gate driver 40-3 can be configured to generate third gate output signal GOUT(4n+3). Gate driver 40-4 can be configured to generate fourth gate output signal GOUT(4n+4).

In the example of FIG. 5C, each gate driver 40 may receive a carry in signal from a gate driver two rows above and may thus generate a carry out signal that is fed forward to a gate driver two rows below. For example, gate driver 40-1 in row (4n+1) may receive a carry in signal from row (4n−1) and may output a carry out signal to row (4n+3). As another example, gate driver 40-3 in row (4n+3) may receive a carry in signal from row (4n+1) and may output a carry out signal to row (4n+5). This is merely illustrative. In general, gate driver 40 may receive a carry in signal from a gate driver in any preceding row (e.g., from one row above, two rows above, three rows above, four rows above, or more than four rows above) and may output a carry out signal to another gate driver in any succeeding row (e.g., to one row below, two rows below, three rows below, four rows below, or more than four rows below).

Although each gate driver 40 includes two shift register clock ports (e.g., CLK_A and CLK_B), gate driver circuitry 34 can be controlled using four different shift register clock signals CLK_SR_1, CLK_SR_2, CLK_SR_3, and CLK_SR_4. Clock signal CLK_SR_1 can be fed to the CLK_A port of a first gate driver in every group of four gate drivers 40 and can be fed to the CLK_B port of a third gate driver in every group of four gate drivers 40. Clock signal CLK_SR_2 can be fed to the CLK_A port of a second gate driver in every group of four gate drivers 40 and can be fed to the CLK_B port of a fourth gate driver in every group of four gate drivers 40. Clock signal CLK_SR_3 can be fed to the CLK_B port of a first gate driver in every group of four gate drivers 40 and can be fed to the CLK_A port of a third gate driver in every group of four gate drivers 40. Clock signal CLK_SR_4 can be fed to the CLK_B port of a second gate driver in every group of four gate drivers 40 and can be fed to the CLK_A port of a fourth gate driver in every group of four gate drivers 40.

Although each gate driver 40 includes one output buffer clock port (e.g., CLK_BUF), gate driver circuitry 34 can also be controlled using four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4. Clock signal CLK_BUF_1 can be fed to the CLK_BUF port of a first gate driver in every group of four gate drivers 40. Clock signal CLK_BUF_2 can be fed to the CLK_BUF port of a second gate driver in every group of four gate drivers 40. Clock signal CLK_BUF_3 can be fed to the CLK_BUF port of a third gate driver in every group of four gate drivers 40. Clock signal CLK_BUF_4 can be fed to the CLK_BUF port of a fourth gate driver in every group of four gate drivers 40.

FIG. 5D is a timing diagram showing at least some of the various clock signal waveforms that can be used to control the chain of gate drivers shown in FIG. 5C. As shown in FIG. 5D, shift register clock signal CLK_SR_3 may be a delayed version of shift register clock signal CLK_SR_1 and may have non-overlapping pulses. The shift register clock signals can toggle between power supply voltages VGL and VGH. At time ta, output buffer signal CLK_BUF_3 may be pulsed high during the pulse width of CLK_SR_1. At time tb, output buffer signal CLK_BUF_1 may be pulsed high during the pulse width of CLK_SR_3. Output buffer clock signals CLK_BUF_4 and CLK_BUF_2 may be similarly aligned to CLK_SR_2 and CLK_SR_4 (not shown in order to avoid obscuring the present embodiments). The output buffer clock signals can also toggle between power supply voltages VGL and VGH.

As described above, output buffer transistor T8 can be sized relatively large to ensure that the rise and fall times of gate output signal GOUT are sufficiently fast. A large transistor T8 typically results in a large parasitic gate capacitance that can couple the rising edge and the falling edge of the output buffer clock signal CLK_BUF to the gate terminal of T8. Such parasitic coupling can result in an inadvertent pulse at node Q1 (see pulse 50 at time t4 in FIG. 5B), which can also lead to an unintentional pulse in the carry out signal CR_OUT (see pulse 52 at time t4).

FIG. 6A shows another embodiment of gate driver circuit 40′ that includes additional transistors configured to isolate the output buffer clock signal CLK_BUF from nodes Q1 and the carry output port. As shown in FIG. 6A, gate driver 40′ may include shift register subcircuit 42 and output buffer subcircuit 44′. The shift register subcircuit 42 in gate driver 40′ of FIG. 6A may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40′ can be implemented as silicon transistors (e.g., all of transistors within gate driver 40′ can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44′ may include transistor T8 coupled in series with transistor T9. Transistors T8 and T9 in output buffer subcircuit 44′ are sometimes referred to as output buffer transistors. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44′ may also include transistor T11 and capacitor C_QB2. Transistor T11 has a first source-drain terminal coupled to node QB2 via path 58, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive shift register clock signal CLK_B. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal configured to receive shift register clock signal CLK_A. Connected in this way, transistor T11 and capacitor C_QB2 can be used to ensure that node QB2 is less than VGL when output buffer transistor T9 needs to be turned on.

Output buffer subcircuit 44′ may further include transistors T10, T1b, T2b, and capacitor C_Q2. Transistor T10 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node Q0 via path 56, and a gate terminal configured to receive low voltage VGL. Transistor T1b may have a first source-drain terminal configured to receive shift register clock signal CLK_B, a second source-drain terminal, and a gate terminal that is coupled to node Q2. Capacitor C_Q2 may be coupled across the gate terminal and the second source-drain terminal of transistor T1b. Transistor T2b may have a first source-drain terminal coupled to the second source-drain terminal of transistor T1b, a second source-drain terminal coupled to high voltage VGH, and a gate terminal that is coupled to node QB1 via path 58. Configured in this way, transistors T10, T1b, and T2b can collectively be used to isolate any parasitic coupling that might be coupled onto the gate terminal (node Q2) of T8 from the internal nodes of shift register subcircuit 42.

FIG. 6B is a timing diagram illustrating the operation of gate driver 40′ of the type shown in FIG. 6A. At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node QB2 to fall from VGL to (2VGL−VGH) due to the capacitive coupling through capacitor C_QB2. Node Q0 falling can also cause node Q2 to fall from VGH to VGL using transistor T10. At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped back up to VGL via capacitor C_QB2.

At time t3, signal CLK_B may be pulsed low (from time t3 to t6), which causes carry out signal CR_OUT to be pulsed low through transistor T1. During this time, node Q2 can also fall from VGL to (2VGL−VGH). At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL−VGH) by coupling through capacitor C_Q1. At time t3, node QB2 can be pull up (e.g., from VGL to VGH) using transistor T11.

At time t4, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t5, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level.

At time t6, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1, and node Q2 will rise back up to VGL as well.

At time t7, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. Node Q2 will also rise back up to VGH. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40′ is able to generate gate output signal GOUT having sufficiently fast rise and fall times.

As described above, output buffer transistor T8 can be sized relatively large to ensure that the rise and fall times of gate output signal GOUT are sufficiently fast. A large transistor T8 typically results in a large parasitic gate capacitance that can couple the rising edge and the falling edge of the output buffer clock signal CLK_BUF to the gate terminal of T8. Such parasitic coupling can result in an inadvertent pulse at node Q2 (see pulse 54 at time t4 in FIG. 6B). Isolating node Q2 from the internal nodes of shift register subcircuit 42 using transistor T10 in this way can be technically advantageous since the parasitic clock coupling will not affect the carry out waveform.

A plurality of gate drivers 40′ can be coupled together in a chain in a way similar to that already shown in FIG. 5C. The carry signals can be fed from one gate driver 40′ to another gate driver 40′. At least four different shift register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40′. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF ports in each group of four gate drivers 40′. The timing of these shift register clock signals and output buffer clock signals that are used to control a chain of gate drivers 40′ can be identical or similar to the waveforms already shown in FIG. 5D.

FIG. 7A shows another embodiment of gate driver circuit 40″ that is powered using two different low voltages VGL and VGL′. As shown in FIG. 7A, gate driver 40″ may include shift register subcircuit 42 and output buffer subcircuit 44″. The shift register subcircuit 42 in gate driver 40″ of FIG. 7A may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40″ can be implemented as silicon transistors (e.g., all of transistors within gate driver 40″ can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44″ may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44″ may also include transistor T11 and capacitor C_QB2. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive shift register clock signal CLK_B. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal configured to receive shift register clock signal CLK_A. Connected in this way, transistor T11 and capacitor C_QB2 can be used to ensure that node QB2 is less than VGL when output buffer transistor T9 needs to be turned on.

Output buffer subcircuit 44″ may further include transistors T10 and capacitor C_Q2. Transistor T10 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to the carry output port, and a gate terminal configured to receive low voltage VGL′. Low voltage VGL′ may be less than VGL (e.g., VGL′ may be at least one Vth less than VGL, where Vth represents the threshold voltage of transistor T10). Capacitor C_Q2 may be coupled across the gate terminal and the drain terminal of transistor T8.

FIG. 7B is a timing diagram illustrating the operation of gate driver 40″ of the type shown in FIG. 7A. At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node QB2 to fall from VGL to (2VGL−VGH) due to the capacitive coupling through capacitor C_QB2. At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped back up to VGL via capacitor C_QB2.

At time t3, signal CLK_B may be pulsed low (from time t3 to t6), which causes carry out signal CR_OUT to be pulsed low through transistor T1. During this time, node Q2 can also fall from VGH to VGL through transistor T10. At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL−VGH) by coupling through capacitor C_Q1. At time t3, node QB2 can be pull up (e.g., from VGL to VGH) using transistor T11.

At time t4, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t5, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 may be coupled down to a voltage below VGL through capacitor C_Q2.

At time t6, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1, and node Q2 will rise back up to VGH using transistor T10.

At time t7, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40″ is able to generate gate output signal GOUT having sufficiently fast rise and fall times.

A plurality of gate drivers 40″ can be coupled together in a chain in a way similar to that already shown in FIG. 5C. The carry signals can be fed from one gate driver 40″ to another gate driver 40″. At least four different shift register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40″. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF ports in each group of four gate drivers 40″. The timing of these shift register clock signals and output buffer clock signals that are used to control a chain of gate drivers 40″ can be identical or similar to the waveforms already shown in FIG. 5D.

FIG. 8A shows another embodiment of gate driver circuit 40′″ in which both carry signals and gate output signals are fed from a preceding gate driver to a succeeding gate driver. As shown in FIG. 8A, gate driver 40′″ may include shift register subcircuit 42 and output buffer subcircuit 44″″. The shift register subcircuit 42 in gate driver 40′″ of FIG. 8A may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40′″ can be implemented as silicon transistors (e.g., all of transistors within gate driver 40′″ can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44″ may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44″″ may also include transistor T11 and capacitor C_QB2. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive shift register clock signal CLK_B. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal configured to receive shift register clock signal CLK_A. Connected in this way, transistor T11 and capacitor C_QB2 can be used to ensure that node QB2 is less than VGL when output buffer transistor T9 needs to be turned on.

Output buffer subcircuit 44″ may further include transistors T10, T12 and capacitors C_Q21 and C_Q21. Transistor T10 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to the carry output port, and a gate terminal configured to receive low voltage VGL. Capacitor C_Q21 may have a first terminal coupled to node Q2 and a second terminal shunted (shorted) to VGL. In other embodiments, the second terminal of capacitor C_Q21 may instead be coupled (shorted) to VGH or other static voltage line. Capacitor C_Q22 may have a first terminal coupled to node Q2 and a second terminal coupled to transistor T12. Transistor T12 may have a first source-drain terminal coupled to capacitor C_Q22, a second source-drain terminal configured to receive signal GOUT_Prev (e.g., a gate output signal from a previous row), and a gate terminal configured to receive low voltage VGL. Transistors T10 and T12 can serve as isolation transistors for isolating any inadvertent parasitic coupling from signals CLK_BUF and GOUT_Prev from affecting the carry out signal CR_OUT. Capacitor C_Q22 can be used to push node Q2 to a lower voltage when GOUT_Prev is pulsed, whereas capacitor C_Q21 can be used as a storage capacitor that holds the charge at node Q2 after transistor T12 is turned off.

FIG. 8B is a timing diagram illustrating the operation of gate driver 40′″ of the type shown in FIG. 8A. At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node QB2 to fall from VGL to (2VGL−VGH) due to the capacitive coupling through capacitor C_QB2. At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped back up to VGL via capacitor C_QB2. At time t2, signal CLK_BUF can also be pulsed high for a short period of time.

At time t3, signal CLK_B may be pulsed low, which causes carry out signal CR_OUT to be pulsed low through transistor T1. During this time, node Q2 can also fall from VGH to a lower voltage through transistor T10. At the same time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL−VGH) by coupling through capacitor C_Q1. At time t3, node QB2 can be pull up (e.g., from VGL to VGH) using transistor T11.

At time t4, GOUT_Prev can be pulsed high. This can cause node Q2 to be pulled all the way down to VGL by the end of the falling edge of GOUT_Prev (at time t5).

At time t6, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t7, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level.

At time t8, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1, and node Q2 will rise back up to VGH using transistor T10.

At time t9, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40′″ is able to generate gate output signal GOUT having sufficiently fast rise and fall times.

FIG. 8C is a block diagram showing multiple gate driver circuits 40′″ of the type described in connection with FIGS. 8A and 8B coupled together in a chain. As shown in FIG. 8C, gate driver circuitry 34 may include a chain of gate drivers 40 such as gate drivers 40′″-1, 40′″-2, 40′″-3, and 40′″-4. Although only four gate drivers 40′″ are shown in FIG. 8C, gate driver circuitry 34 may include hundreds, or thousands of gate drivers 40′″ connected in a chain. Gate driver 40′″-1 can be configured to generate first gate output signal GOUT(4n+1). Gate driver 40′″-2 can be configured to generate second gate output signal GOUT(4n+2). Gate driver 40′″-3 can be configured to generate third gate output signal GOUT(4n+3). Gate driver 40′″-4 can be configured to generate fourth gate output signal GOUT(4n+4). The connection of the shift register clock signals and the output buffer clock signals are similar that already described in connection with FIG. 5C. FIG. 8C, however, also shows the gate output signals being fed from one stage to another (e.g., signal GOUT from one row is being fed to the GOUT_Prev port of a succeeding gate driver). The timing of these shift register clock signals and output buffer clock signals that are used to control a chain of gate drivers 40′″ can be identical or similar to the waveforms already shown in FIG. 5D.

FIG. 9A shows another embodiment of gate driver circuit 40″″ that is powered using power supply voltages VGL and VGH. As shown in FIG. 9A, gate driver 40″″ may include shift register subcircuit 42 and output buffer subcircuit 44″″. The shift register subcircuit 42 in gate driver 40″″ of FIG. 9A may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40″″ can be implemented as silicon transistors (e.g., all of transistors within gate driver 40″″ can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44″″ may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44″″ may also include transistor T11 and capacitor C_QB2. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive shift register clock signal CLK_B. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal configured to receive shift register clock signal CLK_A. Connected in this way, transistor T11 and capacitor C_QB2 can be used to ensure that node QB2 is less than VGL when output buffer transistor T9 needs to be turned on.

Output buffer subcircuit 44″″ may further include transistors T12-T15 and capacitor C_Q2. Capacitor C_Q2 may be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T12 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive low voltage VGL. Transistors T13 may have a drain terminal coupled to low voltage VGL, a gate terminal coupled to node Q1 in the shift register subcircuit 42, and a source terminal coupled to node A. Transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive clock signal CLK_B, and a source terminal coupled to transistor T15. Transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register subcircuit 42, and a source terminal coupled to high power supply voltage VGH.

FIG. 9B is a timing diagram illustrating the operation of gate driver 40″″ of the type shown in FIG. 9A. At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node QB2 to fall from VGL to (2VGL−VGH) due to the capacitive coupling through capacitor C_QB2. At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped back up to VGL via capacitor C_QB2.

At time t3, signal CLK_B may be pulsed low (from time t3 to t6), which causes carry out signal CR_OUT to be pulsed low through transistor T1. During this time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL−VGH) by coupling through capacitor C_Q1. At time t3, node QB2 can be pull up (e.g., from VGL to VGH) using transistor T11.

At time t4, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t5, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 may be coupled down to a voltage below VGL through capacitor C_Q2 (e.g., from VGL to 2VGL−VGH).

At time t6, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1.

At time t7, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40′″ is able to generate gate output signal GOUT having sufficiently fast rise and fall times. Node Q2 will later be driven back up to VGH at the following CLK_B pulse.

A plurality of gate drivers 40′″″ can be coupled together in a chain in a way similar to that already shown in FIG. 5C. The carry signals can be fed from one gate driver 40″″ to another gate driver 40″″. At least four different shift register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40″″. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF ports in each group of four gate drivers 40″″. The timing of these shift register clock signals and output buffer clock signals that are used to control a chain of gate drivers 40″″ can be identical or similar to the waveforms already shown in FIG. 5D.

FIG. 10A shows another embodiment of gate driver circuit 40′″″ that is powered using power supply voltages VGL and VGH. As shown in FIG. 10A, gate driver 40′″″ may include shift register subcircuit 42 and output buffer subcircuit 44′″″. The shift register subcircuit 42 in gate driver 40′″″ of FIG. 10A may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40′″″ can be implemented as silicon transistors (e.g., all of transistors within gate driver 40′″″ can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44′″″ may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44′″″ may also include transistor T11 and capacitor C_QB2. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive low voltage VGL. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal configured to receive shift register clock signal CLK_B. Connected in this way, transistor T5 in subcircuit 42 and capacitor C_QB2 can be used to ensure that node QB2 is less than VGL when output buffer transistor T9 needs to be turned on.

Output buffer subcircuit 44′″″ may further include transistors T12-T15 and capacitor C_Q2. Capacitor C_Q2 may be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T12 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive low voltage VGL. Transistors T13 may have a drain terminal coupled to low voltage VGL, a gate terminal coupled to node Q1 in the shift register subcircuit 42, and a source terminal coupled to node A. Transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive clock signal CLK_B, and a source terminal coupled to transistor T15. Transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register subcircuit 42, and a source terminal coupled to high power supply voltage VGH. The use of transistor T14 is optional. In embodiments where transistor T14 is omitted, node A can be directly connected to the drain terminal of T15. Omission of transistor T14 does not change the operation of gate driver 40′″″.

FIG. 10B is a timing diagram illustrating the operation of gate driver 40′″″ of the type shown in FIG. 10A. At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node Q2 to fall from VGH to VGL. At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped high to VGH via transistor T11.

At time t3, signal CLK_B may be pulsed low (from time t3 to t6), which causes carry out signal CR_OUT to be pulsed low through transistor T1. During this time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL−VGH) by coupling through capacitor C_Q1.

At time t4, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t5, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 may be coupled down to a voltage below VGL through capacitor C_Q2 (e.g., from VGL to 2VGL−VGH).

At time t6, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1.

At time t7, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low to VGL. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40′″″ is able to generate gate output signal GOUT having sufficiently fast rise and fall times. Node Q2 will later be driven back up to VGH at the following CLK_B pulse.

A plurality of gate drivers 40′″″ can be coupled together in a chain in a way similar to that already shown in FIG. 5C. The carry signals can be fed from one gate driver 40′″″ to another gate driver 40′″″. At least four different shift register clock signals CLK_SR1, CLK_SR_2, CLK_SR_3, and CLK_SR4 can be used to control the CLK_A and CLK_B ports in each group of four gate drivers 40′″″. Similarly, at least four different output buffer clock signals CLK_BUF_1, CLK_BUF_2, CLK_BUF_3, and CLK_BUF_4 can be used to control the CLK_BUF ports in each group of four gate drivers 40′″″″. The timing of these shift register clock signals and output buffer clock signals that are used to control a chain of gate drivers 40′″″ can be identical or similar to the waveforms already shown in FIG. 5D.

FIG. 11A is a circuit diagram of another implementation of gate driver circuit 40*. As shown in FIG. 11A, gate driver 40* may include shift register subcircuit 42 and output buffer subcircuit 44*. The shift register subcircuit 42 in gate driver 40* of FIG. 11A may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40* can be implemented as silicon transistors (e.g., all of transistors within gate driver 40* can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44* may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44* may also include transistors T11-T15 and capacitor C_Q2. Capacitor C_Q2 may be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive low voltage VGL. Transistor T12 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive low voltage VGL. Transistors T13 may have a drain terminal coupled to low voltage VGL, a gate terminal coupled to node Q1 in the shift register subcircuit 42, and a source terminal coupled to node A. Transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive clock signal CLK_B, and a source terminal coupled to transistor T15. Transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register subcircuit 42, and a source terminal coupled to high power supply voltage VGH.

Output buffer subcircuit 44* may further include transistor T16 and capacitors C_QB2 and C1. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal coupled to a node B. Capacitor C₁ may have a first terminal coupled to node B and a second terminal coupled to the low power supply voltage VGL. Transistor T16 may have a first source-drain terminal coupled to node B, a second source-drain terminal configured to receive shift register clock signal CLK_B, and a gate terminal coupled to the Q0 node of another gate driver 40* from three rows below (as indicated by the “n+3” notation). Configured in this way, transistor T16 can be used to maintain the voltage at node QB2 to be lower than VGL (e.g., turning transistor T16 off can isolate capacitor C_QB2 from any noise or toggling associated with clock signal CLK_B). The example of FIG. 12 in which the gate terminal of transistor T16 is coupled to Q0(n+3) via transistor T17 is illustrative. In other embodiments, the gate terminal of transistor T16 can be coupled to Q1 (n+3) (e.g., the Q1 node of another gate driver 40*** from three rows below) via transistor T17.

FIG. 11B is a timing diagram illustrating the operation of gate driver 40* of the type shown in FIG. 11A. At time t1, the carry in signal CR_IN from the prior row is pulsed low (from time t1 to t2), which may be synchronized with a CLK_A pulse that turns on transistors T3 and T5, may cause nodes Q0 and Q1 to fall from VGH to VGL and node Q2 to fall from VGH to VGL. FIG. 11B also shows the fall and rise times of nodes Q0 for the current row (e.g., row n) and subsequent rows such as rows (n+1), (n+2), and (n+3). At time t2, signals CR_IN and CLK_A may be driven high, which can cause node QB1 to be driven from VGL to VGH using transistor T4 and can cause node QB2 to be bumped high to VGH via transistor T11.

At time t3, signal CLK_B may be pulsed low (from time t3 to t6), which causes carry out signal CR_OUT to be pulsed low through transistor T1. During this time, node Q1 is pushed down to an even lower level (e.g., from VGL to 2VGL−VGH) by coupling through capacitor C_Q1.

At time t4, output buffer clock signal CLK_BUF may be pulsed high, which causes the gate output signal GOUT to be pulsed high through transistor T8. Clock signal CLK_BUF may have a pulse width PW_SC. At time t5, output buffer clock signal CLK_BUF may be deasserted, which causes the gate output signal GOUT to return to its initial level. At the falling edge of GOUT at time t5, node Q2 may be coupled down to a voltage below VGL through capacitor C_Q2 (e.g., from VGL to 2VGL−VGH).

At time t6, the rising edge of shift register clock signal CLK_B will cause carry out signal CR_OUT to return to its initial VGH level. At the same time, node Q1 will rise back up to VGL due to coupling through capacitor C_Q1.

At time t7, a CLK_A pulse while the feedforward carry in signal CR_IN is high will cause node Q0 to be reset to its initial high level while resetting node QB1 low to VGL. Node Q0 rising will also cause node Q1 to be driven back up to VGH via transistor TA. By having a separate (isolated) output buffer clock pulse CLK_BUF that is narrower than the shift register clock pulses in CLK_A and CLK_B, gate driver 40′″″ is able to generate gate output signal GOUT having sufficiently fast rise and fall times. Node Q2 will later be driven back up to VGH at the following CLK_B pulse. Note that using Q0(n+3) to control transistor T16 can help ensure that transistor T16 remains off before CLK_BUF is pulsed at time t4.

FIG. 11C is a block diagram showing multiple gate driver circuits 40* of the type described in connection with FIGS. 11A and 11B coupled together in a chain. As shown in FIG. 11C, gate driver circuitry 34 may include a chain of gate drivers 40* such as gate drivers 40*-1, 40*-2, 40*-3, and 40*-4. Although only four gate drivers 40* are shown in FIG. 11C, gate driver circuitry 34 may include hundreds, or thousands of gate drivers 40* connected in a chain. Gate driver 40*-1 can be configured to generate first gate output signal GOUT(4n+1). Gate driver 40*-2 can be configured to generate second gate output signal GOUT(4n+2). Gate driver 40*-3 can be configured to generate third gate output signal GOUT(4n+3). Gate driver 40*-4 can be configured to generate fourth gate output signal GOUT(4n+4). The connection of the shift register clock signals and the output buffer clock signals are similar that already described in connection with FIG. 5C. FIG. 11C, however, shows the Q0(n) being fed back to three stages above (e.g., the Q0 of driver 40*-4 is fed back to the Q0(n+3) input of driver 40*-1 and so on).

FIG. 12 is a circuit diagram of another implementation of a gate driver circuit such as gate driver circuit 40**. As shown in FIG. 12, gate driver 40** may include shift register subcircuit 42 and output buffer subcircuit 44**. The shift register subcircuit 42 in gate driver 40** of FIG. 12 may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40** can be implemented as silicon transistors (e.g., all of transistors within gate driver 40** can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44** may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44** may also include transistors T11-T15 and capacitor C_Q2. Capacitor C_Q2 may be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive low voltage VGL. Transistor T12 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive low voltage VGL. Transistors T13 may have a drain terminal coupled to low voltage VGL, a gate terminal coupled to node Q1 in the shift register subcircuit 42, and a source terminal coupled to node A. Transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive clock signal CLK_B, and a source terminal coupled to transistor T15. Transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register subcircuit 42, and a source terminal coupled to high power supply voltage VGH.

Output buffer subcircuit 44** may further include transistors T16-T17 and capacitors C_QB2, C₁, and C₂. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal coupled to a node B. Capacitor C1 may have a first terminal coupled to node B and a second terminal coupled to the low power supply voltage VGL. Transistor T16 may have a first source-drain terminal coupled to node B, a second source-drain terminal configured to receive shift register clock signal CLK_B, and a gate terminal. Capacitor C₂ may have a first terminal coupled to node B and a second terminal coupled to the gate terminal of transistor T16. Transistor T17 may have a gate terminal coupled to the low power supply voltage VGL, a first source-drain terminal coupled to the gate terminal of transistor T16, and a second source-drain terminal coupled to the Q0 node of another gate driver 40** from three rows below (as indicated by the “n+3” notation). Configured in this way, transistor T16 can be used to maintain the voltage at node QB2 to be lower than VGL (e.g., turning transistor T16 off can isolate capacitor C_QB2 from any noise or toggling associated with clock signal CLK_B).

The operation of gate driver 40** of FIG. 12 is substantially similar to the timing diagram already shown in FIG. 11B and need not be reiterated in detail to avoid obscuring the present embodiments. The only difference in the timing waveforms for gate driver 40** is that at the rising edge of Q0(n+3), node QB2 may rise up slightly due to the capacitive coupling through capacitors C₂ and C_QB2. A plurality of gate drivers 40** can be coupled together in a chain using an arrangement that is similar or identical to the control scheme already shown in FIG. 11C.

FIG. 13 is a circuit diagram of another implementation of a gate driver circuit such as gate driver circuit 40*** configured to receive a reset signal. As shown in FIG. 13, gate driver 40*** may include shift register subcircuit 42 and output buffer subcircuit 44***. The shift register subcircuit 42 in gate driver 40*** of FIG. 13 may have an identical structure as shift register subcircuit 42 in gate driver 40 of FIG. 5A and need not be reiterated in detail to avoid obscuring the present embodiment. As an example, all of the transistors within gate driver circuit 40*** can be implemented as silicon transistors (e.g., all of transistors within gate driver 40*** can be implemented as PMOS LTPS thin-film transistors).

Output buffer subcircuit 44*** may include transistor T8 coupled in series with transistor T9. First output buffer transistor T8 has a source terminal configured to receive output buffer clock signal CLK_BUF, a gate terminal coupled to node Q2, and a drain terminal coupled to a gate driver output port on which gate output signal GOUT is generated. Transistor T8 can be sized relatively large to help ensure that gate output signal GOUT has sufficiently short rise and fall times. Signal GOUT may, for example, represent a scan signal for controlling data loading transistor Tdata in FIG. 3 or other switching transistors within pixel 22. Second output buffer transistor T9 has a source terminal coupled to the gate driver output port, a gate terminal coupled to node QB2, and a drain terminal coupled to low power supply signal VGL.

Output buffer subcircuit 44*** may also include transistors T11-T15 and capacitor C_Q2. Capacitor C_Q2 may be coupled across the gate terminal and the drain terminal of transistor T8. Transistor T11 has a first source-drain terminal coupled to node QB2, a second source-drain terminal coupled to node QB1, and a gate terminal configured to receive low voltage VGL. Transistor T12 may have a first source-drain terminal coupled to node Q2 (i.e., the gate terminal of transistor T8), a second source-drain terminal coupled to node A, and a gate terminal configured to receive low voltage VGL. Transistors T13 may have a drain terminal coupled to low voltage VGL, a gate terminal coupled to node Q1 in the shift register subcircuit 42, and a source terminal coupled to node A. Transistor T14 may have a drain terminal coupled to node A, a gate terminal configured to receive clock signal CLK_B, and a source terminal coupled to transistor T15. Transistor T15 may have a drain terminal coupled to the source terminal of T14, a gate terminal coupled to node QB1 in the shift register subcircuit 42, and a source terminal coupled to high power supply voltage VGH.

Output buffer subcircuit 44*** may further include transistors T16-T18 and capacitors C_QB2 and C₁. Capacitor C_QB2 can have a first terminal coupled to node QB2 and a second terminal coupled to a node B. Capacitor C₁ may have a first terminal coupled to node B and a second terminal coupled to the low power supply voltage VGL. Transistor T16 may have a first source-drain terminal coupled to node B, a second source-drain terminal configured to receive shift register clock signal CLK_B, and a gate terminal coupled to the Q0 node of another gate driver 40*** from three rows below (as indicated by the “n+3” notation).

Transistor T17 may have a source terminal coupled to node B, a drain terminal coupled to low power supply voltage VGL, and a gate terminal configured to receive a reset signal. The reset signal may be a global reset signal that controls every gate driver 40*** simultaneously. Transistor T18 may have a drain terminal coupled to node QB1, a source terminal coupled to low power supply voltage VGL, and a gate terminal configured to receive the reset signal. Configured in this way, transistors T16, T17, and T18 can be used to stabilize the gate driver a low refresh rates (e.g., when the display is operation at refresh rates of less than 30 Hz, less than 10 Hz, less than 5 Hz, 2 Hz or less, 1 Hz or less, etc.). For example, use of transistors T16 and T17 can help minimize the impact of leakage from CLK_B to node B, whereas the use of transistor T18 can help minimize the impact of leakage from CLK_A to node QB1 through transistor T4. The global reset signal can be asserted during a vertical blanking period to turn on transistors T17 and T18. Transistors T17 and T18 may remain off during normal display refresh operations.

The operation of gate driver 40*** of FIG. 13 is substantially similar to the timing diagram already shown in FIG. 11B and need not be reiterated in detail to avoid obscuring the present embodiments. A plurality of gate drivers 40*** can be coupled together in a chain using an arrangement that is similar or identical to the control scheme already shown in FIG. 11C.

The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Claims

1. A display gate driver circuit comprising: a first p-type output buffer transistor having a source-drain terminal coupled to an output terminal, the output terminal being coupled to a plurality of display pixels via a gate line;a first capacitor coupled between the source-drain terminal and a gate terminal of the first p-type output buffer transistor;a second p-type output buffer transistor coupled in series with the first p-type output buffer transistor; anda second capacitor coupled between a gate terminal of the second p-type output buffer transistor and a power supply line.

2. The display gate driver circuit of claim 1, further comprising: a first additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal;a second additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first p-type output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node;a third additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node;a fourth additional p-type transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal;a fifth additional p-type transistor having a source-drain terminal coupled to the node and having a gate terminal configured to receive a second clock signal different than the first clock signal; anda sixth additional p-type transistor having a first source-drain terminal coupled to the fifth additional p-type transistor, a second source-drain terminal coupled to the power supply line, and a gate terminal directly coupled to the second capacitor.

3. The display gate driver circuit of claim 1, further comprising: a first additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal;a second additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first p-type output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node;a third additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node;a fourth additional p-type transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal; anda fifth additional p-type transistor having a source-drain terminal coupled to the node and having a gate terminal configured to receive a second clock signal different than the first clock signal.

4. The display gate driver circuit of claim 1, further comprising: a first additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal;a second additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first p-type output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node;a third additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node; anda fourth additional p-type transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal.

5. The display gate driver circuit of claim 1, further comprising: a first additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal;a second additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first p-type output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node; anda third additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node.

6. The display gate driver circuit of claim 1, further comprising: a first additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal; anda second additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first p-type output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node.

7. The display gate driver circuit of claim 1, further comprising: an additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a clock signal.

8. The display gate driver circuit of claim 1, further comprising: a first additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first p-type output buffer transistor, a gate terminal coupled to an additional power supply line different than the power supply line, and a second source-drain terminal coupled to a node.

9. The display gate driver circuit of claim 8, further comprising: a second additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive a first clock signal, and a gate terminal coupled to the node.

10. The display gate driver circuit of claim 9, further comprising: a third additional p-type transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal.

11. The display gate driver circuit of claim 10, further comprising: a fourth additional p-type transistor having a source-drain terminal coupled to the node and having a gate terminal configured to receive a second clock signal different than the first clock signal.

12. The display gate driver circuit of claim 11, further comprising: a fifth additional p-type transistor having a first source-drain terminal coupled to the fourth additional p-type transistor, a second source-drain terminal coupled to the power supply line, and a gate terminal directly coupled to the second capacitor.

13. A display gate driver circuit comprising: a first output buffer transistor having a source-drain terminal coupled to an output terminal, the output terminal being coupled to a plurality of display pixels via a gate line;a first capacitor coupled between the source-drain terminal and a gate terminal of the first output buffer transistor;a second output buffer transistor coupled in series with the first output buffer transistor; anda second capacitor coupled between a gate terminal of the second output buffer transistor and a power supply line.

14. The display gate driver circuit of claim 13, further comprising: a first additional transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal;a second additional transistor having a first source-drain terminal coupled to the gate terminal of the first output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node;a third additional transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node;a fourth additional transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal;a fifth additional transistor having a source-drain terminal coupled to the node and having a gate terminal configured to receive a second clock signal different than the first clock signal; anda sixth additional transistor having a first source-drain terminal coupled to the fifth additional transistor, a second source-drain terminal coupled to the power supply line, and a gate terminal directly coupled to the second capacitor.

15. The display gate driver circuit of claim 13, further comprising: a first additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal; anda second additional p-type transistor having a first source-drain terminal coupled to the gate terminal of the first output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node.

16. The display gate driver circuit of claim 15, further comprising: a third additional p-type transistor having a first source-drain terminal directly coupled to the second capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node.

17. The display gate driver circuit of claim 16, further comprising: a fourth additional p-type transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal.

18. The display gate driver circuit of claim 17, further comprising: a fifth additional p-type transistor having a source-drain terminal coupled to the node and having a gate terminal configured to receive a second clock signal different than the first clock signal.

19. The display gate driver circuit of claim 18, further comprising: a sixth additional p-type transistor having a first source-drain terminal coupled to the fifth additional p-type transistor, a second source-drain terminal coupled to the power supply line, and a gate terminal directly coupled to the second capacitor.

20. A driver circuit comprising: a first p-type output buffer transistor having a source-drain terminal coupled to an output terminal;a second p-type output buffer transistor coupled in series with the first p-type output buffer transistor;a capacitor coupled between a gate terminal of the second p-type output buffer transistor and a power supply line;a first additional p-type transistor having a first source-drain terminal directly coupled to the capacitor, a second source-drain terminal coupled to an additional power supply line different than the power supply line, and a gate terminal configured to receive a first clock signal;a second additional p-type transistor having a first source-drain terminal coupled to a gate terminal of the first p-type output buffer transistor, a gate terminal coupled to the additional power supply line, and a second source-drain terminal coupled to a node;a third additional p-type transistor having a first source-drain terminal directly coupled to the capacitor, a second source-drain terminal configured to receive the first clock signal, and a gate terminal coupled to the node;a fourth additional p-type transistor having a first source-drain terminal coupled to the node, a second source-drain terminal configured to receive a carry in signal, and a gate terminal configured to receive the first clock signal;a fifth additional p-type transistor having a source-drain terminal coupled to the node and having a gate terminal configured to receive a second clock signal different than the first clock signal; anda sixth additional p-type transistor having a first source-drain terminal coupled to the fifth additional p-type transistor, a second source-drain terminal coupled to the power supply line, and a gate terminal directly coupled to the capacitor.