Patent Application
20110304595
The invention relates to displays, particularly the showing of different dimension images on pixelated displays such as liquid crystal on silicon displays.
Displays are sometimes required to work at a variety of resolutions. When the display has a variable raster (as a CRT has), this can be achieved by resynchronization, but when the display has a fixed arrays of pixels (e.g. an LCOS display) other techniques must be used.
One such technique is re-sizing. A new set of pixels appropriate for the new display is generated from the original set of pixels. There are many silicon solutions to accomplish this, but resizing often causes sampling artefacts, e.g. “jaggies” on text and diagrams, and also often distorts the image's aspect ratio.
The present invention provides a windowing method having a good bandwidth efficiency. According to the present invention there is provided a control means for a pixel display, for displaying pixel images provided as rows of data to a row driver, wherein there is included a shift register for transposing each row of data so that it is written to the row driver in a manner that causes each pixel of the row of data to be translated by a number of pixels distance across the screen, and there is included a fill data means for writing a blank signal to the pixels which the row of data would be written too had it not been translated.
If complications due to resynchronization or re-sizing are unacceptable for a given application, then an approach is ‘windowing’. In this approach, the display has sufficient x- and y-resolution to contain every supported format, the original set of pixels is used and each format is shown undistorted on a portion of the display large enough to contain it. Unused portions of the display are referred to as margins, and are typically set to black.
Referring to
The display may also have a border 12 of e.g. 32 pixels round all four sides. These pixels, if present, cannot receive image data and are architecturally designed to be driven black at all times.
When HDTV format is selected, the unused rows above and below the image are called the top and bottom margins. When monitor format is selected, the unused areas to the left and right of the image are called the side margins.
The display is natively binary. Greyscales are rendered using binary weighted bitplanes. Colour is rendered by a colour sequential technique. Data is loaded row by row, though in other displays, the x- and y- axes could be reversed, without affecting the principle.
Bitplane data is clocked into the display over a 64 bit bus, and each clock cycle on the bus allows a word containing 64 pixels to be loaded (the use of a Double Data Rate (DDR) interface would alter the arithmetic, but the same principles would still apply). To load a complete row (1920 pixels) on the display, 30 such words are required for the pixel data, plus one control word (containing row addresses and other control signals for the display control circuitry), making a total of 31 clock cycles per row.
As shown in
To load an entire bitplane, 1200 rows are transmitted, requiring a total of 31×1200=37200 clock cycles. The number of clock cycles needed is significant because it determines the amount of bandwidth which will be required to support any given combination of bit depth and refresh rate. The bandwidth requirement, in turn, affects the cost of the display and its associated drive electronics.
In HDTV format, only 1080 rows of image data need to be transmitted for each bitplane, requiring 31×1080=33480 clock cycles—a saving of 10%. This is slightly offset by a requirement to initialize the 120 margin rows, but this can be done just once per frame instead of for every bitplane, so when large numbers of bitplanes are used per frame the saving approaches 10%.
Monitor format has an area about 16.7% smaller than the full display, due to the 160-pixel margin on each side of the active image, so ideally a bandwidth saving around 16.7% might be achievable.
The display drive electronics captures the 1600×1200 video signal and centres it in a 1920×1200 framestore, padding the side margins with data to produce an optical black state. Given the addressing method described above, each row must be transmitted completely before the next can begin. This means that 31 words are still needed for each row. Since Monitor Format has no fewer lines than the entire display, when simply addressing the display in this manner, the number of cycles per bitplane is unchanged at 37200.
A new shift register is provided with what will be referred to as ‘wide mode’ and ‘narrow mode’. In wide mode, it operates just as before. In narrow mode, the shift register operates as if it were only 1600 bits wide, and its output is offset by 160 columns so that the image is correctly centred.
The remaining columns are filled with ‘fill data’, which is not transmitted from the drive electronics, but is generated inside the display control circuitry. The fill data would consist either of all zeroes or all ones, whichever corresponds to an optical black state.
In narrow mode, the shift register needs only 25 words of pixel data, plus one control word, making 26 words per row. The saving is 16.1% compared with the ideal of 16.7%.
Other formats can be split into two classes:
Formats up to 1600 pixels wide which don't use the full height of the display can benefit from both bandwidth-saving techniques described above.
Although this display system has a shift register with two hard-wired width modes, in principle, three or more hard-wired width modes could also be implemented, but these are not described here.
Alternatively, a general mechanism could be used to support any number of data words from 1 to 30 (or however many data words are needed for full width), which will be described later.
Referring now to
The two-mode centering shifter 24 contains twelve data switches 40, each of which selects one of two 160-bit input busses and routes it to its single 160-bit output bus, as shown in
When narrow mode is switched off, the ‘narrow’ input line, which controls each of the switches 40, is 0. Each switch selects the bus at its ‘0’ input for routing the input 42 to its output 44. In this way, every one of the 1920 bits coming in from the de-multiplexer 22 is routed to the same line in the output to the column driver 24.
When narrow mode is switched on, the ‘narrow’ input line is 1, and each switch selects the bus at its ‘1’ input for routing to its output. Each bit of the first 1600 bits in the input is shifted to the right by 160 places. The first 160 and last 160 bits in the output are generated from fill data (fd).
Referring to
Referring to
Shift256 outputs to Bus C, which is read by shift registers Shift128 which outputs to Bus D, which is read by shift registers Shift64 which outputs to Bus E, which is read by shift registers Shift32 which outputs to Bus F.
The five shift enable lines together allow the image to shifted right by any multiple of 32 bits, from 0×32 to 32×32, but in practice the highest value needed is 29×32. The values used for each width of input (as multiples of 32 bits) are shown in Table 1.
An important feature of this shifter design is that the latency is short and constant—it does not depend upon the amount of shifting which is required. The five shift units (Shift512 to Shift32) ensure by their design that the left margin will be correctly padded with fill data, but the same cannot be said of the right margin. For this reason, a separate right fill unit is incorporated as the final stage in the pipeline.
The right fill unit, shown in
Each Right Fill means rf4 are interposed between Bus F and Bus G, each the Right Fill means rf4 either copying the data from Bus F to Bus G or producing a signal for the right margin on Bus G, depending on the Fill Enable fe0 to fe28 signals determined by the data in Table 2 which control the Right Fill means rf4. More specifically, referring to
This five-shifter architecture would be suitable, with minor modifications, for any display width up to 2048 pixels. The addition of a sixth shifter would support displays up to 4096 pixels wide, and each additional shifter thereafter would further double the maximum image width. Although the example structure has assumed a 64-bit input bus, it is easily adapted to other input bus widths.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0823222.5 | Dec 2008 | GB | national |
This Application is a Continuation of International Application No. PCT/GB2009/051754, filed 21 Dec. 2009, which claims the benefit of GB0823222.5 filed Dec. 19, 2008, the entirety of each of which are hereby incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/GB2009/051754 | Dec 2009 | US |
| Child | 13163155 | US |
