Patent Application
20090184983
This patent application claims priority on convention based on Japanese Patent Application No. 2008-011418. The disclosure thereof is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display apparatus, a display panel driver and a display panel driving method, and more particularly relates to a driving technique of a display panel to execute a color reducing process and an enlarging process to image data at a same time.
2. Description of Related Art
One of requests to an LCD panel (liquid crystal display panel) installed in a portable terminal is in increase in the number of colors to be displayed. In order to satisfy this request, the LCD driver for driving the LCD panel is needed to deal with a multiple gradation display. One problem lies in increase in a chip size, when the number of the displayable gradations of the LCD driver is increased. In order to increase the number of the displayable gradations, a D/A converter used to drive signal lines is needed to deal with a large number of gradations, and this causes the increase in the chip size.
One scheme for suppressing the increase in the chip size that results from the increase in the number of the gradations lies in that the LCD driver includes a color reducing circuit, and a pseudo gradation display is performed to substantially attain the multiple gradation display. For example, Japanese Patent No. 3,735,529 and Japanese Patent Application Publication (JP-A-Heisei, 9-90902) disclose a technique that a color reducing process is executed through error diffusion and further attains the pseudo gradation display by using FRC (frame rate control).
Another request to the LCD panel installed in the portable terminal lies in increase in the number of pixels. In recent years, the LCD panel is used that has the number of pixels more than the number of pixels defined by VGA (video graphic array). However, the increase in the number of pixels increases a data transfer amount to the LCD driver from an image processing unit such as CPU or DSP (digital signal processor), and consequently increases consumption of electric power and EMI (electromagnetic interference) of the LCD driver.
The inventor considers one scheme to solve the above problems of the increases in the electric power consumption and EMI that result from the increase in the number of pixels, in which the size of an image is selected on the basis of a kind of the image to be displayed (for example, VGA, QVCA (quarter VGA) and the like) and also an enlarging process, namely, a function of enlarging the image is given to the LCD driver. For example, it is assumed that the LCD panel has the number of pixels corresponding to VGA. In displaying the image for which a high quality display is requested such as a photograph, the image data of VGA is sent to the LCD driver, and the image is displayed at a same magnification. On the other hand, in displaying the image in which a relatively low resolution is allowable such as the display screen of a game or mail, the enlarging process is executed such that the image data of QVGA is sent to the LCD driver and then the image is enlarged to twice in both of a horizontal direction and a vertical direction by the LCD driver. The enlargement of the image in the horizontal direction is attained by driving the two pixels arrayed in the horizontal direction in accordance with the same image data, as the easiest manner. The enlargement of the image in the vertical direction is attained by driving the adjacent two scan lines sequentially (or at the same time), in the state that the signal line is driven to a desirable drive voltage. Since such a scheme is used to perform the image display, it is possible to decrease the data transfer amount to the LCD driver and decrease consumption of electric power and EMI.
In order to attain the correspondence to the multiple gradation display and the reduction in the consumption of electric power and the EMI at the same time, the color reducing process and the enlarging process are desired to be used at the same time. However, according to the consideration of the inventor, when the color reducing process and the enlarging process are simply combined, there is a possibility of deterioration of the image such as generation of flicker. For example,
At first, it is assumed that the image data of VGA is supplied in which the gradation values of all of pixels of the image data are 18. In this case, as shown in
On the other hand, it is assumed that the image data of QVGA is supplied in which the gradation values of all the pixels of the image data are 18. After the color reducing process is executed on the image data of QVGA, when the enlarging process to double in the column and row directions is executed, a matrix of 2×2 pixels in which the gradation value is 20 and a matrix of 2×2 pixels in which the gradation value is 20 are arranged on the LCD panel in a checker-wise pattern, as shown in
It is an object of the present invention to provide a driving technique that deterioration of an image can be prevented, even if a color reducing process and an enlarging process of the image are combined.
In an aspect of the present invention, a display apparatus includes: a display panel; and a display panel driver configured to drive signal lines of the display panel. The display panel driver includes: a color reducing circuit configured to be possible to generate a first color reduction image data from a first input image data by executing an error diffusion process by using a first error value, and to generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value which is different from the first error value; and a driving section configured to drive a first pixel positioned on a horizontal line of the display panel in response to the first color reduction image data, and drive a second pixel positioned on the horizontal line and adjacent to a the first pixel in a horizontal direction, in response to the second color reduction image data.
In another aspect of the present invention, a display panel driver which drives signal lines of a display panel, includes: a color reducing circuit configured to generate a first color reduction image data from a first input image data by executing an error diffusion process by using a first error value, and generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value different from the first error value; and a driving section configured to drive a first pixel positioned on a horizontal line of the display panel in response to the first color reduction image data, and drive a second pixel positioned on the horizontal line and adjacent to the first pixel in a horizontal direction in response to the second color reduction image data.
In still another aspect of the present invention, a color reducing circuit includes: a first circuit section configured to generate a first color reduction image data and a second error value from a first input image data by executing an error diffusion process by using a first error value; and a second circuit section configured to generate a second color reduction image data from the first input image data by executing the error diffusion process by using a second error value.
In another aspect of the present invention, a display panel driving method is achieved: by driving a first pixel and a second pixel positioned on a first line in response to a first input image data when the first input image data is supplied as image data of a first format; and by driving the first pixel in response to a second input image data and the second pixel in response to a third input image data, when the second and third input image data are supplied as image data of a second format which is different from the first format. The driving a first pixel and a second pixel is achieved: by generating a first color reduction image data by executing an error diffusion process to the first input image data by using a first error value; by generating a second color reduction image data by executing the error diffusion process to the first input image data by using a second error value different from the first error value; by driving the first pixel in response to the first color reduction image data; and by driving the second pixel in response to the second color reduction image data. The driving the first pixel is achieved: by generating a third color reduction image data by executing the error diffusion process to the second input image data; by generating a fourth color reduction image data by executing the error diffusion process to the third input image data; by driving the first pixel in response to the third color reduction image data; and by driving the second pixel in response to the fourth color reduction image data.
According to the present invention, it is possible to provide the driving technique that deterioration of an image can be prevented, even if a color reducing process and an enlarging process of the image are combined.
The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain embodiments taken in conjunction with the accompanying drawings, in which:
Hereinafter, a liquid crystal display apparatus of the present invention will be described in detail with reference to the attached drawings.
On the LCD panel 2, pixels of m rows and n columns are arrayed in a matrix. The pixels arranged on one row in a horizontal direction of the LCD panel 2 are referred to as the pixels for one horizontal line. Each of the pixels includes three sub pixels arrayed in the horizontal direction. One of the three sub pixels is an R sub pixel for displaying a red (R) color, and another is a G sub pixel for displaying a green (G) color, and the other one is a B sub pixel for displaying a blue (B) color. A thin film transistor (TFT) and a pixel electrode are provided for each sub pixel. In order to drive the pixels of m rows and n columns, m scan lines (gate lines) extending in the horizontal direction and 3n signal lines (data lines) extending in the vertical direction are laid on the LCD panel 2, and the pixels are arranged at the intersections of the m scan lines and the n signal lines.
In detail, the LCD driver 3 has a function of receiving an input image data Din from outside, specifically, from an image drawing circuit 4 and driving the signal lines of the LCD panel 2 in response to the input image data Din. As the image drawing circuit 4, a CPU and a DSP (Digital Signal Processor) are exemplified. In this embodiment, the input image data Din is a 24-bit data in which the gradation of each of the three sub pixels in each pixel is represented by 8 bits. In the following description, of the input image data Din, an 8-bit data for representing the gradation of the R sub pixel is noted as an R image data DinR, an 8-bit data for representing the gradation of the G sub pixel is noted as a G image data DinG, and an 8-bit data for representing the gradation of the B sub pixel is noted as a B image data DinB. In addition, the LCD driver 3 also has a function of sequentially driving the m scan lines of the LCD panel 2. A sync signal 5, a dot clock signal DCK and other control signals are supplied to the LCD driver 3 from the image drawing circuit 4. The LCD driver 3 operates in response to each of the supplied control signals. The sync signal 5 supplied to the LCD driver 3 includes a vertical sync signal Vsync and a horizontal sync signal Hsync.
As detailed below, the LCD driver 3 performs different operations in accordance with the format of the image data Di. When the image data Di is supplied in the format of VGA, the LCD driver 3 executes a color reducing process to the image data Din to generate a color reduction image data, and drives the LCD panel 2 to display an image in its original size in response to the color reduction image data. On the other hand, when the image data Din is supplied in the format of QVGA, the LCD driver 3 executes the color reducing process to the image data Di, and executes an enlarging process to a quadruple size in response to the image data after the color reducing process. However, in the liquid crystal display apparatus 1 in this embodiment, when the image data Din is supplied in the format of QVGA, the special color reducing process and enlarging process are executed to suppress deterioration of the image effectively.
The configuration of the LCD driver 3 will be described below. The LCD driver 3 includes a control circuit 11, a color reducing circuit 12, a shift register circuit 13, a data register circuit 14, a latch circuit 15, a data switching circuit 16, a signal line driving circuit 17, a gradation voltage generating circuit 18, a scan line driving circuit 19 and a timing control circuit 20. In this embodiment, those circuits are monolithically integrated on one semiconductor chip. However, a part or all of the circuits may be integrated on different semiconductor chips or the LCD panel 2. For example, the scan line driving circuit 19 may be integrated as a different semiconductor chip or may be integrated on the LCD panel 2. Also, the LCD driver 3 may be integrated onto the LCD panel 2 by using an SOG (semiconductor on glass) technique.
The control circuit 11 has the following three functions. Firstly, the control circuit 11 has the function of transferring the image data Din sent from the image drawing circuit 4 to the color reducing circuit 12. Secondly, the control circuit 11 has the function of generating a timing signal 22 in response to the sync signal 5 and the dot clock signal DCK and supplying to the timing control circuit 20. Thirdly, the control circuit 11 has the function of determining whether the image data Din is sent in the format of VGA or in the format of QVGA, in each frame period, and then generating an enlarging process signal 23 in accordance with the determination result. In this embodiment, the control circuit 11 negates the enlarging process signal 23 (namely, sets the enlarging process signal 23 to “0” when the image data Din is sent in the format of VGA, and asserts the enlarging process signal 23 (namely, sets the enlarging process signal 23 to “1”) when it is sent in the format of QVGA.
The color reducing circuit 12 is a circuit for executing the color reducing process to the image data Din by using error diffusion. The color reducing circuit 12 has the function of executing the color reducing process on the image data Din corresponding to one pixel in one clock period of the dot clock signal DCK. When the image data Din of the respective pixels are sequentially inputted, the color reducing circuit 12 sequentially executes the color reducing process on the input image data Din. The color reducing circuit 12 in this embodiment has the function of separately preparing two error values from the same image data Din and using these two error values to generate color reduction image data Dfrc1 and Dfrc2 of two kinds, respectively. Here, each of the color reduction image data Dfrc1 and Dfrc2 is the 18-bit data in which of each of the three sub pixels of each pixel is represented with 6 bits.
However, attention should be paid to the fact that the color reducing circuit 12 does not always generate the color reduction image data Dfrc1 and Dfrc2 of the two kinds from the image data Din. When the enlarging process signal 23 is negated (namely, when the image data Di is sent in the format of VGA), the color reducing circuit 12 executes an error diffusing process on the image data Di to generate the color reduction image data Dfrc1. On the other hand, when the enlarging process signal 23 is asserted (namely, when the image data Di is sent in the format of QVGA), the color reducing circuit 12 generates the two color reduction image data Dfrc1 and Dfrc2 by using the separately-prepared error values. The configuration of the color reducing circuit 12 will be described later in detail.
The shift register circuit 13, the data register circuit 14, the latch circuit 15, the data switching circuit 16 and the signal line driving circuit 17 are a circuit group which functions as a driving section for driving the signal lines of the LCD panel 2 in response to the color reduction image data Dfrc1 and Dfrc2. In detail, the data register circuit 14 sequentially receives and holds the color reduction image data Dfrc1 and Dfrc2 from the color reducing circuit 12 under the control of the shift register circuit 13. In detail, as shown in
The latch circuit 15 latches the color reduction image data from the data register circuit 14 in response to a latch signal 25 sent from the timing control circuit 20. As shown in
The data switching circuit 16 transfers the color reduction image data outputted from the latch circuit 15 to the signal line driving circuit 17 in the original state or in a changed spatial order in response to a switching signal 26 sent from the timing control circuit 20. In detail, the data switching circuit 16 includes straight switches 33-1 to 33-n and cross switches 34-1 to 34-n, as shown in
The signal line driving circuit 17 drives the signal lines in the LCD panel 2 in response to the color reduction image data for one horizontal line sent from the latch circuit 15. Specifically, the signal line driving circuit 17 selects a gradation voltage corresponding to the gradation indicated by the color reduction image data, from a plurality of gradation voltages supplied from the gradation voltage generating circuit 18, and drives the corresponding signal line of the LCD panel 2 to the selected gradation voltage. In this embodiment, the number of gradation voltages supplied from the gradation voltage generating circuit 18 is 64 (=26). It should be noted that since the color reduction image data supplied to the signal line driving circuit 17 is the data indicating the gradations of the three sub pixels of one pixel, the three signal lines are driven in response to one color reduction image data. That is, in the signal line driving circuit 17, the three outputs are prepared for one input, and the three outputs are connected to the three signal lines. In
Referring to
The timing control circuit 20 has a role for performing the timing control of the entire LCD driver 3. In detail, the timing control circuit 20 generates the horizontal start signal 24, the latch signal 25, the switching signal 26, the output enable signal 27 and the scan line control signal 28, and supplies to the shift register circuit 13, the latch circuit 15, the data switching circuit 16, the signal line driving circuit 17 and the scan line driving circuit 19, respectively. The timing control of the LCD driver 3 is performed by the horizontal start signal 24, the latch signal 25, the switching signal 26, the output enable signal 27 and the scan line control signal 28.
The configuration of the color reducing circuit 12 will be described below in detail.
Each of the R error diffusing circuit 40R, the G error diffusing circuit 40G and the B error diffusing circuit 40B includes adding circuits 41 to 44, selectors 45 and 46, a D latch 47, an initial value setting circuit 48 and a switch 49.
The adding circuits 41 and 42 are a circuit portion for calculating the color reduction image data Dfrc1k and an error value DerrN1 from the image data Dink and an error value DerrC outputted from the selector 46. Here, the error value DerrC is an error value used to generate the color reduction image data Dfrc1k of a target sub pixel. In detail, the adding circuit 42 adds the lower 2 bits of the image data Dink and the error value DerrC, outputs an error value DerrN1 from a data output c+d and outputs a 1-bit carry from a carry output cry. The adding circuit 41 adds the higher 6 bits of the image data Dink and the carry received from the adding circuit 42 and generates the color reduction image data Dfrc1k.
The adding circuits 43 and 44 are a circuit portion for calculating the color reduction image data Dfrc2k and an error value DerrN2 from the image data Dink and the error value DerrN1 outputted by the adding circuit 42. In detail, the adding circuit 44 adds the lower 2 bits of the image data Dink and the error value DerrN1, outputs an error value Derr from the data output c+d and outputs a 1-bit carry from the carry output cry. The adding circuit 43 adds the higher 6 bits of the image data Dink and the carry received from the adding circuit 44 and generates the color reduction image data Dfrc2k.
In summary, the adding circuits 41 to 44 calculate the color reduction image data Dfrc1k and Dfrc2k and the error values DerrN1 and DerrN2 from the image data Dink and the error value DerrC, by using the following equations:
Dfrc1k=(Dink[7:2]+(Dink[1:0]+DerrC)>>2,
Derr
N1=(Dink[1:0]+DerrC)%4
Dfrc2k=(Dink[7:2]+(Dink[1:0]+DerrN1))>>2,
Derr
N2=(Dink[1:0]+DerrN1)%4
Here, Dink[1:0] is the lower 2 bits of the image data Dink, and Dink[7:2] is the higher 6 bits of the image data Dink. Also, “>>2” is a process of truncating the lower 2 bits (namely, in this case, the process that leaves only a carry when the carry is generated), and “%4” is a process of calculating a remainder when it is divided by 4 (namely, in this case, the process that truncates a carry when the carry is generated).
Also, the following process is executed on the color reduction image data Dfrc1k and Dfrc2k (although this is not illustrated in
When Dfrc1k≧63, Dfrc1k=63
When Dfrc2k≧63, Dfrc2k=63
The selector 45 selects one of the error values DerrN1 and DerrN2 in response to the enlarging process signal 23, and supplies the selected error value to the D latch 47. When the enlarging process signal 23 is negated (namely, when the image data Din is sent in the format of VGA), the selector 45 selects the error value DerrN1. On the other hand, when the enlarging process signal 23 is asserted (namely, when the image data Din is sent in the format of QVGA), the selector 45 selects the error value DerrN2.
The D latch 47 latches the error value selected by the selector 45 in synchronization with the dot clock signal DCK.
The selector 46 selects one of the error value outputted from the D latch 47 and an initial value DerrINI generated by the initial value setting circuit 48, as the error value DerrC in response to an error initial value read signal DE_POS. In driving the leftmost pixel on each horizontal line, the error initial value read signal DE_POS is asserted, and the initial value DerrINI is selected as the error value DerrC. On the other hand, in driving the other pixels, the error initial value read signal DE_POS is negated, and the error value outputted from the D latch 47 is selected as the error value DerrC.
The initial value setting circuit 48 is a circuit for giving the initial value DerrINI of an error used in the error diffusing process. A frame count indicating the number of a frame targeted for the color reducing process and a line count indicating the number of the targeted line are given to the initial value setting circuit 48. The initial value setting circuit 48 generates the initial value DerrINI that is different, depending on the frame and the line.
The switch 49 controls the supply of the image data Dink to the adding circuits 43 and 44 on the basis of the enlarging process signal 23. When the enlarging process signal 23 is negated (namely, when the image data Din is sent in the format of VGA), the switch 49 is turned off, and the supply of the image data Dink to the adding circuits 43 and 44 is stopped. On the other hand, when the enlarging process signal 23 is asserted (namely, when the image data Din is sent in the format of QVGA), the switch 49 is turned on, and the image data Dink is supplied to the adding circuits 43 and 44.
In the R error diffusing circuit 40R, G error diffusing circuit 40G and B error diffusing circuit 40B thus configured, the different operations are performed, depending on the state of the enlarging process signal 23. When the enlarging process signal 23 is negated, the switch 49 is turned off. Moreover, the selector 45 selects the error value DerrN1. In this case, the R error diffusing circuit 40R, the G error diffusing circuit 40G and the B error diffusing circuit 40B operate similarly to the typical color reducing circuit to generate the color reduction image data Dfrc1k from the image data Dink and the error value DerrC. As the error value latched by the D latch 47 (namely, the error value used to drive a next pixel), the error value DerrN1 is selected. The color reduction image data Dfrc2k is not generated. On the other hand, when the enlarging process signal 23 is asserted, the switch 49 is turned on. Moreover, the selector 45 selects the error value DerrN2. In this case, the R error diffusing circuit 40R, the G error diffusing circuit 40G and the B error diffusing circuit 40B generate the color reduction image data Dfrc1k by using the error value DerrC from the image data Dink, and generate the color reduction image data Dfrc2k by using the error value DerrN1. As the error value latched by the D latch 47 (namely, the error value used to drive the next pixel), the error value DerrN2 is selected.
It should be noted that since the error value DerrN1 generated by the adding circuit 42 is used for generation of the color reduction image data Dfrc2k by the adding circuits 43 and 44, this contributes to reduction in circuit scale. Unless the reduction in hardware is considered, the D-latch and the initial value setting circuit that are dedicated to the adding circuits 43 and 44 may be employed, separately from the D latch 47 and the initial value setting circuit 48. However, the initial value setting circuit especially requires the large circuit scale. Thus, although such configuration is possible, this is not preferable. As described in this embodiment, since the error value DerrN1 is used for generation of the color reduction image data Dfrc2k by the adding circuits 43 and 44, the single initial value setting circuit can be used to generate the two error values, and the two color reduction image data can be generated from the two error values.
The operation of the liquid crystal display apparatus will be described below in detail.
The control circuit 11 determines in beginning of each frame period, whether the image data Din is sent in the format of VGA or sent in the format of QVGA in the frame period.
With reference
The operation of the LCD driver 3 is different, depending on the state of the enlarging process signal 23, namely, between a case where the image data Din is sent in the format of VGA and a case where it is sent in the format of QVGA. When the image data Din is sent in the format of VGA, the color reducing circuit 12 generates the color reduction image data Dfrc1 from the image data Din (similarly to the typical color reducing circuit). On the other hand, the LCD driver 3 operates to drive the LCD panel 2 so that the sent image is displayed as a whole in its original size.
The LCD panel 2 is driven in response to the color reduction image data Dfrc1.
In detail, when the blanking period of the (j−1)th horizontal period is completed and the horizontal start signal 24 is asserted, the shift register circuit 13 sequentially asserts the shift register output signals SR1 to SRn. In response to the assertion of the shift register output signals SR1 to SRn, the registers 31-1 to 31-n of the data register circuit 14 sequentially latch and hold the color reduction image data Dfrc1. In
In succession, when the jth horizontal period is started, the latch signal 25 is asserted in the blanking period of the jth horizontal period. Consequently, the color reduction image data Dfrc1 used to drive the pixels in the jth horizontal period are latched by the latches 32-1 to 32-n of the latch circuit 15. At this time, since the switching signal 26 is negated, as shown in
According to such a driving procedure, in response to the color reduction image data Dfrc1 generated from the image data Din, the LCD panel 2 is driven such that the sent image is displayed in its original state.
On the other hand, when the image data Din is sent in the format of QVGA, the color reducing circuit 12 generates the color reduction image data Dfrc1 and Dfrc2 from the image data Din. On the other hand, the LCD driver 3 is operated to drive the LCD panel 2 so that the quadruple image which is double in each of the column and row directions, is displayed.
The LCD panel 2 is driven in response to the color reduction image data Dfrc1 and Dfrc2 such that the image size is made quadruple (double in each of column and row directions).
In detail, the color reduction image data Dfrc1 is stored in the odd-numbered register 31-(2k-1) in the data register circuit 14, and the color reduction image data Dfrc2 is stored in the even numbered register 31-(2k) in the data register circuit 14. It should be noted that the two registers 31 latch the color reduction image data Dfrc1 and Dfrc2 at the same time. As shown in
The color reduction image data Dfrc1 and Dfrc2 are generated from the same image data Din. Thus, by the above-mentioned operations, the image is made doubled in the row direction. However, the laterally adjacent pixels are driven in accordance with the color reduction image data generated by using the differently prepared error value. Therefore, the spatial frequency of the brightness change is not decreased.
In succession, when the jth horizontal period is started, the latch signal 25 is asserted in the blanking period of the jth horizontal period. Thus, the color reduction image data Dfrc1 used to drive the pixels in the jth horizontal period are latched by the odd-numbered latch 32-(2k-1) in the latch circuit 15, and the color reduction image data Dfrc2 is latched by the even numbered latch 32-(2k).
When the image data Din is sent in the format of QVGA, the pixels on the different horizontal lines are driven between the front and back halves of the jth horizontal period. Thus, the LCD panel 2 is driven such that the image is made double in the column direction. That is, the pixels on the (2j-1)th horizontal line on the LCD panel 2 are driven in the front half of the jth horizontal period, and the pixels on the (2j)th horizontal line are driven in the front half of the jth horizontal period. Here, the state of the data switching circuit 16 is switched between the front and back halves of the jth horizontal period. Thus, the adjacent pixels in the column direction are driven in accordance with the different color reduction image data generated by using the different error value.
In detail, the switching signal 26 is negated in the front half of the jth horizontal period, and as shown in
On the other hand, the switching signal 26 is asserted in the back half of the jth horizontal period, and as shown in
According to the above-mentioned operations, the adjacent pixels are driven in both of the row direction and the column direction in accordance with the different color reduction image data generated by using the separately prepared error values. For example, as shown in
Also, in the above-mentioned embodiments, the image data Din is a 24-bit data in which the gradation of each of the three sub pixels of each pixel is represented with 8 bits, and each of the color reduction image data Dfrc1 and Dfrc2 is a 18-bit data in which the gradation of each of the three sub pixels of the pixel is represented with 6 bits. However, it is evident that the number of bits of the image data Din and the color reduction image data Dfrc1 and Dfrc2 may be properly changed.
Moreover, in this embodiment, the image data Din is sent in the format of VGA or QVGA. However, the present invention can be typically applied to a case that the image of a first format and the image of a second format having a double size of the image of the first format in both of the column direction and the row direction are selectively supplied to a display panel driver.
Moreover, in the above-mentioned embodiments, a case that the present invention is applied to the driving of the LCD driver has been described. However, the present invention may be applied to the other display panels such as a plasma display panel and this may be evident for one skilled in the art.
Although the present invention has been described above in connection with several embodiments thereof, it would be apparent to those skilled in the art that those embodiments are provided solely for illustrating the present invention, and should not be relied upon to construe the appended claims in a limiting sense.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-011418 | Jan 2008 | JP | national |
