Distributed constant circuit in an amplifier

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a distributed constant circuit, a high-frequency circuit and a bias applying circuit using the same, and an impedance adjusting method.

2. Description of the Background Art

In recent years, as mobile communication has been rapidly developed, electronic waves having a great many frequencies have been required for the communication, and the frequencies of the electronic waves used in the mobile communication are shifting to a microwave band. Therefore, an amplifier used for a portable machine is constituted by a monolithic microwave integrated circuit (MMIC) and a microwave integrated circuit (MIC) modularized.

As anamplifier for amplifying a signal having a desired frequency, a bias applying circuit for applying a predetermined DC bias to the gate and the drain of a field-effect transistor (FET) is used. The bias applying circuit is constituted by a distributed constant line (hereinafter referred to as a λ/4 line) having a length which is one-fourth the wavelength of a fundamental wave, for example.

When one end of the λ/4 line is short-circuited to a ground potential in an AC manner, the other end thereof enters an open state with respect to the frequency of the fundamental wave (hereinafter referred to as a fundamental frequency). The λ/4 line is widely applied to various types of circuits such as a distributor, a synthesizer, a directional coupler, and a filter in addition to the bias applying circuit to the FET.

However, the lower the fundamental frequency is, the larger the length of the λ/4 line is, thereby increasing the size of a chip or a module at frequencies which are not more than several gigahertz. Therefore, a method of miniaturizing the λ/4 line has been examined.

FIG. 37

is a diagram showing a λ/4 line, and

FIG. 38

is a diagram showing a conventional distributed constant circuit equivalent to the λ/4 line. In

FIG. 37

, Z

0

is the characteristic impedance of a λ/4 line 100, and L

0

is the length of the λ/4 line

100

. In

FIG. 38

, Z

1

is the characteristic impedance of a line

101

, L

1

is the length of the line

101

, and C

1

is the capacitance value (capacitance) of capacitors

102

and

103

.

In the distributed constant circuit shown in

FIG. 38

, the line

101

is connected between a node NA and a node NB, the node NA is grounded through the capacitor

102

, and the node NB is grounded through the capacitor

103

.

If the characteristic impedance Z

1

, the length L

1

and the capacitance value C

1

satisfy relations expressed by the following equations (12) and (13), the distributed constant circuit shown in

FIG. 38

is equivalent to the λ/4 line

100

shown in

FIG. 37

at a fundamental frequency (see an article entitled by Tetsuo Hirota, Akira Minakawa, Masahiro Muraguchi, “Reduced-Size Branch-Line and Rat-Race Hybrids for Uniplanar MMIC's”, IEEE MTT. Vol. 38, No. 3, March 1990):

\begin{matrix} Z_{1} = \frac{Z_{0}}{\sin \frac{2 π}{λ} L_{1}} & (12) \\ C_{1} = \frac{1}{ω Z_{0}} \cos \frac{2 π}{λ} L_{1} & (13) \end{matrix}

where λ is the wavelength of a fundamental wave, and ω is the angular velocity of the fundamental wave. In the foregoing equations (12) and (13), the length L

1

of the line

101

can be arbitrarily selected, so that the length L

1

of the line

101

can be reduced.

FIG. 39

is a circuit diagram of a bias applying circuit using the distributed constant circuit shown in

FIG. 38. A

bias applying circuit

110

shown in

FIG. 39

functions as a drain bias applying circuit for applying a drain bias V

dd

to a FET

200

.

In the bias applying circuit

110

shown in

FIG. 39

, a line

101

is connected between a node NA and a node NB, and the node NA is grounded through a capacitor

111

. The drain bias V

dd

is applied to the node NA. The node NB is grounded through a capacitor

103

, and is connected to the drain of the FET

200

.

Z

1

is the characteristic impedance of the line

101

, and L

1

is the length of the line

101

. C

1

is the capacitance value of the capacitor

103

, and C

g

is the capacitance value of the capacitor

111

. Z

fr

is an impedance in a case where an input side (a terminal A) is viewed from the node NB, and Z

lo

is an impedance in a case where an output side (a terminal B) is viewed from the node NB. The impedance Z

fr

and the impedance Z

lo

are taken as 50Ω.

The capacitor

111

has a sufficiently small impedance relative to the fundamental frequency. Therefore, the node NA is short-circuited to a ground potential in an AC manner. Consequently, the node NB enters an open state with respect to the fundamental frequency. That is, the bias applying circuit

110

shown in

FIG. 39

functions as a λ/4 line with respect to the fundamental frequency. In this case, the drain bias V

dd

is applied to the node NA.

On the other hand, when the λ/4 line

100

of

FIG. 37

is used as a drain bias applying circuit to the FET, one end of the λ/4 line

100

is grounded through a capacitor, and the other end is connected to the drain of the FET. In this case, the other end of the λ/4 line

100

enters an open state with respect to the fundamental frequency, and enters a short-circuited state with respect to even-order harmonics.

It has been known that in load conditions under which a short-circuited state occurs with respect to even-order harmonics (particularly second harmonics) in a B-class operation, the power-added efficiency of an amplifier which is constituted by a FET is improved. When the A /4 line

100

is used as a bias applying circuit, therefore, the efficiency of the amplifier can be increased.

In a case of an A-class or AB-class operation of an amplifier, however, the conditions are not necessarily most suitable. In this case, it is necessary to adjust a harmonic impedance (particularly second harmonics) such that the characteristics of the amplifier are most suitable (see “A Load Pull system with Harmonic Tuning”, Microwave Journal, pp. 128-132, March 1996).

Meanwhile, when the distributed constant circuit shown in

FIG. 38

is used as a bias applying circuit for a B-class amplifier as shown in

FIG. 39

, the node NB does not enter a short-circuited state with respect to even-order harmonics. Although an amplifier can be miniaturized, therefore, high efficiency of a B-class amplifier cannot be achieved.

Further, when the distributed constant circuit is used for an A-class or AB class operation, high efficiency can not be achieved because a harmonic impedance is fixed.

In the amplifier which is constituted by the FET, the FET may, in some cases, oscillate in a high-frequency region. As measures to prevent the FET from oscillating, there is a method of significantly decreasing gain at an oscillation frequency. When the λ/4 line

100

shown in

FIG. 37

is used as a bias applying circuit, the gain of the amplifier can be decreased at even-order harmonics, while the gain thereof at the other frequencies cannot be decreased. Therefore, a bias applying method capable of decreasing gain at an arbitrary frequency is demanded.

Furthermore, in an amplifier and a mixer, spurious (a signal having an unnecessary frequency) may, in some cases, be a problem. Therefore, measures to suppress spurious signals is demanded.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a distributed constant circuit which has characteristics equivalent to a λ/4 line with respect to a fundamental wave, can be miniaturized, and can suppress an arbitrary frequency, and a high-frequency circuit using the same.

Another object of the present invention is to provide a bias applying circuit which can be miniaturized and increased in efficiency.

Still another object of the present invention is to provide an impedance adjusting method for adjusting a load impedance of a transistor in a bias applying circuit.

A further object of the present invention is to provide a distributed constant circuit which can be miniaturized and lowered in cost.

A distributed constant circuit according to the present invention comprises a first line, a first capacitor, a second line connected in series with the first capacitor, a second capacitor, and a third line connected in series with the second capacitor, one end of the first line being connected to a predetermined reference potential through a series connection between the first capacitor and the second line, and the other end of the first line being connected to the reference potential through a series connection between the second capacitor and the third line, characteristics equivalent to a line having a length which is one-fourth a wavelength corresponding to a first frequency being obtained with respect to the first frequency, and the first capacitor and the second line resonating and the second capacitor and the third line resonating with respect to a second frequency different from the first frequency.

In the distributed constant circuit, the characteristics equivalent to the line having a length which is one-fourth the wavelength corresponding to the first frequency are obtained with respect to the first frequency. When one of the one end and the other end of the first line is short-circuited to the reference potential in an AC manner, therefore, the other of the one end and the other end of the first line enters an open state with respect to the first frequency.

The first capacitor and the second line resonate and the second capacitor and the third line resonate with respect to the second frequency. Therefore, the one end and the other end of the first line are short-circuited to the reference potential with respect to the second frequency.

In this case, the parameters of the first, second and third lines and the first and second capacitors are adjusted, thereby making it possible to shorten the first, second and third lines as well as to arbitrarily set the second frequency.

Consequently, there is provided a distributed constant circuit which has characteristics equivalent to a λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

It is preferable that the characteristic impedance Z

a

of the first line, the length L

a

of the first line, the characteristic impedance Z

b

of the second and third lines, the length L

b

of the second and third lines, the capacitance value C of the first and second capacitors, a first frequency f

1

, a wavelength λ

1

corresponding to the first frequency, a second frequency f

2

, and a wavelength λ

2

corresponding to the second frequency satisfy relations expressed by equations (1), (2) and (3):

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{1}{Z_{a}} (\frac{1}{2 π f_{1} C} - Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})} & (1) \\ L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (2) \\ Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (3) \end{matrix}

In the distributed constant circuit, by satisfying the equation (3), voltage/current characteristics equivalent to the line having a length which is one-fourth the wavelength corresponding to the first frequency are obtained with respect to the first frequency.

By satisfying the equation (2), the first capacitor and the second line resonate and the second capacitor and the third line resonate with respect to the second frequency. Therefore, the one end and the other end of the first line are short-circuited to the reference potential with respect to the second frequency.

Furthermore, by satisfying the equation (1), when one of the one end and the other end of the first line is short-circuited to the reference potential in an AC manner, the other of the one end and the other end of the first line enters an open state with respect to the first frequency.

In this case, the parameters of the first, second and third lines and the first and second capacitors are adjusted, thereby making it possible to shorten the first, second and third lines as well as to arbitrarily set the second frequency.

Consequently, there is provided a distributed constant circuit which has characteristics equivalent to a λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

A distributed constant circuit according to another aspect of the present invention comprises a first line, a capacitor, and a second line connected in series with the capacitor, one end of the first line being connected to a predetermined reference potential in an AC manner, and the other end of the first line being connected to the reference potential through a series connection between the capacitor and the second line, characteristics equivalent to a line having a length which is one-fourth a wavelength corresponding to a first frequency being obtained with respect to the first frequency, and the capacitor and the second line resonating with respect to a second frequency different from the first frequency.

In the distributed constant circuit, the characteristics equivalent to the line having a length which is one-fourth the wavelength corresponding to the first frequency are obtained with respect to the first frequency. Consequently, the other end of the first line enters an open state with respect to the first frequency.

The capacitor and the second line resonate with respect to the second frequency. Therefore, the other end of the first line is short-circuited to the reference potential with respect to the second frequency.

In this case, the parameters of the first and second lines and the capacitor are adjusted, thereby making it possible to shorten the first and second lines as well as to arbitrarily set the second frequency.

Consequently, there is provided a distributed constant circuit which has characteristics equivalent to a λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

It is preferable that the characteristic impedance Z

a

of the first line, the length L

a

of the first line, the characteristic impedance Z

b

of the second line, the length L

b

of the second line, the capacitance value C of the capacitor, a first frequency f

1

, a wavelength λ

1

corresponding to the-first frequency, a second frequency f

2

, and a wavelength λ

2

corresponding to the second frequency satisfy relations expressed by equations (1), (2) and (3):

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{1}{Z_{a}} (\frac{1}{2 π f_{1} C} - Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})} & (1) \\ L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (2) \\ Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (3) \end{matrix}

In the distributed constant circuit, by satisfying the equation (3), voltage/current characteristics equivalent to the line having a length which is one-fourth the wavelength corresponding to the first frequency are obtained with respect to the first frequency.

By satisfying the equation (2), the capacitor and the second line resonate with respect to the second frequency. Therefore, the other end of the first line is short-circuited to the reference potential with respect to the second frequency.

Furthermore, by satisfying the equation (1), the other end of the first line enters an open state with respect to the first frequency.

In this case, the parameters of the first and second lines and the capacitor are adjusted, thereby making it possible to shorten the first and second lines as well as to arbitrarily set the second frequency.

Consequently, there is provided a distributed constant circuit which has characteristics equivalent to a λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

The one end of the first line may be connected to a bias voltage, and the other end of the first line may be connected to an electrode of a transistor.

The first frequency may be the frequency of a fundamental wave, and the second frequency may be higher than the frequency of second harmonics relative to the fundamental wave.

A distributed constant circuit according to still another aspect of the present invention comprises a first line, a first capacitor, a second line connected in series with the first capacitor, a first impedance element, a second capacitor, a third line connected in series with the second capacitor, and a second impedance element, one end of the first line being connected to a predetermined reference, potential through a series connection between the first capacitor and the second line and connected to the reference potential through the first impedance element, and the other end of the first line being connected to the reference potential through a series connection between the second capacitor and the third line and connected to the reference potential through the second impedance element, characteristics equivalent to a line having a length which is one-fourth a wavelength corresponding to a first frequency being obtained with respect to the first frequency, and the first capacitor and the second line resonating and the second capacitor and the third line resonating with respect to a second frequency different from the first frequency.

In the distributed constant circuit, the characteristics equivalent to the line having a length which is one-fourth the wavelength corresponding to the first frequency are obtained with respect to the first frequency. When one of the one end and the other end of the first line is short-circuited to the reference potential in an AC manner, therefore, the other of the one end and the other end of the first line enters an open state with respect to the first frequency.

The first capacitor and the second line resonate and the second capacitor and the third line resonate with respect to the second frequency. Therefore, the one end and the other end of the first line are short-circuited to the reference potential with respect to the second frequency.

In this case, the parameters of the first, second and third lines and the first and second capacitors are adjusted, thereby making it possible to shorten the first, second and third lines as well as to arbitrarily set the second frequency.

Consequently, there is provided a distributed constant circuit which has characteristics equivalent to a λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

It is preferable that the characteristic impedance Z

a

of the first line, the length L

a

of the first line, the characteristic impedance Z

b

of the second and third lines, the length L

b

of the second and third lines, the capacitance value C of the first and second capacitors, the impedance Z

c

of the first and second impedance elements, a first frequency f

1

, a wavelength λ

1

corresponding to the first frequency, a second frequency f

2

, and a wavelength λ

2

corresponding to the second frequency satisfy relations expressed by equations (4), (5) and (6):

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{\frac{j Z_{c}}{Z_{a}} (\frac{1}{j 2 π f_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})}{Z_{c} + \frac{1}{j2π f_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b}}} & (4) \\ L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (5) \\ Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (6) \end{matrix}

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{\frac{j Z_{c}}{Z_{a}} (\frac{1}{j 2 π f_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})}{Z_{c} + \frac{1}{j2π f_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b}}} & (4) \\ L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (5) \\ Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (6) \end{matrix}

In the distributed constant circuit, by satisfying the equation (6), voltage/current characteristics equivalent to the line having a length which is one-fourth the wavelength corresponding to the first frequency are obtained with respect to the first frequency.

By satisfying the equation (5), the capacitor and the second line resonate with respect to the second frequency. Therefore, the other end of the first line is short-circuited to the reference potential with respect to the second frequency.

Furthermore, by satisfying the equation (4), the other end of the first line enters an open state with respect to the first frequency.

In this case, the parameters of the first and second lines and the capacitor are adjusted, thereby making it possible to shorten the first and second lines as well as to arbitrarily set the second frequency.

Consequently, there is provided a distributed constant circuit which has characteristics equivalent to a λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

The impedance element may comprise an impedance device.

In this case, the parameter of the impedance element is adjusted in addition to the parameters of the first and second lines and the capacitor, thereby making it possible to shorten the first and second lines as well as to arbitrarily set the second frequency.

Consequently, the distributed constant circuit can have characteristics equivalent to the λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

The impedance element may be a shift of the impedance from a 50 ohm system in a case where a circuit connected to the other end of the first line is viewed from the other end.

In this case, even when the impedance in a case where the circuit connected to the other end of the first line is viewed from the other end is shifted from the 50 ohm system, the distributed constant circuit can have characteristics equivalent to the λ/4 line, can be miniaturized, and can suppress an arbitrary frequency.

The one end of the first line may be connected to a bias voltage, and the other end of the first line may be connected to an electrode of a transistor.

The first frequency may be the frequency of a fundamental wave, and the second frequency may be higher than the frequency of second harmonics relative to the fundamental wave.

A high-frequency circuit according to another aspect of the present invention comprises a transistor, a bias applying circuit for applying a DC bias to one electrode of the transistor, and a matching circuit for performing impedance matching between the electrode of the transistor and the other circuit, the bias applying circuit being constituted by any one of the above-mentioned distributed constant circuits, the matching circuit being provided between the bias applying circuit and the other circuit.

In the high-frequency circuit, the bias applying circuit is constituted by any one of the distributed constant circuits, thereby making it possible to transmit a signal having a first frequency between the electrode of the transistor and the other circuit while suppressing a second frequency and to apply a DC bias to the electrode of the transistor.

In this case, the matching circuit is provided between the bias applying circuit and the other circuit, so that frequency characteristics of a reflection coefficient at a node between the matching circuit and the other circuit have a wide peak directed downward at the first frequency. Consequently, wide band characteristics centered around the first frequency are obtained.

A high-frequency circuit according to still another aspect of the present invention comprises a transistor, a bias applying circuit for applying a DC bias to one electrode of the transistor, and a matching circuit for performing impedance matching between the electrode of the transistor and the other circuit, the bias applying circuit being constituted by any one of the above-mentioned distributed constant circuits, the matching circuit being provided between the electrode of the transistor and the bias applying circuit.

In the high-frequency circuit, the bias applying circuit is constituted by any one of the distributed constant circuits, thereby making it possible to transmit a signal having a first frequency between the electrode of the transistor and the other circuit while suppressing a second frequency and to apply a DC bias to the electrode of the transistor.

In this case, the matching circuit is provided between the electrode of the transistor and the bias applying circuit, so that frequency characteristics of a reflection coefficient at a node between the bias applying circuit and the other circuit have a narrow peak directed downward at the first frequency. Consequently, narrow band characteristics centered around the first frequency are obtained.

The high-frequency circuit may further comprise a harmonic removing circuit connected to the electrode of the transistor for removing a harmonic component relative to the first frequency.

In this case, it is possible to reliably remove the harmonic component relative to the first frequency while transmitting the first frequency between the electrode of the transistor and the other circuit.

A bias applying circuit according to another aspect of the present invention for bringing one electrode of a transistor into an open state with respect to the frequency of a fundamental wave and applying a DC bias to the electrode of the transistor comprises a resonance circuit connected between the electrode of the transistor and a predetermined reference potential, the resonance frequency of the resonance circuit being higher than the frequency of the second harmonics relative to the fundamental wave.

In the bias applying circuit, a DC bias is applied to the one electrode of the transistor, and the electrode of the transistor enters an open state with respect to the frequency of the fundamental wave. Further, the resonance circuit is connected between the electrode of the transistor and the reference potential, so that the electrode of the transistor enters a short-circuited state with respect to the resonance frequency of the resonance circuit. Consequently, the component of the resonance frequency of the resonance circuit is suppressed in the electrode of the transistor. Particularly, the resonance frequency of the resonance circuit is set to a frequency higher than the frequency of the second harmonics relative to the fundamental wave, so that losses are reduced in an AB-class operation of the transistor, thereby achieving high efficiency.

A bias applying circuit according to still another aspect of the present invention for applying a DC bias to one electrode of a transistor comprises any one of the above-mentioned distributed constant circuits, a first frequency being the frequency of a fundamental wave, a second frequency being higher than the frequency of second harmonics relative to the fundamental wave.

The bias applying circuit comprises any one of the distributed constant circuits, so that it is possible to transmit a signal having the first frequency between the electrode of the transistor and the other circuit while suppressing the component of the second frequency and to apply the DC bias to the electrode of the transistor.

In this case, the first frequency is the frequency of the fundamental wave, and the second frequency is set to a frequency higher than the frequency of the second harmonics relative to the fundamental wave, so that losses are reduced in an AB-class operation of the transistor, thereby achieving high efficiency. Consequently, there is provided a bias applying circuit which can be miniaturized and increased in efficiency.

An impedance adjusting method according to another aspect of the present invention comprises the step of changing the impedance of a resonance circuit in the above-mentioned bias applying circuit, to adjust a load impedance in second harmonics.

In the impedance adjusting method, it is possible to adjust the load impedance in the second harmonics by changing the impedance of the resonance circuit in the bias applying circuit. Consequently, it is possible to control the efficiency of a transistor.

An impedance adjusting method according to still another aspect of the present invention comprises the step of adjusting a load impedance in second harmonics on the basis of the product of a current and a voltage in an electrode in the above-mentioned bias applying circuit.

In the impedance adjusting method, it is possible to adjust the load impedance in the second harmonics on the basis of the product of a current and a voltage in the electrode in the bias applying circuit. Consequently, it is possible to control the efficiency of a transistor.

A distributed constant circuit according to another aspect of the present invention comprises a line and a capacitor, one end of the line being connected to a predetermined reference potential in an AC manner, and the other end of the line being connected to the reference potential through the capacitor, the line and the capacitor constituting an inductor with respect to a predetermined frequency.

In the distributed constant circuit, the capacitor and the short line constitute an inductor. Consequently, it is possible to miniaturize the circuit and lower the cost thereof.

It is preferable that the characteristic impedance Z

a

of the line, the length L

a

of the line, the capacitance value C of the capacitor, a wavelength λ

1

corresponding to the predetermined frequency, and an angular frequency ω

1

corresponding to the predetermined frequency satisfy a relation expressed by an equation (7):

\begin{matrix} 1 > ω_{1} {CZ}_{a} \tan (\frac{2 π}{λ_{1}} L_{a}) & (7) \end{matrix}

The distributed constant circuit functions as an inductor by satisfying the equation (7).

A distributed constant circuit according to still another aspect of the present invention comprises a line, a capacitor, and an inductor component connected in series with the capacitor, one end of the line being connected to a predetermined reference potential in an AC manner, and the other end of the line being connected to the reference potential through a series connection between the capacitor and the inductor component, the line, the capacitor and the inductor component constituting an inductor with respect to a first frequency.

In the distributed constant circuit, the capacitor, the inductor component and the short line constitute an inductor. Consequently, it is possible to miniaturize the circuit and lower the cost thereof.

It is preferable that the characteristic impedance Z

a

of the line, the length L

a

of the line, the capacitance value C of the capacitor, the inductance L of the inductor component, a wavelength λ

1

corresponding to the first frequency, and an angular frequency ω

1

corresponding to the first frequency satisfy a relation expressed by an equation (8):

\begin{matrix} \frac{1}{ω_{1} C} > ω_{1} L + Z_{a} \tan (\frac{2 π}{λ_{1}} L_{a}) & (8) \end{matrix}

The distributed constant circuit functions as an inductor by satisfying the equation (8).

It is preferable that the capacitance value C of the capacitor, the inductance L of the inductor component, and an angular frequency ω

2

corresponding to a second frequency satisfy a relation expressed by an equation (9):

\begin{matrix} ω_{2} L = \frac{1}{ω_{2} C} & (9) \end{matrix}

In this case, by satisfying the equation (9), the other end of the line is short-circuited to the reference potential with respect to the second frequency. Therefore, it is possible to suppress the second frequency.

A distributed constant circuit according to a further aspect of the present invention comprises a first line, a capacitor, and a second line connected in series with the capacitor, one end of the line being connected to a predetermined reference potential in an AC manner, and the other end of the line being connected to the reference potential through a series connection between the capacitor and the second line, the first line, the capacitor and the second line constituting an inductor with respect to a first frequency.

In the distributed constant circuit, the capacitor and the short first and second lines constitute an inductor. Consequently, it is possible to miniaturize the circuit and lower the cost thereof.

It is preferable that the characteristic impedance Z

a

of the first line, the length L

a

of the first line, the characteristic impedance Z

b

of the second line, the length L

b

of the second line, the capacitance value C of the capacitor, a wavelength λ

1

corresponding to the first frequency, and an angular frequency ω

1

corresponding to the first frequency satisfy a relation expressed by an equation (10):

\begin{matrix} \frac{1}{ω_{1} C} > Z_{b} \tan (\frac{2 π}{λ_{1}} L_{b}) + Z_{a} \tan (\frac{2 π}{λ_{1}} L_{a}) & (10) \end{matrix}

The distributed constant circuit functions as an inductor by satisfying the equation (10).

It is preferable that the characteristic impedance Z

b

of the second line, the length L

b

of the second line, the capacitance value C of the capacitor, a wavelength λ

2

corresponding to a second frequency, and the angular frequency ω

2

corresponding to the second frequency satisfy a relation expressed by an equation (11):

\begin{matrix} \frac{1}{ω_{2} C} = Z_{b} \tan (\frac{2 π}{λ_{2}} L_{b}) & (11) \end{matrix}

In this case, by satisfying the equation (11) , the other end of the first line is short-circuited to the reference potential with respect to the second frequency. Therefore, it is possible to suppress the second frequency.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a circuit diagram showing a distributed constant circuit in one embodiment of the present invention;

FIG. 2

is a diagram showing parameters in a λ/4 line;

FIG. 3

is a diagram showing parameters in the distributed constant circuit in the embodiment;

FIG. 4

is a diagram showing the results of simulation of frequency characteristics of S

11

and S

21

in the λ/4 line and the distributed constant circuit in the embodiment;

FIG. 5

is a circuit diagram of a bias applying circuit using the distributed constant circuit shown in

FIG. 1

;

FIG. 6

is a diagram showing parameters in a bias applying circuit in a comparative example 1 using the λ/4 line;

FIG. 7

is a diagram showing the results of simulation of frequency characteristics of S

11

and S

21

in the bias applying circuit-shown in

FIG. 6

;

FIG. 8

is a diagram showing parameters in a bias applying circuit in a comparative example 2 using a distributed constant circuit shown in

FIG. 38

;

FIG. 9

is a diagram showing the results of simulation of frequency characteristics of S

11

and S

21

in the bias applying circuit shown in

FIG. 8

;

FIG. 10

is a diagram showing parameters in a bias applying circuit in an embodiment using the distributed constant circuit shown in

FIG. 1

;

FIG. 11

is a diagram showing the results of simulation of frequency characteristics of S

11

and S

21

in the bias applying circuit shown in

FIG. 10

;

FIG. 12

is a diagram showing a circuit to be replaced when an input-side impedance and an output-side impedance are shifted from 50 Ω;

FIG. 13

is a circuit diagram of a distributed constant circuit considering shifts of the input-side impedance and the output-side impedance from 50Ω;

FIG. 14

is a circuit diagram of a bias applying circuit using the distributed constant circuit shown in

FIG. 13

;

FIG. 15

is a diagram showing the results of simulation of frequency characteristics of S

11

and S

21

in the bias applying circuit shown in

FIG. 14

;

FIG. 16

is a diagram for explaining a method of calculating a relational expression of parameters in the distributed constant circuit shown in

FIG. 1

;

FIG. 17

is a diagram for explaining a method of calculating a relational expression of parameters in the distributed constant circuit shown in

FIG. 1

;

FIG. 18

is a diagram for explaining a method of calculating a relational expression of parameters in the distributed constant circuit shown in

FIG. 1

;

FIG. 19

is a diagram for explaining a method of calculating a relational expression of parameters in the distributed constant circuit shown in

FIG. 13

;

FIG. 20

is a circuit diagram showing one example of a high-frequency circuit including the bias applying circuit shown in

FIG. 5

;

FIG. 21

is a circuit diagram showing a specific example of a matching circuit in the high-frequency circuit shown in

FIG. 20

;

FIG. 22

is a circuit diagram showing another example of a high-frequency circuit including the bias applying circuit shown in

FIG. 5

;

FIG. 23

is a circuit diagram showing a specific example of a matching circuit in the high-frequency circuit shown in

FIG. 22

;

FIG. 24

is a diagram showing the results of calculation of the frequency dependence of a reflection coefficient in each of the high-frequency circuits shown in

FIGS. 21 and 23

;

FIG. 25

is a circuit diagram showing still another example of a high-frequency circuit including the bias applying circuit shown in

FIG. 5

;

FIG. 26

is a circuit diagram of a high-frequency circuit for explaining the increase in efficiency of a FET;

FIG. 27

is a Smith chart showing the results of simulation of the change in a load impedance at the drain terminal of the FET in a case where the capacitance value of a capacitor in a bias applying circuit shown in

FIG. 26

is changed;

FIG. 28

is a waveform diagram of a drain current in a AB-class operation of the FET;

FIG. 29

is a diagram showing a load line in a case where the drain terminal of the FET is brought into a short-circuited state in the bias applying circuit shown in

FIG. 26

;

FIG. 30

is a diagram showing a load line in a case where the drain terminal of the FET is not brought into a short-circuited state in the bias applying circuit shown in

FIG. 26

;

FIG. 31

is a circuit diagram mainly showing a bias applying circuit including a third harmonic processing circuit;

FIG. 32

is a diagram showing the relation between the capacitance value of a capacitor and the length of a line in the distributed constant circuit according to the embodiment shown in

FIG. 1

;

FIG. 33

is a cross-sectional view showing a microstrip line;

FIG. 34

is a circuit diagram of a distributed constant circuit according to another embodiment of the present invention;

FIG. 35

is a circuit diagram showing one example of an amplifier using the distributed constant circuit shown in

FIG. 34

;

FIG. 36

is a diagram showing the results of calculation of the relation between the length of a line and an input impedance in the distributed constant circuit shown in FIG.

34

(

b

);

FIG. 37

is a diagram showing a conventional λ/4 line;

FIG. 38

is a circuit diagram of a conventional distributed constant circuit equivalent to the λ/4 line shown in

FIG. 37

; and

FIG. 39

is a circuit diagram of a bias applying circuit using the distributed constant circuit shown in FIG.

38

.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1

is a circuit diagram of a distributed constant circuit in one embodiment of the present invention.

In

FIG. 1

, a line

1

is connected between a node NA and a node NB. The node NA is grounded through a series connection between a capacitor

4

and a line

2

, and the node NB is grounded through a series connection between a capacitor

5

and a line

3

. Each of the lines

1

,

2

and

3

is constituted by a microstrip line, for example. In the present embodiment, a ground potential corresponds to a reference potential.

Z

a

is the characteristic impedance of the line

1

, L

a

is the length of the line

1

, Z

b

is the characteristic impedance of the lines

2

and

3

, and L

b

is the length of the lines

2

and

3

. C is the capacitance value (capacitance) of the capacitors

4

and

5

.

In the distributed constant circuit shown in

FIG. 1

, the characteristic impedances Z

a

and Z

b

, the lengths L

a

and L

b

, and the capacitance value C are set so as to satisfy the following equations (1), (2) and (3):

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{1}{Z_{a}} (\frac{1}{2 π f_{1} C} - Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})} & (1) \\ L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (2) \\ Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (3) \end{matrix}

In the foregoing equations (1), (2) and (3), f

1

is the frequency of a fundamental wave (a fundamental frequency), f

2

is a frequency to be suppressed, λ

1

is the wavelength of the fundamental wave, and λ

2

is a wavelength corresponding to the frequency to be suppressed. A method of driving the equations (1), (2) and (3) will be described later.

In the distributed constant circuit shown in

FIG. 1

, when the node NA is brought into a grounded state in an AC manner, the node NB enters an open state with respect to the fundamental frequency f

1

, and enters a short-circuited state with respect to the frequency f

2

. Consequently, it is possible to obtain characteristics equivalent to a λ/4 line while shortening the lines as well as to reduce gain at the arbitrary frequency f

2

.

Frequency characteristics of S

11

and S

21

in the λ/4 line and the distributed constant circuit in the present embodiment were simulated. S

11

is an S parameter representing an input reflection coefficient, and S

21

is an S parameter representing gain.

FIG. 2

is a diagram showing parameters in the λ/4 line and

FIG. 3

is a diagram showing parameters in the distributed constant circuit in the embodiment. The fundamental frequency is 1.5 GHz.

As shown in

FIG. 2

, a λ/4 line

100

is connected between nodes NA and NB. The width W

0

of the λ/4 line

100

is 1945 μm, the length L

0

thereof is 18000 μm, and the characteristic impedance Z

0

thereof is 25 Ω.

As shown in

FIG. 3

, the width W

a

of a line

1

is 592 μm, the length L

a

thereof is 6575 μm, and the characteristic impedance Z

a

thereof is 50 Ω. The width W

b

of a line

2

is 592 μm, the length L

b

thereof is 2248 μm, and the characteristic impedance Z

b

thereof is 50 Ω. Similarly, the width W

b

of a line

3

is 592 μm, the length L

b

thereof is 2248 μm, and the characteristic impedance Z

b

thereof is 50 Ω. The capacitance values C of capacitors

4

and

5

are respectively 2.8 pF.

FIG. 4

is a diagram showing the results of the simulation of S

11

and S

21

between the nodes NA and NB in the λ/4 line

100

and the distributed constant circuit in the present embodiment. In

FIG. 4

, a square mark indicates S

11

in the λ/4 line

100

, and a circular mark indicates S

11

in the distributed constant circuit in the embodiment, a downward triangular mark indicates S

21

in the λ/4 line

100

, and an upward triangular mark indicates S

21

in the distributed constant circuit in the embodiment.

As shown in

FIG. 4

, S

11

(an input reflection coefficient) and S

21

(gain) in the distributed constant circuit in the embodiment and S

11

and S

12

in the λ/4 line

100

respectively coincide with each other at a fundamental frequency of 1.5 GHz. That is, it is found that the distributed constant circuit in the embodiment functions as the λ/4 circuit with respect to the fundamental wave while the lengths of the lines

1

,

2

and

3

are being made smaller than those in the λ/4 line.

FIG. 5

is a circuit diagram of a bias applying circuit to which the distributed constant circuit of

FIG. 1

is operably linked. The bias applying circuit

10

shown in

FIG. 5

functions as a drain bias applying circuit for applying a drain bias V

dd

to a FET

20

.

In the bias applying circuit

10

shown in

FIG. 5

, a line

1

is connected between a node NA and a node NB, and the node NA is grounded through a capacitor

11

. The drain bias V

dd

is applied to the node NA. The node NB is connected to the drain of the FET

20

, and is grounded through a series connection between a line

3

and a capacitor

5

.

Z

fr

is an impedance in a case where an input side (a terminal A) is viewed from the node NB (hereinafter referred to as an input-side impedance), and Z

lo

is an impedance in a case where an output side (a terminal B) is viewed from the node NB (hereinafter referred to as an output-side impedance). Z

cir

is an impedance in a case where a circuit other than the distributed constant circuit is viewed from the node NB. The input-side impedance Z

fr

and the output-side impedance Z

lo

are respectively taken as 501 Ω.

Frequency characteristics of S

11

and S

21

in a bias applying circuit in a comparative example 1 using the λ/4 line, a bias applying circuit in a comparative example 2 using the conventional distributed constant circuit shown in

FIG. 38

, and a bias applying circuit in the embodiment having a circuit arrangement of

FIG. 5

have been simulated. In the simulation, a substrate composed of an alumina material having a thickness of 635 μm and having a dielectric constant of 10 has been used.

FIG. 6

is a diagram showing parameters in the bias applying circuit in the comparative example 1. In

FIG. 6

, a λ/4 line

100

is connected between a node NA and a node NB. The node NA is grounded through a capacitor

11

, and the node NB is connected between terminals A and B.

The width W

0

of the λ/4 line

100

is 1945 μm, the length L

0

thereof is 18000 μm, and the characteristic impedance Z

0

thereof is 25 Ω. The capacitance value C

g

of the capacitor

11

is 1000 pF.

FIG. 7

is a diagram showing the results of the simulation of the frequency characteristics of S

11

and S

21

between the terminals A and B in the bias applying circuit shown in FIG.

6

.

As shown in

FIG. 7

, in the bias applying circuit shown in

FIG. 6

, S

11

(an input reflection coefficient) is decreased at a fundamental frequency of 1.5 GHz, and S

21

(gain) is decreased at the second harmonic (3.0 GHz). That is, in the bias applying circuit shown in

FIG. 6

, it is found that the node NB is in an open state with respect to a fundamental wave, and is in a short-circuited state with respect to the second harmonic.

FIG. 8

is a diagram showing parameters in the bias applying circuit in the comparative example 2. In

FIG. 8

, a line

101

is connected between a node NA and a node NB. The node NA is grounded through a capacitor

11

, and the node NB is grounded through a capacitor

103

and is connected between terminals A and B.

The width W

1

of the line

101

is 592 μm, the length L

1

thereof is 6500 μm, and the characteristic impedance Z

1

thereof is 50 Ω. The capacitance value C

1

of the capacitor

103

is 3.68 pF, and the capacitance value C

g

of the capacitor

11

is 1000 pF. The length of a λ/4 line in a case where the characteristic impedance is 50 Ω is 19500 μm, so that the length of the line

101

corresponds to λ/12.

FIG. 9

is a diagram showing the results of the simulation of the frequency characteristics of S

11

and S

21

between the terminals A and B in the bias applying circuit shown in FIG.

8

.

As shown in

FIG. 9

, in the bias applying circuit shown in

FIG. 8

, S

11

(an input reflection coefficient) is decreased at a fundamental frequency of 1.5 GHz, while S

21

(gain) is not decreased at the second harmonic (3.0 GHz). That is, in the bias applying circuit shown in

FIG. 8

, it is found that the node NB is in an open state with respect to a fundamental wave, while not being in a short-circuited state with respect to the second harmonic. Although the line can be shortened, therefore, the power-added efficiency of an amplifier cannot be improved.

FIG. 10

is a diagram showing parameters in the bias applying circuit in the embodiment. In

FIG. 10

, a line

1

is connected between a node NA and a node NB. The node NA is grounded through a capacitor

11

, and the node NB is grounded through a series connection between a capacitor

5

and a line

3

and is connected between terminals A and B.

The width W

a

of the line

1

is 592 μm, the length L

a

thereof is 6575 μm, and the characteristic impedance Z

a

thereof is 50 Ω. The width W

b

of the line

3

is 592μm, the length L

b

thereof 2248 μm, and the characteristic impedance Z

b

thereof is 50 Ω. The capacitance value C of the capacitor

5

is 2.8 pF, and the capacitance value C

g

of the capacitor

11

is 1000 pF.

FIG. 11

is a diagram showing the results of the simulation of the frequency characteristics of S

11

and S

21

between the terminals A and B in the bias applying circuit shown in FIG.

10

.

As shown in

FIG. 11

, in the bias applying circuit shown in

FIG. 10

, S

11

(an input reflection coefficient) is decreased at a fundamental frequency of 1.5 GHz, and S

21

(gain) is decreased at the second harmonic (3.0 GHz). That is, in the bias applying circuit shown in

FIG. 10

, it is found that the node NB is in an open state with respect to a fundamental wave, and is in a short-circuited state with respect to the second harmonic, so that characteristics close to those of the λ/4 line

100

are obtained. Consequently, it is possible to shorten the lines, and improve the power-added efficiency of an amplifier.

Although in the bias applying circuit

10

shown in

FIG. 5

, the input-side impedance Z

fr

and the output-side impedance Z

lo

are respectively taken as 50 Ω, the input-side impedance Z

fr

and the output-side impedance Z

lo

may be shifted from 50 Ω in the actual circuit. In this case, the impedance Z

cir

in a case where a circuit other than the distributed constant circuit is viewed from the node NB is replaced with that in a circuit arrangement of FIG.

12

. In

FIG. 12

, an impedance Z

c

is connected to a node NB. The impedance Z

c

corresponds to shifts of the input-side impedance Z

fr

and the output-side impedance Z

lo

from 50Ω.

The impedance Z

c

is found in the following manner. First, the impedance Z

cir

shown in

FIG. 5

is found by measurement or calculation. It is then assumed that the input-side impedance Z

fr

and the output-side impedance Z

lo

are respectively 50 Ω, to find the impedance Z

c

such that an impedance Z

cir

shown in

FIG. 12

is equal to the impedance Z

cir

shown in FIG.

5

.

FIG. 13

is a circuit diagram of a distributed constant circuit equivalent to a λ/4 line in a case where the impedance Z

c

shown in

FIG. 12

is considered.

In the distributed constant circuit shown in

FIG. 13

, impedance elements

6

and

7

each having an impedance Z

c

are further provided in the arrangement of the distributed constant circuit shown in

FIG. 1. A

node NA is grounded through the impedance element

6

, and a node NB is grounded through the impedance element

7

.

In the distributed constant circuit shown in

FIG. 13

, characteristic impedances Z

a

and Z

b

, an impedance Z

c

, lengths L

a

and L

b

, and a capacitance value C are set so as to satisfy the following equations (4), (5) and (6):

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{\frac{j Z_{c}}{Z_{a}} (\frac{1}{j 2 π f_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})}{Z_{c} + \frac{1}{j2π f_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b}}} & (4) \\ L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (5) \\ Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (6) \end{matrix}

In the foregoing equations (4), (5) and (6), f

1

is the frequency of a fundamental wave (a fundamental frequency), f

2

is a frequency to be suppressed, λ

1

is the wavelength of the fundamental wave, and λ

2

is a wavelength corresponding to the frequency to be suppressed. A method of deriving the equations (4), (5) and (6) will be described later.

In the distributed constant circuit shown in

FIG. 13

, when the node NA is grounded in an AC manner, the node NB enters an open state with respect to the fundamental frequency f

1

, and enters a short-circuited state with respect to the frequency f

2

to be suppressed. Consequently, it is possible to obtain characteristics equivalent to a λ/4 line while shortening the lines as well as to decrease gain at an arbitrary frequency f

2

.

FIG. 14

is a diagram showing parameters in a bias applying circuit using the distributed constant circuit shown in FIG.

13

. In

FIG. 14

, a line

1

is connected between a node NA and a node NB. The node NA is grounded through a capacitor

11

, and the node NB is grounded through a series connection between a line

5

and a capacitor

3

, is grounded through an Impedance element

7

, and is connected between terminals A and B.

The width W

a

of the line

1

is 592 μm, the length L

a

thereof is 4430 μm, and the characteristic impedance Z

a

thereof is 50 Ω. The width W

b

of the line

3

is 592μm, the length L

b

thereof is 2248 μm, and the characteristic impedance Z

b

thereof is 50 Ω. The capacitance value C of the capacitor

5

is 2.8 pF, the capacitance value C

g

of the capacitor

11

is 1000 pF, and the impedance Z

c

of the impedance element

7

is 2.0 pF.

FIG. 15

is a diagram showing the results of the simulation of the frequency characteristics of S

11

and S

21

between the terminals A and B in the bias applying circuit shown in FIG.

14

.

As shown in

FIG. 15

, in the bias applying circuit shown in

FIG. 14

, S

11

(an input reflection coefficient) is decreased at a fundamental frequency of 1.5 GHz, and S

21

(gain) is decreased at the second harmonics (3.0 GHz). That is, in the bias applying circuit shown in

FIG. 14

, it is found that the node NB is in an open state with respect to the fundamental wave of 1.5 GHz, and is in a short-circuited state with respect to the second harmonic, so that characteristics closer to those of a λ/4 line are obtained.

Although in the above-mentioned example, description is made of a case where the impedance Z

c

corresponds to shifts of the input-side impedance Z

fr

and the output-side impedance Z

lo

from 50 Ω, an impedance device having an impedance Z

c

may be provided in a case where the input-side impedance Z

fr

and the output-side impedance Z

lo

are 50Ω.

Although in the above-mentioned embodiment, the frequency f

2

to be suppressed is taken as the second harmonic (3.0 GHz), the frequency f

2

can be arbitrarily set if the parameters are set so as to satisfy the foregoing equation (2) or (5). Consequently, the distributed constant circuit shown in

FIG. 1

or

13

functions as a λ/4 line having filter characteristics.

As described in the foregoing, in the distributed constant circuit according to the present embodiment, it is possible to miniaturize the circuit serving as the λ/4 line and to suppress an arbitrary frequency.

When the distributed constant circuit according to the present embodiment is used as a bias applying circuit, it is possible to miniaturize the bias applying circuit as well as to form a short-circuited state with respect to the second harmonic. Therefore, it is possible to fabricate a small-sized and highly efficient amplifier.

Furthermore, in the distributed constant circuit according to the present embodiment, frequency filter characteristics for decreasing gain at an arbitrary frequency f

2

are obtained. Consequently, it is possible to suppress frequencies other than a required frequency, thereby obtaining effects such as prevention of oscillation of a FET and the suppression of spurious.

The distributed constant circuit according to the present embodiment is applicable to various types of circuits such as an amplifier, a distributor, a synthesizer, a directional coupler, a mixer, and a filter.

Description is now made of a method of deriving the foregoing equations (1), (2) and (3).

The basic items of the distributed constant circuit will be described while referring to

FIGS. 16 and 17

before the equations (1), (2) and (3) are derived.

FIG.

16

(

a

) is a diagram showing the relation between a voltage and a current in a λ/4 line

100

. In FIG.

16

(

a

), Z

0

is the characteristic impedance of the λ/4 line

100

, and L

0

is the length of the λ/4 line

100

. V

1

is an input voltage, V

2

is an output voltage, I

1

is an input current, and I

2

is an output current. The relation between a voltage and a current in the λ/4 line

100

and a [F

1

] matrix are expressed by the following equation (A1):

\begin{matrix} [\begin{matrix} V_{1} \\ I_{1} \end{matrix}] = [F_{1}] [\begin{matrix} V_{2} \\ I_{2} \end{matrix}] [F_{1}] = [\begin{matrix} 0 & j Z_{0} \\ j \frac{1}{Z_{0}} & 0 \end{matrix}] & (A1) \end{matrix}

FIG.

16

(

b

) is a diagram showing the relation between a voltage and a current in a line

300

having a characteristic impedance Z

a

and having a length L

a

. The relation between a voltage and a current in the line

300

shown in FIG.

16

(

b

) and a [F

2

] matrix are expressed by the following equation (A2):

\begin{matrix} [\begin{matrix} V_{1} \\ I_{1} \end{matrix}] = [F_{2}] [\begin{matrix} V_{2} \\ I_{1} \end{matrix}] [F_{2}] = [\begin{matrix} \cos \frac{2 π}{λ} L_{a} & j Z_{a} \sin \frac{2 π}{λ} L_{a} \\ j \frac{1}{Z_{a}} \sin \frac{2 π}{λ} L_{a} & \cos \frac{2 π}{λ} L_{a} \end{matrix}] & (A2) \end{matrix}

FIG.

16

(

c

) is a diagram showing the relation between a voltage and a current in a π-type circuit. In FIG.

16

(

c

), Z

a

is the characteristic impedance of a line

301

, and L

a

is the length of the line

301

. Further, Z

2

is the impedance of lines

302

and

303

. The relation between a voltage and a current in the π-type circuit shown in FIG.

16

(

c

) and a [F

3

] matrix are expressed by the following equation (A3):

\begin{matrix} [\begin{matrix} V_{1} \\ I_{1} \end{matrix}] = [F_{3}] [\begin{matrix} V_{2} \\ I_{2} \end{matrix}] [F_{3}] = [\begin{matrix} 1 & 0 \\ \frac{1}{Z_{2}} & 1 \end{matrix}] [F_{2}] [\begin{matrix} 1 & 0 \\ \frac{1}{Z_{2}} & 1 \end{matrix}] & (A3) \end{matrix}

In order that the λ/4 line

100

shown in FIG.

16

(

a

) and the π-type circuit shown in FIG.

16

(

c

) are equivalent to each other, the relation of [F

1

]=[F

3

] must be satisfied. The first row and the second column in the [F

3

] matrix is jZ

a

sin(2π/λ)L

a

, and the first row and the second column in the [F

1

] matrix is jZ

0

. Consequently the following equation (A4) holds:

\begin{matrix} j Z_{a} \sin \frac{2 π}{λ} L_{a} = j Z_{0} & (A4) \end{matrix}

FIG.

17

(

a

) is a diagram showing a line

304

having its output terminal short-circuited to a ground potential. In FIG.

17

(

a

), Z

0

is the characteristic impedance of the line

304

, and L

0

is the length of the line

304

. The input impedance Z

in

of the line

304

is expressed by the following equation (A5):

\begin{matrix} Z_{i n} = j Z_{0} \tan \frac{2 π}{λ} L_{0} & (A5) \end{matrix}

FIG.

17

(

b

) is a diagram showing the relation between the length L

0

of the line

304

and an input impedance Z

in

shown in FIG.

17

(

a

). As shown in FIG.

17

(

b

), in the range of 0<L

0

<λ/4, for example, the input impedance Z

in

is positive, so that the line

304

functions as an inductor. In this case, the impedance Z

L

of the inductor is JωL.

Referring to

FIGS. 18 and 19

, the foregoing equations (1), (2), and (3) will be derived.

Derivation of equation (3)

A λ/4 line

100

shown in FIG.

18

(

a

) and a distributed constant circuit shown in FIG.

18

(

b

) shall be equivalent to each other at a fundamental frequency. Let f

1

be a fundamental frequency, and λ

1

be a wavelength corresponding to the fundamental frequency f

1

.

In FIG.

18

(

a

), the following equation (B1) holds from the foregoing equation (A1):

V

1

=j Z

0

I

2

(B1)

In FIG.

18

(

b

), the following equation (B2) holds from the foregoing equation (A4):

\begin{matrix} V_{1} = j Z_{a} \sin \frac{2 π}{λ_{1}} L_{a} I_{2} & (B2) \end{matrix}

The following equation (B3) holds from the equations (B1) and (B2):

\begin{matrix} j Z_{0} I_{2} = j Z_{a} \sin \frac{2 π}{λ_{1}} L_{a} I_{2} & (B3) \end{matrix}

The following equation (B4) is derived from the equation (B3):

\begin{matrix} Z_{a} = \frac{Z_{0}}{\sin \frac{2 π}{λ_{1}} L_{a}} & (B4) \end{matrix}

The equation (B4) corresponds to the equation (3).

{circle around (2)} Derivation of Equation (2)

In order that the distributed constant circuit shown in FIG.

18

(

b

) enters a short-circuited state with respect to a frequency f

2

(a wavelength λ

2

), capacitors

4

and

5

and lines

2

and

3

may respectively resonate. Letting L be an inductor component which resonates with a capacitance value C, the following equation (B5) holds:

\begin{matrix} 2 π f_{2} = \frac{1}{\sqrt{LC}} & (B5) \end{matrix}

The following equation (B6) is obtained from the equation (B5):

\begin{matrix} L = \frac{1}{C \cdot 4 π^{2} f_{2}^{2}} & (B6) \end{matrix}

Since the impedance of the lines

2

and

3

is jZ

b

tan(2π/λ

2

)L

b

, the following equation (B7) holds from the relation shown in FIG.

17

:

\begin{matrix} {jω}_{2} L = j Z_{b} \tan \frac{2 π}{λ_{2}} L_{b} & (B7) \end{matrix}

where ω

2

is an angular velocity corresponding to the frequency f

2

.

When the equation (B6) is substituted into the equation (B7), the following equation (B8) is obtained:

\begin{matrix} j2π f_{2} \cdot \frac{1}{C \cdot 4 π^{2} f_{2}^{2}} = j Z_{b} \tan \frac{2 π}{λ_{2}} L_{b} & (B8) \end{matrix}

When the equation (B8) is deformed, the following equation (B9) is obtained:

\begin{matrix} L_{b} = \frac{λ_{2}}{2 π} \arctan \frac{1}{C \cdot 2 π f_{2} Z_{b}} & (B9) \end{matrix}

The equation (B9) corresponds to the equation (2).

{circle around (3)} Derivation of equation (1)

In order that the distributed constant circuit shown in FIG.

18

(

b

) is equivalent to the λ/4 line

100

shown in FIG.

18

(

a

), when one end is short-circuited to a ground potential the other end must enter an open state with respect to the fundamental frequency f

1

, as shown in FIG.

18

(

c

).

In FIG.

18

(

c

), an impedance Z

1

in a case where the line

1

is viewed from a node NA is expressed by the following equation (B10):

\begin{matrix} Z_{1} = j Z_{a} \tan \frac{2 π}{λ_{1}} L_{b} & (B10) \end{matrix}

An impedance Z

2

in a case where a capacitor

4

and a line

2

are viewed from the node NA is expressed by the following equation (B

11

):

\begin{matrix} Z_{2} = \frac{1}{{jω}_{1} C} + j Z_{a} \tan \frac{2 π}{λ_{1}} L_{b} & (B11) \end{matrix}

An admittance Y

in

in a case where the whole of the distributed constant circuit is viewed from the node NA is expressed by the following equation (B12):

\begin{matrix} Y_{i n} = \frac{1}{Z_{1}} + \frac{1}{Z_{2}} = \frac{Z_{1} + Z_{2}}{Z_{1} Z_{2}} & (B12) \end{matrix}

In order that the node NA enters an open state, Y

in

must be zero. Accordingly, the following equation (B13) holds:

Z

1

+Z

2

=0 (B13)

When the equations (B10) and (B11) are substituted into the equation (B13), the following equation (B14) is obtained:

\begin{matrix} j Z_{a} \tan \frac{2 π}{λ_{1}} L_{a} + \frac{1}{j ω_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b} = 0 & (B14) \end{matrix}

When the equation (B14) is deformed, the following equation (B15) is obtained:

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{1}{Z_{a}} (\frac{1}{2 π f_{1} C} - Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})} & (B15) \end{matrix}

The equation (B15) corresponds to the equation (1).

{circle around (4)} Derivation of equation (6)

The equation (6) is derived in the same manner as the foregoing item {circle around (1)}.

{circle around (5)} Derivation of equation (5)

The equation (5) is derived in the same manner as the foregoing item {circle around (2)}.

{circle around (6)} Derivation of equation (4)

The equation (4) is derived in the same manner as the foregoing item {circle around (3)}. As shown in

FIG. 19

, when one end is short-circuited to a ground potential, the other end must enter an open state with respect to the fundamental frequency f

1

.

In

FIG. 19

, an impedance Z

1

in a case where a line

1

is viewed from a node NA is expressed by the following equation (C1):

\begin{matrix} Z_{1} = j Z_{a} \tan \frac{2 π}{λ} L_{a} & (C1) \end{matrix}

An impedance Z

2

in a case where a capacitor

4

and a line

2

are viewed from the node NA is expressed by the following equation (C2):

\begin{matrix} Z_{2} = \frac{Z_{c} (\frac{1}{j ω_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})}{Z_{c} + \frac{1}{{jω}_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b}} & (C2) \end{matrix}

An admittance Y

in

in a case where the whole of the distributed constant circuit is viewed from the node NA is expressed by the following equation (C3):

\begin{matrix} Y_{i n} = \frac{1}{Z_{1}} + \frac{1}{Z_{2}} = \frac{Z_{1} + Z_{2}}{Z_{1} Z_{2}} & (C3) \end{matrix}

In order that the node NA enters an open state, Y

in

must be zero. Accordingly, the following equation (C4) holds:

Z

1

+Z

2

=0 (C4)

When the equations (C1) and (C2) are substituted into the equation (C4), the following equation (C5) is obtained:

\begin{matrix} j Z_{a} \tan = \frac{2 π}{λ_{1}} L_{a} + \frac{Z_{c} (\frac{1}{j ω_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})}{Z_{c} + \frac{1}{{jω}_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b}} = 0 & (C5) \end{matrix}

When the equation (C5) is deformed, the following equation (C6) is obtained:

\begin{matrix} L_{a} = \frac{λ_{1}}{2 π} \arctan {\frac{\frac{j Z_{c}}{Z_{a}} (\frac{1}{{jω}_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b})}{Z_{c} + \frac{1}{{jω}_{1} C} + j Z_{b} \tan \frac{2 π}{λ_{1}} L_{b}}} & (C6) \end{matrix}

The equation (C6) corresponds to the equation (4).

FIG. 20

is a circuit diagram showing a first example of a high-frequency circuit including a bias applying circuit using the distributed constant circuit shown in FIG.

5

. In the high-frequency circuit shown in

FIG. 20

, a matching circuit

30

is connected to the drain of a FET

20

. A bias applying circuit

10

is connected to a node NB between the drain of the FET

20

and the matching circuit

30

. Another circuit (not shown) is connected to a stage succeeding the matching circuit

30

.

In the high-frequency circuit shown in

FIG. 20

, the bias applying circuit

10

enters an open state with respect to a fundamental wave, so that the bias applying circuit

10

can be designed independently of the matching circuit

30

. Consequently, the bias applying circuit

10

and the matching circuit

30

can be independently adjusted.

The bias applying circuit

10

can be also designed by a 50 ohm system, or can be designed in consideration of the capacitance value of the FET

20

.

When the bias applying circuit

10

is designed by the 50 ohm system, the design becomes easy. In this case, even when the FET

20

performs a large signal operation, the bias applying circuit

10

can be kept in an open state with respect to the fundamental wave. Consequently, the designing method is applicable to a high-frequency circuit performing a large signal operation.

When the bias applying circuit

10

is designed in consideration of the capacitance value of the FET

20

, the length of the line

1

can be reduced. In this case, when the FET

20

performs a large signal operation, the capacitance value of the FET

20

varies, so that the bias applying circuit

10

cannot, in some cases, be kept in an open state with respect to the fundamental wave. Consequently, the designing method is applicable to a high-frequency circuit performing a small signal operation.

FIG. 21

is a circuit diagram showing a specific example of a matching circuit in the high-frequency circuit shown in FIG.

20

. In

FIG. 21

, a matching circuit

30

comprises a line

31

and a capacitor

32

. The line

31

is connected between a node NB and a port P

1

, and the capacitor

32

is connected between the port P

1

and a ground potential.

FIG. 22

is a circuit diagram showing a second example of a high-frequency circuit including a bias applying circuit using the distributed constant circuit shown in FIG.

5

. In the high-frequency circuit shown in

FIG. 22

, a matching circuit

30

is connected between the drain of a FET

20

and a node NB, and a bias applying circuit

10

is connected to the node NB. Another circuit (not shown) in a stage succeeding the matching circuit

30

is connected to the node NB.

In the high-frequency circuit shown in

FIG. 22

, the bias applying circuit

10

enters an open state with respect to a fundamental wave, so that the bias applying circuit

10

can be designed independently of the matching circuit

30

. Consequently, the bias applying circuit

10

and the matching circuit

30

can be independently adjusted.

Since an input-side impedance Z

fr

in a case where the FET

20

is viewed from the node NB is approximately 50 Ω, and an output-side impedance Z

lo

in a case where the other circuit connected to the node NB is viewed from the node NB is 50 Ω, the bias applying circuit

10

can be designed by a 50 ohm system. Consequently, the bias applying circuit

10

an be easily designed.

Furthermore, the matching circuit

30

is provided between the drain of the FET

20

and the bias applying circuit

10

. Even when the capacitance value of the FET

20

varies by a large signal operation of the FET

20

, therefore, the bias applying circuit

10

is not easily affected by the variation in the capacitance value.

FIG. 23

is a circuit diagram showing a specific example of the matching circuit in the high-frequency circuit shown in FIG.

22

. In

FIG. 23

, the matching circuit

30

comprises a line

31

and a capacitor

32

. The line

31

is connected between the drain of a FET

20

and a node NB, and the capacitor

32

is connected between the node NB and a ground potential.

The frequency dependence of a reflection coefficient in each of the high-frequency circuits shown in

FIGS. 21 and 23

has been calculated. In the calculation, a microstrip line has been used as the lines

1

,

3

, and

31

. The thickness of a substrate in the microstrip line is 635 nm, and the dielectric constant thereof is 9.7.

An impedance Z

frt

in a case where an input side is viewed from the drain of the PET

20

is 10 Ω. The characteristic impedance Z

a

of the line

1

is 50 Ω, and the length L

a

thereof is 4160 μm, while the characteristic impedance Z

b

of the line

3

is 50 Ω, and the length L

b

thereof is 1200 μm. The capacitance value C of the capacitor

5

is 5 pF, and the capacitance value C

g

of the capacitor

11

is 1000 pF. The characteristic impedance Z

m

of the line

31

is 50 Ω, the length L

m

thereof is 5455 μm, and the capacitance value C

m

of the capacitor

32

is 3.9 pF.

The results of the calculation are shown in FIG.

24

. As shown in

FIG. 24

, in the high-frequency circuit in the first example shown in

FIG. 21

, a reflection coefficient at the port P

1

has a wide peak directed downward centered around a frequency of 1.5 GHz. On the other hand, in the high-frequency circuit in the second example shown in

FIG. 23

, a reflection coefficient at the port P

1

has a narrow peak. directed downward centered around a frequency of 1.5 GHz. The results indicate that wide band characteristics are obtained in the high-frequency circuit shown in

FIG. 21

, while narrow band characteristics are obtained in the high-frequency circuit shown in FIG.

23

.

FIG. 25

is a circuit diagram showing a third example of a high-frequency circuit including a bias applying circuit using the distributed constant circuit shown in FIG.

5

. In the high-frequency circuit shown in

FIG. 25

, a matching circuit

30

is connected between the drain of a FET

20

and a node NB, a bias applying circuit

10

is connected to the node NB, and a second harmonic processing circuit

50

comprising a capacitor

51

and a line

52

are connected to the drain of the FET

20

.

In the high-frequency circuit shown in

FIG. 25

, a fundamental wave outputted from the drain of the FET

20

is transmitted to the other circuit while suppressing an arbitrary frequency, thereby making it possible to reliably remove the second harmonic relative to a fundamental wave.

Description is now made of the conditions of high efficiency using a high-frequency circuit shown in FIG.

26

. The high-frequency circuit shown in

FIG. 26

has the same arrangement as that of the high-frequency circuit shown in

FIGS. 20 and 21

. That is, a bias applying circuit

10

is connected to the drain of a FET

20

(a node NB). In the bias applying circuit

10

, a line

3

and a capacitor

5

constitute a resonance circuit.

The change in a load impedance at the drain terminal of the FET

20

in a case where the capacitance value C of the capacitor

5

in the bias applying circuit

10

is changed has been found by simulation.

FIG. 27

is a Smith chart showing the results of the simulation of the change in the load impedance at the drain terminal of the FET

20

in a case where the capacitance value C of the capacitor

5

in the bias applying circuit

10

is changed. In the simulation, the capacitance value C of the capacitor

5

in the bias applying circuit

10

has been changed to 2.0 pF, 1.5 pF, 1.0 pF and 0.5 pF. In

FIG. 27

, load impedances at frequencies of 0.5 to 3.0 GHz are illustrated, and load impedances at a frequency of 2.9 GHz of second harmonics are particularly indicated by black circular marks.

When the capacitance value C of the capacitor

5

and the impedance of the line

3

are changed, to change a resonance frequency, characteristics at frequencies which are not more than the resonance frequency are also changed, so that the load impedances at the frequencies which are not more than the resonance frequency are also changed.

When the capacitance value C of the capacitor

5

is 2.0 pF, the load impedance at the frequency of 2.9 GHz of the second harmonic is approximately zero, that is, the drain terminal of the FET

20

is substantially in a short-circuited state. It is found that the load impedance at the frequency of 2.9 GHz of the second harmonic is changed by changing the capacitance value C of the capacitor

5

to 1.5 pF, 1.0 pF, and 0.5 pF.

FIG. 28

is a waveform diagram showing a drain current in an AB-class operation of the FET

20

.

FIG. 28

illustrates a pseudo waveform obtained by subjecting the waveform of the drain current in the AB-class operation of the FET

20

to Fourier series expansion from the first harmonic to the sixth harmonic.

FIG. 29

is a diagram showing a load line in a case where a load impedance in the FET

20

at the second harmonics is zero (that is, in a short-circuited state), and

FIG. 30

is a diagram showing a load line in a case where a load impedance in the FET

20

at the second harmonics is not zero. In

FIGS. 29 and 30

, the horizontal axes indicates a drain voltage, and the vertical axes indicate a drain current.

FIG. 29

illustrates a case where the magnitude of a load impedance at a frequency other than the second harmonics is 0.415 and the angle thereof is 153 degrees, and the magnitude of a load impedance at the second harmonics is zero (a state A).

FIG. 30

illustrates a case where the magnitude of a load impedance at a frequency other than the second harmonics is 0.415 and the angle thereof is 153 degrees, and the magnitude of a load impedance at the second harmonics is 0.96 and the angle thereof is −143 degrees (a state B).

The integrated values over one period of the drain current and the drain voltage in

FIGS. 29 and 30

are respectively 1.12 J and 1.08 J. The integrated value represents energy to be a loss. The results indicate that a loss in the state B where no short-circuited state occurs with respect to the second harmonics is smaller than a loss in the state A where a short-circuited state occurs with respect to the second harmonics. Consequently, it is possible to achieve high efficiency.

The input/output characteristics of the FET

20

in the high-frequency circuit shown in

FIG. 26

have been then measured. In the measurement, third harmonics are not in a short-circuited state. A source and a load impedance have been changed such that adjacent channel leakage power characteristics(ACP characteristics) detuned by 50 kHz is −50 dBc and power-added efficiency is the maximum, to measure the input/output characteristics. The gate width of the FET

20

is 1.6 mm, and an idle current (a current in the no signal state) is 92 mA. The frequency of a fundamental wave is 1.45 GHz. As bias conditions, a drain bias is 3.5 V, and a gate bias is 0 V. The length L

a

of the line

1

is 8.9 mm, which is not more than one-fourth the length of the λ/4 line. The results of the measurement are shown in Table 1.

TABLE 1

Impedance of

fundamental

Impedance of

wave

second harmonics

Power-added

(magnitude,

(magnitude,

Pout/Pin

efficiency

state

angle [deg.])

angle [deg.])

[dBm/dBm]

[%]

a

0.38, 173

0.98, −177

23.6/6.5

42

b

0.42, 153

0.96, −143

23.7/4.8

50

c

0.44, 148

0.90, −71

23.4/5.0

46

d

0.47, 145

0.91, 13.5

23.0/4.8

42

In Table 1, a state a shows a case where the magnitude of the impedance at second harmonics is approximately 1.0, and the angle thereof is −180 degrees. That is, in the state a, the drain terminal of the FET

20

is in an almost short-circuited state. On the other hand, in a state b, a state c, and a state d, the drain terminal of the FET

20

is not in a short-circuited state with respect to the second harmonics.

From the results shown in Table 1, in the state b where the magnitude of the impedance of the second harmonics is 0.957 (≈0.96) and the angle thereof is −143 degrees, power-added efficiency is 50%, which is higher by 8% than that in the state a where a short-circuited state occurs with respect to the second harmonics.

It is possible to achieve high efficiency by thus setting the resonance frequencies of the line

3

and the capacitor

5

to frequencies higher than the frequency of the second harmonics. Further, the length of the line

1

is smaller than the length of the λ/4 line, so that it is possible to achieve miniaturization.

FIG. 31

is a circuit diagram showing still another example of a bias-applying circuit. A bias applying circuit

10

a

shown in

FIG. 31

comprises a third harmonic processing circuit

60

in addition to the bias applying circuit

10

shown in FIG.

26

. The third harmonic processing circuit

60

comprises a series connection between a line

61

and a capacitor

62

, and is connected between a node NB and a ground potential.

Also in the bias applying circuit

10

a

shown in

FIG. 31

, the resonance frequencies of the line

3

and the capacitor

5

are set to frequencies higher than the frequency of the second harmonic, thereby making it possible to achieve high efficiency as well as to suppress third harmonics by the third harmonic processing circuit

60

.

FIG. 32

is a diagram showing the relation between the capacitance values of the capacitors

4

and

5

and the lengths of the lines

1

,

2

and

3

in the distributed constant circuit in the embodiment shown in FIG.

1

. FIG.

32

(

a

) illustrates the distributed constant circuit in the embodiment shown in

FIG. 1

, and FIG.

32

(

b

) illustrates the results of calculation of the relation between the capacitance values of the capacitors

4

and

5

and the lengths of the lines

1

,

2

, and

3

.

In FIG.

32

(

b

), the horizontal axis indicates the capacitance value C of the capacitors

4

and

5

, the vertical axis indicates the length L

a

of the line

1

and the length L

b

of the lines

2

and

3

, a solid line indicates the relation between the capacitance value C of the capacitors

4

and

5

and the length L

a

of the line

1

, and a dotted line indicates the relation between the capacitance value C of the capacitors

4

and

5

and the length L

b

of the lines

2

and

3

.

As the lines

1

,

2

, and

3

, a microstrip line shown in FIG.

33

is used. The microstrip line shown in

FIG. 33

comprises a ceramic substrate

91

, a microstrip conductor

92

, and a ground conductor

93

. The dielectric constant ∈

r

of the ceramic substrate

91

is 9.8, and the thickness h thereof is 635 μm. The width w of the microstrip conductor

92

is 300 μm, and the thickness t thereof is 10 μm. The frequency f

1

of a fundamental wave is 950 MHz.

FIG.

32

(

b

) shows that as the capacitance value C of the capacitors

4

and

5

increases, the length L

a

of the line

1

and the length L

b

of the lines

2

and

3

decrease.

FIG. 34

is a circuit diagram of a distributed constant circuit in another embodiment of the present invention. The distributed constant circuit shown in

FIG. 34

functions as an inductor when particular conditions are satisfied.

In an example shown in FIG.

34

(

a

), a node NB is grounded through a line

501

, and is grounded through a capacitor

502

. Let λ be a wavelength, ω be an angular frequency, Z

a

be the characteristic impedance of a line

501

, L

a

be the length of the line

501

, and C be the capacitance value of the capacitor

502

, where L

a

<λ/4. An input impedance Z

in

is expressed by the following equation:

Z_{i n} = \frac{j Z_{a} \tan (\frac{2 π}{λ} L_{a})}{1 - ω {CZ}_{a} \tan (\frac{2 π}{λ} L_{a})}

If 1−ωCZ

a

tan[(2π/λ)L

a

]32 0, the input impedance Z

in

increases to infinity, and the node NB enters an open state. Further, if 1>ωCZ

a

tan[(2π/λ)L

a

], Z

in

=jX. X is a reactance, and X>0. Consequently, the distributed constant circuit shown in FIG.

34

(

a

) functions as an inductor.

In an example shown in FIG.

34

(

b

), a node NB is grounded through a line

501

, and is grounded through a capacitor 502 and an inductor component

503

. Let L be the inductance of the inductor component

503

, where L

a

<λ/4. In this case, an input impedance Z

in

is expressed by the following equation:

Z_{i n} = j \frac{(ω L - \frac{1}{ω C}) Z_{a} \tan (\frac{2 π}{λ} L_{a})}{(ω L - \frac{1}{ω C}) + Z_{a} \tan (\frac{2 π}{λ} L_{a})}

If 1/ωC=ωL+Z

a

tan[(2π/λ)L

a

], the input impedance Z

in

increases to infinity, and the node NB enters an open state. Further, if 1/ωC>ωL+Z

a

tan[(2π/λ)L

a

], Z

in

=jX (X>0). Consequently, the distributed constant circuit shown in FIG.

34

(

a

) functions as an inductor. The inductor component

503

shown in FIG.

34

(

b

) may be an inductor component appended to a chip capacitor.

With respect to a particular frequency satisfying ω L=1/ωC, the input impedance Z

in

becomes zero, and the node NB enters a short-circuited state to a ground potential.

Consequently, the distributed constant circuit shown in FIG.

34

(

b

) can enter an open state with respect to a fundamental wave or operate as an inductor, and can enter a short-circuited state with respect to a particular frequency. Utilization of this makes it possible to perform harmonic processing in a load.

In an example shown in FIG.

34

(

c

), a node NB is grounded through a line

501

, and is grounded through a capacitor

502

and a line

504

. Let Z

b

be the characteristic impedance of the line

504

, and L

b

be the length thereof, where L

a

<λ/4 and L

b

<λ/4. In this case, an input impedance Z

in

is expressed by the following equation:

Z_{i n} = j \frac{(Z_{b} \tan (\frac{2 π}{λ} L_{b}) - \frac{1}{ω C}) Z_{a} \tan (\frac{2 π}{λ} L_{a})}{Z_{b} \tan (\frac{2 π}{λ} L_{b}) - \frac{1}{ω C} + Z_{a} \tan (\frac{2 π}{λ} L_{a})}

If 1/ωC=Z

b

tan[(2π/λ)L

b

]+Z

a

tan[(2π/λ)L

a

], the input impedance Z

in

increases to infinity, and the node NB enters an open state. Further, if 1/ωC>Z

b

tan[(2π/λ)L

b

]+Z

a

tan[(2π/λ)L

a

], Z

in

=jX (X>0). Consequently, the distributed constant circuit shown in FIG.

34

(

c

) functions as an inductor.

With respect to a particular frequency satisfying 1/ωC=Z

b

tan[(2π/λ)L

b

], the input impedance Z

in

becomes zero, and the node NB enters a short-circuited state to a ground potential.

Consequently, the distributed constant circuit shown in FIG.

34

(

c

) can enter an open state with respect to a fundamental wave or operate as an inductor, and can enter a short-circuited state with respect to a particular frequency. Utilization of this makes it possible to perform harmonic processing in a load.

Consider a case where the same input impedance is obtained. In any of the examples shown in FIGS.

34

(

a

),

34

(

b

) and

34

(

c

), if the capacitance value C of the capacitor

502

is increased, the length L

a

of the line

501

is decreased.

FIG. 35

is a circuit diagram showing one example of an amplifier using the distributed constant circuit shown in FIG.

34

. The amplifier shown in

FIG. 35

comprises two FETs

61

and

62

, distributed constant circuits

60

a

and

60

b

, capacitors

63

,

64

,

65

,

66

,

67

, and

68

, resistors

69

and

70

, and lines

71

and

72

. A capacitor

502

in each of the distributed constant circuits

60

a

and

60

b

is a chip capacitor, and includes an inductor component of 0.9 nH. Consequently, the distributed constant circuits

60

a

and

60

b

actually have the arrangement shown in FIG.

34

(

b

).

The distributed constant circuit

60

a

functions as a parallel inductor, and constitutes a part of a matching circuit. A drain bias VDD

1

is applied to the drain of the FET

61

through the line

71

.

In the distributed constant circuit

60

b

, a line

501

is connected between a node NA and a node NB, the node NA is grounded through a capacitor

505

, and the node NB is connected to the drain of the FET

62

. Further, the node NB is grounded through the capacitor

502

. A drain bias VDD

2

is applied to the node NA.

The distributed constant circuit

60

b

functions as a parallel inductor and functions as a high-frequency processing circuit, and constitutes a drain bias circuit and constitutes a part of a matching circuit. The input impedance Z

in

of the distributed constant circuit

60

b

is approximately 40 Ω. Since a load impedance on the side of the FET

62

is as low as several ohms, an output signal of the FET

62

does not leak toward a power supply for supplying the drain bias VDD

2

.

In the amplifier shown in

FIG. 35

, the short line

501

can constitute an inductor by using the distributed constant circuits

60

a

and

60

b

. Consequently, the amplifier can be miniaturized.

Consider a case where an inductor of approximately 12 nH (11.8 nH) having its one end grounded at a frequency of 950 MHz is formed using the microstrip line shown in FIG.

33

.

When only the microstrip line is used, the length of the line is 16.3 mm. Conversely, when the distributed constant circuit shown in FIG.

34

(

b

) is used, the length L

a

of the line

501

is 8.36 mm. The capacitance value C of the capacitor

502

is 3 pF, and the inductance L of the inductor component

503

is 0.9 nH.

At this time, the input impedance Z

in

becomes zero by resonance between the capacitor

502

and the inductor component

503

at a frequency of 3.06 GHz, so that the node NB enters a short-circuited state to a ground potential.

The distributed constant circuit shown in

FIG. 34

is utilized as an inductor, thereby making it possible to miniaturize the circuit.

FIG. 36

is a diagram showing the results of calculation of the relation between the length L

a

of the line

501

and the input impedance Z

in

in the distributed constant circuit shown in FIG.

34

(

b

). In

FIG. 36

, the horizontal axis indicates the length L

a

of the line

501

, and the vertical axis indicates the reactance X of the input impedance Z

in

.

The dielectric constant ∈

r

of the ceramic substrate

91

is 9.8, and the thickness h thereof is 635 μm. The width w of the microstrip conductor

92

is 300 μm, and the thickness t thereof is 10 μm. The frequency is 950 MHz. The characteristic impedance Z

a

of the line

501

is 66.0 Ω. The capacitance value C of the capacitor

502

is 4 pF, and the inductance L of the inductor component

503

is 0.9 nH.

As shown in

FIG. 36

, in a range in which the length L

a

of the line

501

is more than zero and less than 10 mm, the distributed constant circuit functions as an inductor. When the length L

a

of the line

501

is 10 mm, resonance occurs, so that the input impedance Z

in

of the distributed constant circuit increases to infinity, and the node NB enters an open state.

When the circuit is constructed using a chip part, a chip inductor is higher in cost than a chip capacitor. In an MMIC (Monolithic Microwave Integrated Circuit), a spiral inductor has a large area on a chip. When a parallel inductor is constituted by a chip inductor or a spiral inductor, therefore, the cost thereof is increased and the area thereof is increased.

On the other hand, when the distributed constant circuit shown in

FIG. 34

is used as an inductor, the length L

a

of the line

501

can be decreased by increasing the capacitance value C of the capacitor

502

. Consequently, it is possible to lower the cost of the circuit and miniaturize the circuit.

The distributed constant circuit shown in

FIG. 34

can be used for a bias circuit, a matching circuit, a filter, and so forth.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Number	Date	Country
9-240074	Sep 1997	JP
10-032498	Feb 1998	JP
10-234649	Aug 1998	JP

Number	Name	Date	Kind
5202649	Kashiwa	Apr 1993	A
5272456	Ishida	Dec 1993	A
5525942	Horii et al.	Jun 1996	A
5592122	Masahiro et al.	Jan 1997	A
5656874	Kato et al.	Aug 1997	A
5697087	Miya et al.	Dec 1997	A
6064281	Sheen	May 2000	A

Distributed constant circuit in an amplifier

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (3)

CROSS REFERENCE TO RELATED APPLICATION

US Referenced Citations (7)

Non-Patent Literature Citations (7)

Entry
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S. Makioka et al., “A Miniaturized GaAs Power Amplifier for 1.5 GHz Digital Cellular Phones”, IEEE 1996 Microwave and Millimeter-Wave Monolithic Circuits Symposium pp. 13-16 (1996).
Seiichi Banba et al., “Small-Sized MMIC Amplifiers Using Thin Dielectric Layers” IEEE Transactions On Microwave Theory And Techniques, vol. 43, No. 3 pp. 485-492, (Mar. 1995).
Kazuhiko Honjo, “Microwave Nonlinear Circuit” MWE '95 Microwave Workshop Digest pp. 65-74 (1995).
Kazuhisa Yamauchi et al., “A Novel Series Diode Linearizer for Mobile Radio Power Amplifiers”, 1996 IEEE MTT-S Digest pp. 831-834 (1996).