The present invention generally relates to graphics processing circuitry and, more particularly, to dividing graphics processing operations among multiple pipelines.
Computer graphics systems, set top box systems or other graphics processing systems typically include a host processor, graphics (including video) processing circuitry, memory (e.g. frame buffer), and one or more display devices. The host processor may have a graphics application running thereon, which provides vertex data for a primitive (e.g. triangle) to be rendered on the one or more display devices to the graphics processing circuitry. The display device, for example, a CRT display includes a plurality of scan lines comprised of a series of pixels. When appearance attributes (e.g. color, brightness, texture) are applied to the pixels, an object or scene is presented on the display device. The graphics processing circuitry receives the vertex data and generates pixel data including the appearance attributes which may be presented on the display device according to a particular protocol. The pixel data is typically stored in the frame buffer in a manner that corresponds to the pixels location on the display device.
The amount of time taken for an entire frame of information to be calculated and provided to the frame buffer becomes a bottleneck in graphics systems as the calculations associated with the graphics become more complicated. Contributing to the increased complexity of the graphics calculation is the increased need for higher resolution video, as well as the need for more complicated video, such as 3-D video. The video image observed by the human eye becomes distorted or choppy when the amount of time taken to render an entire frame of video exceeds the amount of time in which the display device must be refreshed with a new graphic or frame in order to avoid perception by the human eye. To decrease processing time, graphics processing systems typically divide primitive processing among several graphics processing circuits where, for example, one graphics processing circuit is responsible for one vertical strip (e.g. 13) of the frame while another graphics processing circuit is responsible for another vertical strip (e.g. 14) of the frame. In this manner, the pixel data is provided to the frame buffer within the required refresh time.
Load balancing is a significant drawback associated with the partitioning systems as described above. Load balancing problems occur, for example, when all of the primitives 20-23 of a particular object or scene are located in one strip (e.g. strip 13) as illustrated in
Changing the width of the strips has been employed to counter the system performance problems. However, when the width of a strip is increased, the load balancing problem is enhanced as more primitives are located within a single strip; thereby, increasing the processing required of the graphics processing circuit responsible for that strip, while the remaining graphics processing circuits remain idle. When the width of the strip is decreased (e.g. four bits to two bits), cache (e.g. texture cache) efficiency is decreased as the number of cache lines employed in transferring data is reduced in proportion to the decreased width of the strip. In either case, graphics processing system performance is still decreased due to the idle graphics processing circuits.
Frame based subdivision has been used to overcome the performance problems associated with conventional partitioning systems. In frame based subdivision, each graphics processor is responsible for processing an entire frame, not strips within the same frame. The graphics processors then alternate frames. However, frame subdivision introduces one or more frames of latency between the user and the screen, which is unacceptable in real-time interactive environments, for example, providing graphics for a flight simulator application.
The present invention and the related advantages and benefits provided thereby, will be best appreciated and understood upon review of the following detailed description of a preferred embodiment, taken in conjunction with the following drawings, where like numerals represent like elements, in which:
A multi-pipeline graphics processing circuit includes at least two pipelines operative to process data in a corresponding tile of a repeating tile pattern, a respective one of the at least two pipelines is operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. The multi-pipeline graphics processing circuit may be coupled to a frame buffer that is subdivided into a replicating pattern of square regions (e.g. tiles), where each region is processed by a corresponding one of the at least two pipelines such that load balancing and texture cache utilization is enhanced.
A multi-pipeline graphics processing method includes receiving vertex data for a primitive to be rendered, generating pixel data in response to the vertex data, determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions, and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines. An exemplary embodiment of the present invention will now be described with reference to
Graphics data 31, for example, vertex data of a primitive (e.g. triangle) 80 (
The graphics processing circuit 34 includes a first graphics pipeline 101 operative to process graphics data in a first set of tiles as discussed in greater detail below. The first pipeline 101 includes front end circuitry 35, a scan converter 37, and back end circuitry 39. The graphics processing circuit 34 also includes a second graphics pipeline 102, operative to process graphics data in a second set of tiles as discussed in greater detail below. The first graphics pipeline 101 and the second graphics pipeline 102 operate independently of one another. The second graphics pipeline 102 includes the front end circuitry 35, a scan converter 40, and back end circuitry 42. Thus, the graphics processing circuit 34 of the present invention is configured as a multi-pipeline circuit, where the back end circuitry 39 of the first graphics pipeline 101 and the back end circuitry 42 of the second graphics pipeline 102 share the front end circuitry 35, in that the first and second graphics pipelines 101 and 102 receive the same pixel data 36 provided by the front end circuitry 35. Alternatively, the back end circuitry 39 of the first graphics pipeline 101 and the back end circuitry 42 of the second pipeline 102 may be coupled to separate front end circuits. Additionally, it will be appreciated that a single graphics processing circuit can be configured in similar fashion to include more than two graphics pipelines. The illustrated graphics processing circuit 34 has the first and second pipelines 101-102 present on the same chip. However, in alternate embodiments, the first and second graphics pipelines 101-102 may be present on multiple chips interconnected by suitable communication circuitry or a communication path, for example, a synchronization signal or data bus interconnecting the respective memory controllers.
The front end circuitry 35 may include, for example, a vertex shader, set up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data 31 and generate pixel data 36 to be further processed by the back end circuitry 39 and 42, respectively. The front end circuitry 35 generates the pixel data 36 by performing, for example, clipping, lighting, spatial transformations, matrix operations and rasterizing operations on the primitive data 31. The pixel data 36 is then transmitted to the respective scan converters 37 and 40 of the two graphics pipelines 101-102.
The scan converter 37 of the first graphics pipeline 101 receives the pixel data 36 and sequentially provides the position (e.g. x, y) coordinates 60 in screen space of the pixels to be processed by the back end circuitry 39 by determining or identifying those pixels of the primitive, for example, the pixels within portions 81-82 of the triangle 80 (
Back end circuitry 39 may include, for example, pixel shaders, blending circuits, z-buffers or any other circuitry for performing pixel appearance attribute operations (e.g. color, texture blending, z-buffering) on those pixels located, for example, in tiles 72, 75 (
The scan converter 40 of the second graphics pipeline 102, receives the pixel data 36 and sequentially provides position (e.g. x, y) coordinates 61 in screen space of the pixels to be processed by the back end circuitry 42 by determining those pixels of the primitive, for example, the pixels within portions 83-84 of the triangle 80 (
Back end circuitry 42 may include, for example, pixel shaders, blending circuits, z-buffers or any suitable circuitry for performing pixel appearance attribute operations on those pixels located, for example, in tiles 73 and 74 (
The memory controller 46 is operative to transmit and receive the processed pixel data 43-44 from the back end circuitry 39 and 42; transmit and retrieve pixel data 49 from the graphics memory 48; and in a single circuit implementation, transmit pixel data 50 for presentation on a suitable display 51. The display 51 may be a monitor, a CRT, a high definition television (HDTV) or any other device or combination thereof.
Graphics memory 48 may include, for example, a frame buffer that also stores one or more texture maps. Referring to
By configuring the frame buffer 48 according to the present invention, as the primitive data 31 is typically written in strips, the tiles (e.g. 72 and 75) being processed by the first graphics pipeline 101 and the tiles (e.g. 73 and 74) being processed by the second graphics pipeline 102 will be substantially equal in size, notwithstanding the primitive 80 orientation. Thus, the amount of processing performed by the first graphics pipeline 101 and the second graphics pipeline 102, respectively, are substantially equal; thereby, effectively eliminating the load balance problems exhibited by conventional techniques.
Referring briefly to
Returning to
The front end circuitry 135 may include, for example, a vertex shader, set up circuitry, rasterizer or other suitable circuitry operative to receive the primitive data 31 from the AGP 32 and generate pixel data 136 to be processed by the third graphics pipeline 201 and fourth graphics pipeline 202, respectively. The front end circuitry 135 generates the pixel data 136 by performing, for example, clipping, lighting, spatial transformations, matrix operations, rasterization or any suitable primitive operations or combination thereof on the primitive data 31. The pixel data 136 is then transmitted to the respective scan converters 137 and 140 of the two graphics pipelines 201-202.
The scan converter 137 of the third graphics pipeline 201 receives the pixel data 136 and sequentially provides the position (e.g. x, y) coordinates 160 in screen space of the pixels to be processed by the back end circuitry 139, based on the tile identification data present on pixel identification line 138. In corresponding fashion, scan converter 140 of the fourth graphics pipeline 202 receives the pixel data 136 and sequentially provides the position (e.g. x, y) coordinates 161 in screen space of the pixels to be processed by the back end circuitry 143, based on the tile identification data present on pixel identification line 141.
Referring to
As illustrated, the super-tile pattern 68 is formed of a horizontally and vertically repeating pattern of regions or tiles 92-99, where each tile is a 16×16 pixel array. With this frame buffer configuration, as the primitive data 31 is typically written in strips, at least one tile (e.g. 92) being processed by the third graphics pipeline 201 and at least one tile (e.g. 93) being processed by the fourth graphics pipeline 202 will be intersected or contain at least a portion of the primitive data 31, notwithstanding the primitive orientation; thereby achieving substantially equal load balancing between the pipelines.
Thus, in the multi-processor implementation, each of the graphics pipelines is responsible for processing 1/(M×N) of the tiles present in the partitioned graphics memory 68, where M represents the number of pipelines per circuit and N represents the number of graphics processing circuits being used. Thus, in an embodiment where graphics processing circuit 34 and graphics processing circuit 54 are combined, for example, through AGP 32 (
In step 104, the pixels within a set of tiles of the repeating tile pattern to be processed by a corresponding one of the at least two graphics pipelines in response to the pixel data is determined. This is accomplished, for example, in step 105 by the scan converter 37 determining which of tiles (e.g. 72 and 75) of the repeating tile pattern are to be processed by the back end circuitry 39 based on the tile identification data present on the pixel identification line 38. Next, in step 106, the scan converter 37 provides the position coordinates 60 of the pixels within portions 81-82 of the triangle 80 that intersect the tiles (e.g. 72 and 75) to the back end circuitry 39.
In step 108, pixel operations are performed on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines is performed. This is accomplished, for example, by the back end circuitry 39 performing color, shading, blending, texturing and/or z-buffering operations on the pixels within the portions (e.g. 81-82) of the tiles (e.g. 72 and 75) they are responsible for.
In step 109, a determination is made as to whether the processing is complete. If the processing is complete, the process proceeds to step 100 where vertex data for a new primitive is received. Otherwise, the process ends. In the multi-processor implementation, graphics processing circuit 54 performs substantially the same operations as discussed above, in conjunction with graphics processing circuit 34.
As noted above, a rasterizer setup unit manages the distribution of polygons to the different rasterizer pipelines within a chip. The design divides the screen into multiple square tiles. Each pipeline is responsible for a subset of the tiles. In our design, the tile sizes are 8×8 pixels, 16×16 pixels (default) or 32×32 pixels. However, any number of square pixels or even non-square tiles could be done. It will be recognized that the number of pixels in the tiles be a common divisor of the number of pixels on the screen, in both X and Y directions.
Vertices are given by the application currently executing on the host. The vertices are converted from object space three-dimensional homogeneous coordinate system to a screen based coordinate system. This conversion can be done on the host processor or in the front end section of the graphics chip (i.e. vertex transformation). The screen based coordinate system has at least X and Y coordinates for each vertex.
As shown in
The bounding boxes' four corners are mapped to the tile pattern, simply by discarding the lower bits of X & Y. The four corners map to the same or different tiles. If they all map to the same tile, then only the pipeline that is associated with that tile receives the polygon. If it maps to only tiles that are associated with only one pipeline, then again only that pipeline receives the polygon. If it maps to tiles that are associated with multiple pipelines, then the entire polygon is sent to all pipelines. In one implementation, the polygon is broadcast to all pipelines, masking the pipelines that should not receive it. Consequently, polygons can be sent to only one pipe or up to all the pipes, depending on the coverage of the tiles by the polygon.
For super tiling when using multiple graphics chips, the rasterizer setup unit manages the distribution of polygons to different graphics chips. The super tiles, which are a square assembly of pixels, are used to perform load balancing between each processor. Basically, each processor is responsible for generating all of the pixels in its subset of super tiles. The tiles are distributed evenly across all processors, in a checkerboard pattern. The tile size is variable, but one implementation may be 32×32 pixels, or 2×2 tiles. This amount can be changed through programming registers. Super tiles do not have to be of a size which is a common divisor of the screen resolution, but it's more efficient if it is. The number of chips in use should be a power of two.
In operation, an application generates vertex data, which assembles into polygons (i.e. 2 vertices for a line, 3 for a triangle). Each vertex's homogeneous object space coordinate (generated by the application) is transformed into screen space coordinates by either the host or the front end of the graphics chip (transform unit or vertex processor). The screen space coordinates hold X, Y coordinates (in screen pixels) for each of the vertices. The polygons coming from an application are all broadcast to all chips. Each chip processes the vertices as needed to generate the same X, Y coordinates for all vertices. Then, each chip creates a bounding box around the polygon as shown in
In this way, triangle setup performance does not scale with each processor (since all polygons go through all setup units), but fill rate (defined as the number of pixels output total) does scale with each processor added.
The above detailed description of the invention and the examples described therein have been provided for the purposes of illustration and description. Although an exemplary embodiment of the present invention has been described in detail herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to the precise embodiment disclosed, and that various changes and modifications to the invention are possible in light of the above teaching. Accordingly, the scope of the present invention is to be defined by the claims appended hereto.
This application claims the benefit of U.S. Provisional Application Ser. No. 60/429,641 filed Nov. 27, 2002, entitled “Dividing Work Among Multiple Graphics Pipelines Using a Super-Tiling Technique”, having as inventors Mark M. Leather and Eric Demers, and owned by instant assignee. This is a related application to a co-pending application entitled “Parallel Pipeline Graphics System”, having Ser. No. 10/724,384, having Leather et al. as the inventors, filed on Nov. 26, 2003, owned by the same assignee and hereby incorporated by reference in its entirety.
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