DMA Address Translation in an IOMMU

Abstract

In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description makes reference to the accompanying drawings, which are now briefly described.

FIG. 1 is a block diagram of a high level view of one embodiment of a computer system.

FIG. 2 is a block digram of a more detailed embodiment of a computer system.

FIG. 3 is a block diagram illustrating a high level structure of one embodiment of the I/O translation tables shown in FIG. 1.

FIG. 4 is a block diagram of one embodiment of a device table entry for a device table shown in FIG. 3.

FIG. 5 is a block diagram of one embodiment of a page table entry for an I/O page table shown in FIG. 3.

FIG. 6 is a block diagram of one embodiment of a memory archetype field shown in FIG. 5

FIG. 7 is a block diagram of a second embodiment of a memory archetype field shown in FIG. 5 and a corresponding table.

FIG. 8 is a block diagram illustrating one embodiment of sharing I/O and CPU page table entries.

FIG. 9 is a block diagram illustrating one embodiment of an I/O page table entry and a CPU page table entry.

FIG. 10 is a flowchart illustrating one embodiment of a method of translating an I/O device-generated request.

Claims

1. An input/output (FO) memory management unit (IOMMU) comprising: at least one memory configured to store translation data; andcontrol logic coupled to the memory and configured to translate an PO device-generated memory request using the translation data, and wherein the translation data corresponds to: (i) one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request; and (ii) one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.

2. The IOMMU as recited in claim 1 wherein the device table entry for the given request further comprises a second pointer to an interrupt remapping table that stores data for remapping interrupts source by the I/O device.

3. The IOMMU as recited in claim 2 wherein the device table entry further comprises one or more control fields indicating how specific interrupts are to be handled.

4. The IOMMU as recited in claim 1 wherein the device table entry further comprises a domain identifier, and wherein two or more I/O devices are grouped into one group for accessing the I/O page tables by assigning the same domain identifier to the device table entries for the two or more PO devices.

5. The IOMMU as recited in claim 4 wherein two or more I/O devices are separated and use separate I/O translation data structures if the domain identifiers in the devices' device table entries differ.

6. The IOMMU as recited in claim 1 wherein the one or more I/O page tables are structured hierarchically, and wherein each level is indexed by different subsets of virtual address bits from the I/O device-generated memory request, and wherein each I/O page table entry includes a next level field identifying the next level in the hierarchy, wherein one or more levels in the hierarchy are shippable via encodings of the next level field.

7. A system comprising: a memory system storing a device table and one or more input/output (I/O) page tables during use;a least one I/O device configured to generate a memory request;an I/O memory management unit (IOMMU) coupled to the I/O device and to the memory system, wherein the IOMMU is configured to translate the memory request using translation data, and wherein the translation data corresponds to: (i) one or more device table entries in the device table, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device; and (ii) one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.

8. The system as recited in claim 7 wherein the device table entry for the given request further comprises a second pointer to an interrupt remapping table that stores data for remapping interrupts source by the I/O device.

9. The system as recited in claim 8 wherein the device table entry further comprises one or more control fields indicating how specific interrupts are to be handled.

10. The system as recited in claim 7 wherein the device table entry further comprises a domain identifier, and wherein two or more I/O devices are grouped into one group for accessing the I/O page tables by assigning the same domain identifier to the device table entries for the two or more I/O devices.

11. The system as recited in claim 10 wherein two or more I/O devices are separated and use separate I/O translation data structures if the domain identifiers in the devices' device table entries differ.

12. The system as recited in claim 7 wherein the one or more I/O page tables are structured hierarchically, and wherein each level is indexed by different subsets of virtual address bits from the I/O device-generated memory request, and wherein each I/O page table entry includes a next level field identifying the next level in the hierarchy, wherein one or more levels in the hierarchy are skippable via encodings of the next level field.

13. The system as recited in claim 7 further comprising a processor coupled to the memory system, wherein the memory system is configured to store a set of processor page tables to translate memory requests issued by the processor.

14. The system as recited in claim 13 wherein one or more page tables of the set of processor page tables are shared with the I/O page tables.

15. The system as recited in claim 14 wherein fields used by the processor but not the IOMMU are defined as not used in the I/O page table definition.

16. The system as recited in claim 15 wherein fields used by the IOMMU but not the processor are defined as not used in the processor page table definition.

17. A method comprising: receiving an input/output (I/O) device-generated memory request in an IOMMU;determining a device table entry corresponding to the memory request by the IOMMU;determining a set of I/O page tables corresponding to the memory request responsive to the device table entry; andtranslating the memory request using translation data corresponding to the device table entry and the set of I/O page tables.

18. The method as recited in claim 17 further comprising, if a device table entry does not exist for the memory request, causing a fault.

19. The method as recited in claim 17 further comprising, if the translating fails, causing a fault.