Claims
- 1. A method of direct memory access (DMA), comprising:
receiving a first notification at a DMA engine that a first list of descriptors has been prepared, each of the descriptors in the list comprising an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link; reading and executing the descriptors in the first list using the DMA engine; receiving a second notification at the DMA engine that a second list of the descriptors has been prepared; rereading at least a part of the final descriptor in the first list to determine a changed value of the link, indicating to the DMA engine a first descriptor in the second list; and reading and executing the descriptors in the second list using the DMA engine responsive to the changed value of the link.
- 2. A method according to claim 1, wherein receiving the first and second notifications comprises receiving the notifications that the first and second lists have been stored at respective addresses in a memory, and wherein reading the descriptors comprises reading the descriptors from the memory.
- 3. A method according to claim 2, wherein executing the descriptors comprises marking each of the descriptors as having been executed after executing each of the descriptors, and wherein marking each of the descriptors comprises marking the final descriptor in a manner that is distinctive from the marking of the other descriptors.
- 4. A method according to claim 3, and comprising reclaiming the addresses in the memory responsive to the marking of each of the descriptors, so as to permit reallocation of the addresses, while preserving the final descriptor from being reclaimed responsive to its distinctive marking.
- 5. A method according to claim 2, wherein the link in each of the descriptors comprises a pointer to the address of the succeeding one of the descriptors, and wherein receiving the second notification comprises receiving the second notification after the value of the null link has been changed to comprise a pointer to the first descriptor in the second list.
- 6. A method according to claim 1, wherein receiving the second notification comprises receiving the second notification while the DMA engine is executing the descriptors in the first list, and wherein reading and executing the descriptors in the second list comprises reading and executing the descriptors responsive to the notification after the DMA engine has finished executing the descriptors in the first list.
- 7. A method according to claim 6, wherein receiving the first notification comprises receiving a first data input to a command register of the DMA engine and setting a flag in response to the first data input, responsive to which flag the DMA engine reads and executes the descriptors, and wherein receiving the second notification comprises leaving the flag set as long as the DMA engine is executing the descriptors.
- 8. A method according to claim 1, wherein receiving the second notification comprises receiving the second notification after the DMA engine has finished executing the descriptors in the first list, and wherein rereading at least the part of the final descriptor comprises rereading at least the part of the final descriptor after the final descriptor has been executed.
- 9. A method according to claim 1, wherein reading and executing the descriptors comprises at least one of conveying data from a data source to a memory and conveying data from a memory to a data target.
- 10. A method according to claim 9, wherein receiving the first and second notifications comprises receiving the notifications submitted by a program running on a central processing unit (CPU), which has prepared the lists of descriptors, while conveying the data comprises transmitting the data using the DMA engine substantially without intervention of the CPU in conveying the data.
- 11. A method according to claim 10, wherein receiving the second notification comprises receiving the notifications submitted by the program substantially irrespective of an execution state of the DMA engine.
- 12. A method of direct memory access (DMA), comprising:
preparing a first list of descriptors for execution by a DMA engine, each of the descriptors in the list comprising an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link; submitting a first notification to the DMA engine that the first list has been prepared, so that the DMA engine will execute the descriptors in the first list responsive to the first notification; preparing a second list of the descriptors for execution by the DMA engine; modifying the link in the final descriptor in the first list so as to indicate a first descriptor in the second list; submitting a second notification to the DMA engine that the second list has been prepared, so that the DMA engine will execute the descriptors in the second list responsive to the second notification, substantially irrespective of an execution state of the DMA engine when it receives the second notification.
- 13. A method according to claim 12, wherein submitting the second notification comprises causing the DMA engine to reread at least a portion of the final descriptor in the first list so as to locate thereby the first descriptor in the second list.
- 14. A method according to claim 12, wherein preparing the first and second lists comprises storing the lists at respective addresses in a memory, and wherein submitting the first and second notifications comprises notifying the DMA engine that it should read the descriptors from the memory.
- 15. A method according to claim 14, wherein the link in each of the descriptors comprises a pointer to the address of the succeeding one of the descriptors, and wherein modifying the link comprises changing a value of the null link so as to comprise a pointer to the first descriptor in the second list.
- 16. A method according to claim 12, wherein submitting the second notification comprises submitting the second notification while the DMA engine is executing the descriptors in the first list.
- 17. A method according to claim 12, wherein submitting the second notification comprises submitting the second notification after the DMA engine has finished executing the descriptors in the first list.
- 18. A method according to claim 12, wherein the descriptors comprises at least one of an instruction to the DMA engine to convey data from a data source to a memory and an instruction to the DMA engine to convey data from a memory to a data target.
- 19. A method according to claim 18, wherein preparing the first and second lists and submitting the first and second notifications comprises preparing the lists and submitting the notifications by means of a program running on a central processing unit (CPU), and wherein the DMA engine conveys the data substantially without intervention of the CPU in conveying the data.
- 20. Apparatus for direct memory access (DMA), comprising a DMA engine, which is coupled to receive a first notification that a first list of descriptors has been prepared, each of the descriptors in the list comprising an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link, and which is adapted to read and execute the descriptors in the first list, and which is further coupled to receive a second notification a second list of the descriptors has been prepared, and which is further adapted to reread at least a part of the final descriptor in the first list to determine a changed value of the link, indicating a first descriptor in the second list, and to read and execute the descriptors in the second list using the DMA engine responsive to the changed value of the link.
- 21. Apparatus according to claim 20, and comprising a memory, which is coupled to store the first and second lists, wherein the first and second notifications comprise notifications that the first and second lists have been stored at respective addresses in a memory, and wherein the DMA engine is coupled to read the descriptors from the memory.
- 22. Apparatus according to claim 21, wherein the DMA engine is adapted to mark each of the descriptors with an indication that the descriptor has been executed, and to mark the final descriptor in a manner that is distinctive from the other descriptors.
- 23. Apparatus according to claim 22, and comprising a processor, which is coupled to reclaim the addresses of the descriptors in the memory responsive to the indication that the descriptors have been executed, so as to permit reallocation of the addresses, while preserving the final descriptor from being reclaimed responsive to its distinctive indication.
- 24. Apparatus according to claim 21, wherein the link in each of the descriptors comprises a pointer to the address of the succeeding one of the descriptors, and wherein the changed value of the link in the final descriptor comprises a pointer to the first descriptor in the second list.
- 25. Apparatus according to claim 20, wherein the DMA engine is adapted to receive the second notification while the DMA engine is executing the descriptors in the first list, and to read and execute the descriptors responsive to the notification after the DMA engine has finished executing the descriptors in the first list.
- 26. Apparatus according to claim 25, wherein the DMA engine comprises a command register and flag, wherein the first notification comprises a first data input to the command register, and wherein the second notification comprises a second data input to the command register, and wherein the DMA engine is adapted to set the flag in response to the first data input, and to read and execute the descriptors responsive to the flag being set, leaving the flag set as long as the DMA engine is executing the descriptors.
- 27. Apparatus according to claim 20, wherein the DMA engine is adapted to receive the second notification after the DMA engine has finished executing the descriptors in the first list, and to reread at least the part of the final descriptor in the first list after it has executed the final descriptor.
- 28. Apparatus according to claim 20, wherein in accordance with the descriptors, the DMA engine performs at least one of conveying data from a data source to a memory and conveying data from a memory to a data target.
- 29. Apparatus according to claim 28, and comprising a central processing unit (CPU), which is programmed to prepare the first and second lists of descriptors and to submit the first and second notifications, responsive to which the DMA engine is adapted to convey the data substantially without intervention of the CPU in conveying the data.
- 30. Apparatus according to claim 29, wherein the CPU is programmed to submit the first and second notifications substantially irrespective of an execution state of the DMA engine.
- 31. Apparatus for direct memory access (DMA), comprising:
a DMA engine, adapted to transfer data between a data target and a data source responsive to descriptors submitted thereto; and a descriptor processor, adapted to prepare a first list of the descriptors for execution by the DMA engine, each of the descriptors in the list comprising an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link, and coupled to submit a first notification to the DMA engine that the first list has been prepared, so that the DMA engine will execute the descriptors in the first list responsive to the first notification, and which is further adapted to prepare a second list of the descriptors for execution by the DMA engine and to modify the link in the final descriptor in the first list so as to indicate a first descriptor in the second list, and which is further coupled to submit a second notification to the DMA engine that the second list has been prepared, causing the DMA engine to execute the descriptors in the second list responsive to the second notification, substantially irrespective of an execution state of the DMA engine when it receives the second notification.
- 32. Apparatus according to claim 31, wherein responsive to the second notification the DMA engine is operative to reread at least a portion of the final descriptor in the first list so as to locate thereby the first descriptor in the second list.
- 33. Apparatus according to claim 31, and comprising a memory, wherein the processor is coupled to store the lists at respective addresses in the memory, and to notify the DMA engine that it should read the descriptors from the memory.
- 34. Apparatus according to claim 33, wherein the link in each of the descriptors comprises a pointer to the address of the succeeding one of the descriptors, and wherein the processor is adapted to change a value of the null link in the final descriptor in the first list so as to comprise a pointer to the first descriptor in the second list.
- 35. Apparatus according to claim 31, wherein the processor is adapted to submit the second notification, and the DMA engine is capable of receiving the second notification, while the DMA engine is executing the descriptors in the first list.
- 36. Apparatus according to claim 31, wherein the processor is adapted to submit the second notification, and the DMA engine is capable of receiving the second notification, after the DMA engine has finished executing the descriptors in the first list.
- 37. Apparatus according to claim 31, wherein the DMA engine is adapted to transfer the data substantially without intervention of the processor in transferring the data.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Patent Application No. 60/209,163, filed Jun. 2, 2000, which is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60209163 |
Jun 2000 |
US |