Patent Application
20240186956
The present disclosure relates to a Doherty amplifier circuit.
As high-efficiency power amplifier circuits, Doherty amplifier circuits have been known. Typically, a Doherty amplifier circuit is configured such that a carrier amplifier that operates regardless of the power level of an input signal and a peak amplifier that is turned off when the power level of an input signal is small and is turned on when the power level of an input signal is large are connected in parallel. With this configuration, when the power level of a high frequency input signal is large, the carrier amplifier operates while maintaining saturation at the saturated output power level. Thus, the Doherty amplifier circuit can improve efficiency compared to normal power amplifier circuits.
Techniques for controlling the bias of a peak amplifier are described in Patent Documents 1 to 3 described below.
The technique described in Patent Document 1 is detecting saturation of a carrier amplifier by using a bias circuit for the carrier amplifier and controlling a bias circuit for a peak amplifier in accordance with a detection signal.
The technique described in Patent Document 2 is detecting saturation of a carrier amplifier on the basis of an output signal of the carrier amplifier and controlling a bias circuit for a peak amplifier in accordance with a detection signal.
The technique described in Patent Document 3 is controlling a bias circuit for a peak amplifier in accordance with the level of a high frequency input signal input to a Doherty amplifier circuit or the level of a high frequency input signal input to a carrier amplifier.
In the techniques described in Patent Documents 1 and 2, it takes about several tens of nanoseconds for a circuit that detects saturation of a carrier amplifier to respond. Thus, inconvenience described below may occur. For example, in the case where a high frequency input signal with a momentary (much shorter than several tens of nanoseconds) increase in power is input to a Doherty amplifier circuit, a time during which the carrier amplifier saturates may occur during the duration of several tens of nanoseconds from the start of saturation of the carrier amplifier to a change of a bias point of the peak amplifier. Thus, the quality of a high frequency output signal of the Doherty amplifier circuit cannot always be maintained high. Furthermore, in the case where the Doherty amplifier circuit is applied to a communication apparatus, the quality of communication cannot always be maintained high.
In the technique described in Patent Document 3, although operation is performed in accordance with the level of a high frequency input signal, since the level of the high frequency input signal is detected by the bias circuit, the response speed is basically considered to be low. Thus, the quality of a high frequency output signal of the Doherty amplifier circuit cannot always be maintained high.
The present disclosure suppresses a decrease in the quality of a high frequency output signal.
A Doherty amplifier circuit according to an aspect of the present disclosure includes a carrier amplifier that amplifies an input high frequency signal, a peak amplifier that amplifies an input high frequency signal, a first bias circuit that applies a bias to the carrier amplifier, a second bias circuit that applies a bias to the peak amplifier, and a control circuit that controls the second bias circuit on the basis of an input high frequency signal and a signal indicating a drive level of the carrier amplifier.
According to the present disclosure, a decrease in the quality of a high frequency output signal can be suppressed.
Hereinafter, Doherty amplifier circuits according to embodiments of the present disclosure will be described in detail with reference to drawings. The embodiments are not intended to limit the present disclosure. Each of the embodiments is illustrative and, obviously, components illustrated in different embodiments can be partially replaced or combined. In second and subsequent embodiments, description of matters common to a first embodiment will be omitted, and only different points will be described. In particular, similar operational effects obtained by similar configurations will not be repeatedly described in each embodiment.
Each of the bias circuits 14 and 15 corresponds to an example of a “first bias circuit” according to the present disclosure. Each of the bias circuits 18 and 19 corresponds to a “second bias circuit” according to the present disclosure.
The number of stages of the Doherty amplifier circuit 10 is two. However, the present disclosure is not limited to this example. The number of stages of the Doherty amplifier circuit 10 may be one or three or more.
The bias circuit 3 applies a bias to the amplifier 2. The amplifier 2 outputs a high frequency signal RF1 obtained by amplifying a high frequency signal RFin to the 90-degree hybrid circuit 11. The 90-degree hybrid circuit 11 divides the high frequency signal RF1 into high frequency signals RF2 and RF5 whose phases are different by approximately 90 degrees, outputs the high frequency signal RF2 to the carrier amplifier 12, and outputs the high frequency signal RF5 to the peak amplifier 16. “Approximately 90 degrees” not only represents a phase of 90 degrees but also includes a phase of 90 degrees plus/minus 45 degrees.
The phase of the high frequency signal RF5 is illustrated as being delayed by 90 degrees with respect to the high frequency signal RF2. The power of the high frequency signal RF2 and the power of the high frequency signal RF5 are illustrated as being the same.
The bias circuit 14 applies a bias to the carrier amplifier 12. The bias circuit 15 applies a bias to the carrier amplifier 13. The carrier amplifier 12 outputs a high frequency signal RF3 obtained by amplifying the high frequency signal RF2 to the carrier amplifier 13. The carrier amplifier 13 outputs a high frequency signal RF4 obtained by amplifying the high frequency signal RF3 to the coupler 20.
The bias circuit 18 applies a bias to the peak amplifier 16. The bias circuit 19 applies a bias to the peak amplifier 17. The peak amplifier 16 outputs a high frequency signal RF6 obtained by amplifying the high frequency signal RF5 to the peak amplifier 17. The peak amplifier 17 outputs a high frequency signal RF7 obtained by amplifying the high frequency signal RF6 to the coupler 20.
The coupler 20 couples the high frequency signal RF4 with the high frequency signal RF7. In the first embodiment, the coupler 20 is a phase shifter. However, the present disclosure is not limited to this example. The coupler 20 performs output in such a manner that the phase of the high frequency signal RF4 is delayed by 90 degrees. The sum of the high frequency signal RF7 and the output signal of the coupler 20 is a high frequency signal RFout.
The high frequency signal RFin and a signal S1 indicating the drive level (operation level) of the carrier amplifier 13 are input to the detection circuit 22. Instead of the high frequency signal RFin, the high frequency signal RF1 may be input to the detection circuit 22. The signal S1 may be output from the bias circuit 15 or may be output from the carrier amplifier 13. In the case where the signal S1 is output from the carrier amplifier 13, the signal S1 may be the high frequency signal RF4. The signal S1 may be a signal (inversion signal) that changes in a complementary manner according to the drive level of the carrier amplifier 13.
The detection circuit 22 outputs a signal S2 for controlling the bias circuits 18 and 19 to the bias circuits 18 and 19 on the basis of the high frequency signal RFin and the signal S1. The bias circuit 18 applies a bias to the peak amplifier 16 on the basis of the signal S2. The bias circuit 19 applies a bias to the peak amplifier 17 on the basis of the signal S2.
The detection circuit 22 changes the rising point of the signal S2 in accordance with the signal S1. A waveform 31 represents the relationship between the power of the high frequency signal RFin and the signal S2 in the case where the drive level of the carrier amplifier 13 is relatively low. A waveform 32 represents the relationship between the power of the high frequency signal RFin and the signal S2 in the case where the drive level of the carrier amplifier 13 is relatively medium. A waveform 33 represents the relationship between the power of the high frequency signal RFin and the signal S2 in the case where the drive level of the carrier amplifier 13 is relatively high.
In the case where the drive level of the carrier amplifier 13 is relatively low, when the power of the high frequency signal RFin reaches a value A, the detection circuit 22 causes the signal S2 to rise, as indicated by the waveform 31. In the case where the power of the high frequency signal RFin is equal to or more than the value A, the detection circuit 22 increases the signal S2 as the power of the high frequency signal RFin increases.
In the case where the drive level of the carrier amplifier 13 is relatively medium, when the power of the high frequency signal RFin reaches a value B (B<A), the detection circuit 22 causes the signal S2 to rise, as indicated by the waveform 32. In the case where the power of the high frequency signal RFin is equal to or more than the value B, the detection circuit 22 increases the signal S2 as the power of the high frequency signal RFin increases.
In the case where the drive level of the carrier amplifier 13 is relatively high, when the power of the high frequency signal RFin reaches a value C (C<B), the detection circuit 22 causes the signal S2 to rise, as indicated by the waveform 33. In the case where the power of the high frequency signal RFin is equal to or more than the value C, the detection circuit 22 increases the signal S2 as the high frequency signal RFin increases.
In the case where input of a high frequency signal RFin with a high power, which is a main cause of saturation of the carrier amplifiers 12 and 13, occurs, the detection circuit 22 outputs the signal S2 to the bias circuits 18 and 19, so that the bias circuits 18 and 19 activate the peak amplifiers 16 and 17. Thus, basically, the carrier amplifiers 12 and 13 do not saturate.
Improving the response speed of the detection circuit 22 is suitable. Since the detection circuit 22 detects the high frequency signal RFin, the detection circuit 22 can respond at a significantly high speed, compared to the techniques in Patent Documents 1 and 2 in which saturation of a carrier amplifier is detected. Thus, even in the case where the power of the high frequency signal RFin has increased in a short period of time, the detection circuit 22 quickly responds and causes the bias circuits 18 and 19 to activate the peak amplifiers 16 and 17. Therefore, saturation of the carrier amplifiers 12 and 13 does not occur even for a moment.
However, in the case where temperature or other surrounding environmental conditions change (for example, in the case where the gain of the carrier amplifiers 12 and 13 increases at an extremely low temperature), the carrier amplifiers 12 and 13 may saturate even when the power of the high frequency signal RFin is low. To cope with such a case, the detection circuit 22 detects the signal S1 indicating the drive level of the carrier amplifiers 12 and 13. In the case where the carrier amplifiers 12 and 13 are in a state close to saturation, the detection circuit 22 promptly activates the peak amplifiers 16 and 17 even if the power of the high frequency signal RFin is low.
Since the detection circuit 22 detects the high frequency signal RFin, even if it takes time to detect the drive level of the carrier amplifiers 12 and 13, the detection circuit 22 is able to cause the bias circuits 18 and 19 to activate the peak amplifiers 16 and 17 without necessarily causing the carrier amplifiers 12 and 13 to saturate. Thus, the Doherty amplifier circuit 10 can suppress a decrease in the quality of the high frequency signal RFout.
It can be considered that the detection circuit 22 operates in a feed-forward manner in accordance with the high frequency signal RFin and operates in a feed-back manner in accordance with the signal S1.
The detection circuit 22 includes transistors QDE1 and QDE2 and resistors RDEE1 and RDEE2.
In the present disclosure, each of the transistors is a bipolar transistor. However, the present disclosure is not limited to this example. As the bipolar transistor, a heterojunction bipolar transistor (HBT) is illustrated. However, the present disclosure is not limited to this example. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor including a plurality of unit transistors that are electrically connected in parallel. A unit transistor represents the minimum element of a transistor.
The collector of the transistor QDE1 is electrically connected to a power supply potential Vcc. The emitter of the transistor QDE1 is electrically connected to one end of the resistor RDEE1. That is, the transistor QDE1 and the resistor RDEE1 are emitter-follower connected. The transistor QDE1 and the resistor RDEE1 form a first emitter-follower circuit 22a.
The detection circuit 22 may include a source-follower circuit, instead of the first emitter-follower circuit 22a.
The collector of the transistor QDE2 is electrically connected to the power supply potential Vcc. The emitter of the transistor QDE2 is electrically connected to one end of the resistor RDEE2. That is, the transistor QDE2 and the resistor RDEE2 are emitter-follower connected. The transistor QDE2 and the resistor RDEE2 form a second emitter-follower circuit 22b.
The detection circuit 22 may include a source-follower circuit, instead of the second emitter-follower circuit 22b.
The other end of the resistor RDEE1 and the other end of the resistor RDEE2 are electrically connected. The sum of an output current of the first emitter-follower circuit 22a and an output current of the second emitter-follower circuit 22b is an output current I1 of the detection circuit 22.
Resistors RDEBB, RDEB1, and RDEB2 and transistors QDE5, QDE6, and QDE7 apply bias voltages to the bases of the transistors QDE1 and QDE2.
One end of the resistor RDEBB, one end of the resistor RDEB1, and one end of the resistor RDEB2 are electrically connected.
The other end of the resistor RDEBB is electrically connected to the collector and base of the transistor QDE7. That is, the transistor QDE7 is diode-connected. The emitter of the transistor QDE7 is electrically connected to the collector and base of the transistor QDE6. That is, the transistor QDE6 is diode-connected. The emitter of the transistor QDE6 is electrically connected to the collector and base of the transistor QDE5. That is, the transistor QDE5 is diode-connected. The emitter of the transistor QDE5 is electrically connected to a reference potential. The reference potential is illustrated as a ground potential. However, the present disclosure is not limited to this example.
A bias current BIAS1 is input to one end of the resistor RDEBB, one end of the resistor RDEB1, and one end of the resistor RDEB2. The resistor RDEBB, the transistor QDE7, the transistor QDE6, and the transistor QDE5 generate a constant voltage. This voltage is input to the base of the transistor QDE1 through the resistor RDEB1 and to the base of the transistor QDE2 through the resistor RDEB2.
Each of the transistors QDE3 and QDE4 is current-mirror connected to the transistor QDE5. The collector of the transistor QDE3 is electrically connected to the base of the transistor QDE1. Thus, the transistor QDE3 is capable of adjusting the base current of the transistor QDE1. The collector of the transistor QDE4 is electrically connected to the base of the transistor QDE2. Thus, the transistor QDE4 is capable of adjusting the base current of the transistor QDE2.
High frequency signals IN1 and IN2 obtained by converting the high frequency signal RFin into differential signals are input to the base of the transistor QDE1 and the base of the transistor QDE2, respectively. The high frequency signals IN1 and IN2 can be obtained by, for example, inputting the high frequency signal RFin to a balun.
The other end of the resistor RDEE1 and the other end of the resistor RDEE2 are electrically connected to a constant current circuit 41. The constant current circuit 41 includes transistors QDE11 and QDE12. The constant current circuit 41 is a current bias circuit for the detection circuit 22.
The transistor QDE12 is diode-connected. A voltage BIAS2 indicating the drive level of the carrier amplifier 13 (see
In the first embodiment, the voltage BIAS2 is a voltage that changes in a complementary manner according to the drive level of the carrier amplifier 13. In the case where the drive level of the carrier amplifier 13 is relatively high (close to saturation), the voltage BIAS2 is relatively low. In the case where the drive level of the carrier amplifier 13 is relatively low (amplification rate decreases), the voltage BIAS2 is relatively high.
The transistor QDE11 is current-mirror connected to the transistor QDE12. Thus, a collector current I2 of the transistor QDE11 is a current corresponding to the voltage BIAS2.
The collector of the transistor QDE11 is electrically connected to the other end of the resistor RDEE1 and the other end of the resistor RDEE2.
The low pass filter 42 includes a capacitor Cenv. One end of the capacitor Cenv is electrically connected to the other end of the resistor RDEE1, the other end of the resistor RDEE2, and the collector of the transistor QDE11. The other end of the capacitor Cenv is electrically connected to the reference potential.
The capacitor Cenv is charged or discharged in accordance with a difference between the output current I1 of the detection circuit 22 and the collector current I2 of the transistor QDE11. The voltage of the capacitor Cenv serves as the signal S2. The capacitor Cenv terminates a high frequency component (for example, a carrier frequency signal component) of the signal S2 to the reference potential and eliminates the high frequency component, so that only a low frequency component passes through the capacitor Cenv. Thus, the capacitor Cenv allows the bias circuits 18 and 19 in the stage following the low pass filter 42 and a bias supply target transistor (amplifier transistor) to be properly biased.
The bias circuit 18 includes transistors QDE8, QDE9, and QDE10. Since the circuit configuration of the bias circuit 19 (see
The transistor QDE9 is diode-connected. The collector and base of the transistor QDE9 are electrically connected to one end of the capacitor Cenv. The emitter of the transistor QDE9 is electrically connected to the collector and base of the transistor QDE8. The transistor QDE8 is diode-connected. The emitter of the transistor QDE8 is electrically connected to the reference potential. A current corresponding to the voltage of the capacitor Cenv flows to the transistors QDE9 and QDE8.
The collector of the transistor QDE10 is electrically connected to the power supply potential Vcc. The base of the transistor QDE10 is electrically connected to the collector and base of the transistor QDE9. The emitter voltage of the transistor QDE10 is output as a bias voltage BIAS16 (BIAS17) to the peak amplifier 16 (17).
Operation of the detection circuit 22 will be described.
The transistor QDE1 is turned on when the high frequency signal IN1 is equal to or more than a threshold voltage of the transistor QDE1, and outputs an emitter current. The transistor QDE2 is turned on when the high frequency signal IN2 is equal to or more than a threshold voltage of the transistor QDE2, and outputs an emitter current.
That is, as the amplitudes of the high frequency signals IN1 and IN2 increase (power of the high frequency signal RFin increases), the output current of the detection circuit 22 increases. Furthermore, as the amplitudes of the high frequency signals IN1 and IN2 decrease (power of the high frequency signal RFin decreases), the output current of the detection circuit 22 decreases.
In contrast, as described above, the voltage BIAS2 is relatively low in the case where the drive level of the carrier amplifier 13 is relatively high (close to saturation), and the voltage BIAS2 is relatively high in the case where the drive level of the carrier amplifier 13 is relatively low (amplification rate decreases).
That is, as the drive level of the carrier amplifier 13 relatively increases (closer to saturation), the collector current I2 of the transistor QDE11 decreases. Furthermore, as the drive level of the carrier amplifier 13 relatively decreases (amplification rate decreases), the collector current I2 of the transistor QDE11 increases.
Summarizing the above, the voltage of the capacitor Cenv is more likely to increase as the drive level of the carrier amplifier 13 relatively increases (closer to saturation). The voltage of the capacitor Cenv is less likely to increase as the drive level of the carrier amplifier 13 relatively decreases (amplification rate decreases). Furthermore, the voltage of the capacitor Cenv is more likely to increase as the power of the high frequency signal RFin increases. The voltage of the capacitor Cenv is less likely to increase as the power of the high frequency signal RFin decreases.
A waveform 51 represents variations in the bias voltage BIAS16 (BIAS17) in the case where the drive level of the carrier amplifier 13 is relatively low. A waveform 52 represents variations in the bias voltage BIAS16 (BIAS17) in the case where the drive level of the carrier amplifier 13 is relatively medium. A waveform 53 represents variations in the bias voltage BIAS16 (BIAS17) in the case where the drive level of the carrier amplifier 13 is relatively high.
In the case where the drive level of the carrier amplifier 13 is relatively high, the detection circuit 22 is able to cause the peak amplifiers 16 and 17 to rise even when the power of the high frequency signal RFin is low, as indicated by the waveform 53. In contrast, in the case where the drive level of the carrier amplifier 13 is relatively low, the detection circuit 22 is able to delay the rise of the peak amplifiers 16 and 17 until the power of the high frequency signal RFin becomes high, as indicated by the waveform 51.
Thus, in the case where the drive level of the carrier amplifier 13 is relatively high (close to saturation), the current of the constant current circuit 41 may be small so that the peak amplifiers 16 and 17 can be caused to rise even when the power of the high frequency signal RFin is low. In contrast, in the case where the drive level of the carrier amplifier 13 is relatively low, since there is no need to rise the peak amplifiers 16 and 17 until the power of the high frequency signal RFin becomes high, the current of the constant current circuit 41 may be large. That is, by setting the voltage BIAS2 input to the constant current circuit 41 to be a voltage that changes in a complementary manner according to the drive level of the carrier amplifier 13, a desired operation as the entire circuit can be attained.
Rapid response of the detection circuit 22 can be achieved due to the reasons described below.
Firstly, differential operation is performed by the first emitter-follower circuit 22a and the second emitter-follower circuit 22b. Thus, compared to the case where an emitter-follower circuit performs a single-end operation, the capacitance of the capacitor Cenv can be decreased. Accordingly, delay at the capacitor Cenv can be reduced, and the signal S2 quickly changes. That is, the detection circuit 22 can respond quickly.
Secondly, an emitter-follower circuit is a circuit capable of outputting a large current. Therefore, each of the first emitter-follower circuit 22a and the second emitter-follower circuit 22b is capable of outputting a large current. That is, the detection circuit 22 is capable of outputting a large output current I1. Thus, the detection circuit 22 is capable of charging the capacitor Cenv quickly. That is, the rise response of the detection circuit 22 is fast.
Thirdly, the transistor QDE11 is capable of discharging the capacitor Cenv using a constant current (collector current I2). Thus, the transistor QDE11 is capable of discharging the capacitor Cenv quickly. That is, the drop response of the detection circuit 22 is fast.
The bias circuit 15 that applies a bias to the final-stage carrier amplifier 13 includes a resistor RCBB and transistors QCB1, QCB2, and QCB3.
A bias current BIASC is input to one end of the resistor RCBB. The other end of the resistor RCBB is connected to the transistors QCB1 and QCB2. The transistors QCB1 and QCB2 are circuits in which base and collector terminals of the transistors are connected so as to operate similarly to diodes and are connected in a two-stage manner. The base of the transistor QCB3 is electrically connected to the base of the transistor QCB2. The collector of the transistor QCB3 is electrically connected to the power supply potential Vcc. The transistor QCB3 outputs, through the emitter thereof, a bias current BIAS13 to the carrier amplifier 13.
In this specific example, the emitter voltage of the transistor QCB3 corresponds to the signal S1.
A low pass filter 43 includes a resistor RLPF and a capacitor CLPF.
One end of the resistor RLPF is electrically connected to the emitter of the transistor QCB3. The other end of the resistor RLPF is electrically connected to one end of the capacitor CLPF. The other end of the capacitor CLPF is electrically connected to the reference potential.
Unlike the constant current circuit 41 (see
The other end of the resistor RLPF and the one end of the capacitor CLPF are electrically connected to the base of the transistor QDE11. The low pass filter 43 performs low-pass filtering of the signal S1 and outputs the low-pass filtered signal S1 to the base of the transistor QDE11.
In the circuit illustrated in
Furthermore, in the circuit illustrated in
In contrast, in the circuit illustrated in
Thus, at the path connecting the bias circuit 15, the detection circuit 22, the bias circuit 19, the peak amplifier 17, the coupler 20, the carrier amplifier 13, and the bias circuit 15 in that order, isolation in a high frequency signal band can be increased. If isolation in the path is not sufficient, the path may become a return path, which may cause oscillation. However, in the circuit illustrated in
In the case where the peak bias circuit has three or more stages, the control circuit 21 may control at least the bias circuit 18 that applies a bias to the initial-stage peak amplifier 16 and the bias circuit 19 that applies a bias to the final-stage peak amplifier 17.
In the first embodiment, the amplifier 2 in the stage preceding the Doherty amplifier circuit 10 is a single-end amplifier. However, the present disclosure is not limited to this example. An amplifier in the stage preceding the Doherty amplifier circuit 10 may be a differential amplifier.
A power amplifier circuit 1A includes a balun 61, an amplifier 2A, the bias circuit 3, and a Doherty amplifier circuit 10A. The Doherty amplifier circuit 10A includes 90-degree hybrid circuits 11A and 11B, an initial-stage carrier amplifier 12A, a final-stage carrier amplifier 13A, the bias circuits 14 and 15, an initial-stage peak amplifier 16A, a final-stage peak amplifier 17A, the bias circuits 18 and 19, a coupler 20A, and the control circuit 21.
The number of stages of the Doherty amplifier circuit 10A is two. However, the present disclosure is not limited to this example. The number of stages of the power amplifier circuit 10A may be one or three or more.
Each of the amplifier 2A, the carrier amplifiers 12A and 13A, and the peak amplifiers 16A and 17A is a differential amplifier.
In the present disclosure, it is desirable that the difference of voltage amplitude between an output signal of one amplifier in the differential amplifier and an output signal of the other amplifier in the differential amplifier be 3 dB or less and the phase difference be within a range from 90 degrees to 270 degrees.
The balun 61 outputs high frequency signals RF11 and RF12 that form differential signals, on the basis of the input high frequency signal RFin.
The bias circuit 3 applies a bias to the amplifier 2A. A first amplifier 71 in the amplifier 2A outputs a high frequency signal RF13 obtained by amplifying the high frequency signal RF11 to the 90-degree hybrid circuit 11A. A second amplifier 72 outputs a high frequency signal RF14 obtained by amplifying the high frequency signal RF12 to the 90-degree hybrid circuit 11B.
The 90-degree hybrid circuit 11A divides the high frequency signal RF13 into high frequency signals RF15 and RF16 whose phases are different by approximately 90 degrees. The 90-degree hybrid circuit 11A outputs the high frequency signal RF15 to the carrier amplifier 12A, and outputs the high frequency signal RF16 to the peak amplifier 16A.
The 90-degree hybrid circuit 11B divides the high frequency signal RF14 into high frequency signals RF17 and RF18 whose phases are different by approximately 90 degrees. The 90-degree hybrid circuit 11B outputs the high frequency signal RF17 to the carrier amplifier 12A, and outputs the high frequency signal RF18 to the peak amplifier 16A.
The bias circuit 14 applies a bias to the carrier amplifier 12A. A first amplifier 73 in the carrier amplifier 12A outputs a high frequency signal RF19 obtained by amplifying the high frequency signal RF15 to the carrier amplifier 13A. A second amplifier 74 in the carrier amplifier 12A outputs a high frequency signal RF20 obtained by amplifying the high frequency signal RF17 to the carrier amplifier 13A.
The bias circuit 15 applies a bias to the carrier amplifier 13A. A first amplifier 75 in the carrier amplifier 13A outputs a high frequency signal RF21 obtained by amplifying the high frequency signal RF19 to the coupler 20A. A second amplifier 76 in the carrier amplifier 13A outputs a high frequency signal RF22 obtained by amplifying the high frequency signal RF20 to the coupler 20A.
The bias circuit 18 applies a bias to the peak amplifier 16A. A first amplifier 77 in the peak amplifier 16A outputs a high frequency signal RF23 obtained by amplifying the high frequency signal RF16 to the peak amplifier 17A. A second amplifier 78 in the peak amplifier 16A outputs a high frequency signal RF24 obtained by amplifying the high frequency signal RF18 to the peak amplifier 17A.
The bias circuit 19 applies a bias to the peak amplifier 17A. A first amplifier 79 in the peak amplifier 17A outputs a high frequency signal RF25 obtained by amplifying the high frequency signal RF23 to the coupler 20A. A second amplifier 80 in the peak amplifier 17A outputs a high frequency signal RF26 obtained by amplifying the high frequency signal RF24 to the coupler 20A.
The coupler 20A couples the high frequency signals RF21, RF22, RF25, and RF26, and outputs the high frequency signal RFout.
The high frequency signals RF11 and RF12 and the signal S1 indicating the drive level of the carrier amplifier 13A are input to the detection circuit 22.
In the first modification, the high frequency signals RF11 and RF12 correspond to the high frequency signals IN1 and IN2 (see
Instead of the high frequency signals RF11 and RF12, the high frequency signals RF13 and RF14 may be input to the detection circuit 22. The signal S1 may be output from the bias circuit 15 or may be output from the carrier amplifier 13A.
The detection circuit 22 outputs the signal S2 to the bias circuits 18 and 19 on the basis of the high frequency signals RF11 and RF12 and the signal S1. The bias circuit 18 applies a bias to the peak amplifier 16A on the basis of the signal S2. The bias circuit 19 applies a bias to the peak amplifier 17A on the basis of the signal S2.
Unlike the power amplifier circuit 1A according to the first modification (see
The number of stages of the Doherty amplifier circuit 10B is two. However, the present disclosure is not limited to this example. The number of stages of the Doherty amplifier circuit 10B may be one or three or more.
The 90-degree hybrid circuit 11C is a 90-degree hybrid circuit that performs a differential operation. The 90-degree hybrid circuit 11C includes windings L1, L2, L3, and L4 and cores 81 and 82.
The winding L1 is wound around the core 81. The winding L2 is wound around the core 81 in a direction opposite to the direction in which the winding L1 is wound (opposite winding direction). The winding L3 is wound around the core 82 in a direction opposite to the direction in which the winding L1 is wound (opposite winding direction). The winding L4 is wound around the core 82 in the same direction as the direction in which the winding L1 is wound (same winding direction).
One end of the winding L1 is electrically connected to the first amplifier 71 in the amplifier 2A. The other end of the winding L1 is electrically connected to the first amplifier 73 in the carrier amplifier 12A. One end of the winding L2 is electrically connected to the reference potential. The other end of the winding L2 is electrically connected to the first amplifier 77 in the peak amplifier 16A.
One end of the winding L3 is electrically connected to the reference potential. The other end of the winding L3 is electrically connected to the second amplifier 78 in the peak amplifier 16A. One end of the winding L4 is electrically connected to the second amplifier 72 in the amplifier 2A. The other end of the winding L4 is electrically connected to the second amplifier 74 in the carrier amplifier 12A.
Operation of the power amplifier circuit 1B is similar to operation of the power amplifier circuit 1A, and description of the operation of the power amplifier circuit 1B will be omitted.
Component elements of a power amplifier circuit according to the second embodiment that are the same as component elements in the first embodiment are denoted by the same reference signs, and description of the same component elements will be omitted.
Unlike the power amplifier circuit 1 according to the first embodiment (see
The number of stages of the Doherty amplifier circuit 10C is two. However, the present disclosure is not limited to this example. The number of stages of the Doherty amplifier circuit 10C may be one or three or more.
The high frequency signal RFin and the signal S1 indicating the drive level of the carrier amplifier 13 are input to the variable attenuator 23. Instead of the high frequency signal RFin, a high frequency signal RF1 may be input to the variable attenuator 23.
The variable attenuator 23 attenuates the high frequency signal RFin on the basis of the signal S1, and outputs an attenuated high frequency signal RF31. The detection circuit 22 outputs the signal S2 to the bias circuits 18 and 19 on the basis of the high frequency signal RF31.
In the first embodiment, a bias point of the detection circuit 22 is changed according to the signal S1.
In contrast, in the second embodiment, the bias point of the detection circuit 22 is fixed. The amount of attenuation at the variable attenuator 23, which is provided in a stage preceding the detection circuit 22, is changed according to the signal S1. Thus, the control circuit 21A is capable of outputting the signal S2 corresponding to the drive level of the carrier amplifier 13.
The base of the transistor QDE11 is electrically connected to the collector and base of the transistor QDE5. Thus, in the second embodiment, the collector current I2 is fixed.
The variable attenuator 23 includes resistors RAT1, RAT2, RAT3, and RAT4, transistors QAT1, QAT2, and QAT3, and capacitors CAT1 and CAT2.
One end of the resistor RAT2 is electrically connected to the power supply potential Vcc. The other end of the resistor RAT2 is electrically connected to the collector and base of the transistor QAT3. That is, the transistor QAT3 is diode-connected. The emitter of the transistor QAT3 is electrically connected to a node N2.
The collector and base of the transistor QAT2 is electrically connected to the node N2. That is, the transistor QAT2 is diode-connected. The emitter of the transistor QAT2 is electrically connected to a node N1.
One end of the resistor RAT1 is electrically connected to the node N1. The other end of the resistor RAT1 is electrically connected to the collector of the transistor QAT1. The emitter of the transistor QAT1 is electrically connected to the reference potential. The signal S1 that has been low-pass filtered by the low pass filter 43 is input to the base of the transistor QAT1.
The high frequency signal IN1 is input to one end of the resistor RAT3. The other end of the resistor RAT3 is electrically connected to the node N1. One end of the capacitor CAT1 is electrically connected to the node N1. The other end of the capacitor CAT1 is electrically connected to the base of the transistor QDE1.
The high frequency signal IN2 is input to one end of the resistor RAT4. The other end of the resistor RAT4 is electrically connected to the node N2. One end of the capacitor CAT2 is electrically connected to the node N2. The other end of the capacitor CAT2 is electrically connected to the base of the transistor QDE2.
The variable attenuator 23 is an attenuator that uses the principle that the equivalent resistance of the transistor QAT1 decreases as the current flowing in the transistor QAT1 increases.
In the case where the drive level of the carrier amplifier 13 is relatively low, a relatively high voltage is input to the base of the transistor QAT1, which is a control terminal for the variable attenuator 23. At this time, a large amount of collector current of the transistor QAT1 flows, and a large amount of current also flows in the transistors QAT2 and QAT3. Thus, the equivalent resistance of the transistors QAT1, QAT2, and QAT3 decreases, and the nodes N1 and N2 to which the high frequency signals IN1 and IN2 are transmitted enter a state close to short circuit. Therefore, the variable attenuator 23 does not allow the frequency signals IN1 and IN2 to pass therethrough.
In contrast, in the case where the drive level of the carrier amplifier 13 is relatively high, current does not flow to the transistors QAT1, QAT2, and QAT3. Thus, the variable attenuator 23 allows the frequency signals IN1 and IN2 to pass therethrough.
By providing the variable attenuator 23 in the stage preceding the detection circuit 22, the detection circuit 22 is capable of outputting the signal S2 corresponding to the drive level of the carrier amplifier 13.
The variable attenuator 23 substantially needs to control bandpass characteristics (attenuation characteristics) and delay of the input/output characteristics of the frequency signals IN1 and IN2 only needs to be small. Thus, various types of devices such as a variable gain amplifier may be used as the variable attenuator 23.
By providing the variable attenuator 23 as in the second embodiment, the sensitivity of output of the detection circuit 22 with respect to the drive level of the carrier amplifier 13 can be designed freely, and it is obvious that designing can be done easily.
In the second embodiment, in addition to a stabilization effect as in the first embodiment, an effect of further stabilization can be achieved. Reasons for these effects will be described below.
In the configuration of the first embodiment (see
In contrast, in the configuration of the second embodiment (see
As in the first modification (see
Component elements of a power amplifier circuit according to a third embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
A power amplifier circuit 111 (Doherty amplifier circuit 10D) includes the 90-degree hybrid circuit 11, baluns 121, 122, 127, and 128, the initial-stage carrier amplifier 12A, an intermediate-stage carrier amplifier 123, the final-stage carrier amplifier 13A, bias circuits 14, 15, and 124, the initial-stage peak amplifier 16A, an intermediate-stage peak amplifier 125, the final-stage peak amplifier 17A, bias circuits 18, 19, and 126, the coupler 20A, and a control circuit 21B.
The number of stages of the Doherty amplifier circuit 10D is three. However, the present disclosure is not limited to this example. The number of stages of the Doherty amplifier circuit 10D may be two or less or four or more.
Each of the carrier amplifiers 12A, 13A, and 123 and the peak amplifiers 16A, 17A, and 125 is a differential amplifier.
The 90-degree hybrid circuit 11 divides the high frequency signal RFin into high frequency signals RF41 and RF42 whose phases are different by approximately 90 degrees. The 90-degree hybrid circuit 11 outputs the high frequency signal RF41 to one end of a first winding of the balun 121, and outputs the high frequency signal RF42 to one end of a first winding of the balun 122. The other end of the first winding of the balun 121 and the other end of the first winding of the balun 122 are electrically connected to the reference potential.
The balun 121 outputs, through corresponding ends of a second winding thereof, high frequency signals RF43 and RF44 configuring differential signals, on the basis of the input high frequency signal RF41.
The balun 122 outputs, through corresponding ends of a second winding thereof, high frequency signals RF45 and RF46 configuring differential signals, on the basis of the input high frequency signal RF42.
The first amplifier 73 in the carrier amplifier 12A outputs a high frequency signal RF47 obtained by amplifying the high frequency signal RF43 to the carrier amplifier 123. The second amplifier 74 in the carrier amplifier 12A outputs a high frequency signal RF48 obtained by amplifying the high frequency signal RF44 to the carrier amplifier 123.
The bias circuit 124 applies a bias to the carrier amplifier 123. A first amplifier 131 in the carrier amplifier 123 outputs a high frequency signal RF49 obtained by amplifying the high frequency signal RF47 to one end of a first winding of the balun 127. A second amplifier 132 in the carrier amplifier 123 outputs a high frequency signal RF50 obtained by amplifying the high frequency signal RF48 to the other end of the first winding of the balun 127.
The balun 127 outputs, through corresponding ends of a second winding thereof, high frequency signals RF51 and RF52 configuring differential signals, on the basis of the input high frequency signals RF49 and RF50.
The first amplifier 75 in the carrier amplifier 13A outputs a high frequency signal RF53 obtained by amplifying the high frequency signal RF51 to one end of a first winding L5 of the coupler 20A. The second amplifier 76 in the carrier amplifier 13A outputs a high frequency signal RF54 obtained by amplifying the high frequency signal RF52 to the other end of the first winding L5 of the coupler 20A.
The first amplifier 77 in the peak amplifier 16A outputs a high frequency signal RF55 obtained by amplifying the high frequency signal RF45 to the peak amplifier 125. The second amplifier 78 in the peak amplifier 16A outputs a high frequency signal RF56 obtained by amplifying the high frequency signal RF46 to the peak amplifier 125.
The bias circuit 126 applies a bias to the peak amplifier 125. A first amplifier 133 in the peak amplifier 125 outputs a high frequency signal RF57 obtained by amplifying the high frequency signal RF55 to one end of a first winding of the balun 128. A second amplifier 134 in the peak amplifier 125 outputs a high frequency signal RF58 obtained by amplifying the high frequency signal RF56 to the other end of the first winding of the balun 128.
The balun 128 outputs, through corresponding ends of a second winding thereof, high frequency signals RF59 and RF60 configuring a pair of differential signals, on the basis of the input high frequency signals RF57 and RF58.
The first amplifier 79 in the peak amplifier 17A outputs a high frequency signal RF61 obtained by amplifying the high frequency signal RF59 to one end of a third winding L7 of the coupler 20A. The second amplifier 80 in the peak amplifier 17A outputs a high frequency signal RF62 obtained by amplifying the high frequency signal RF60 to the other end of the third winding L7 of the coupler 20A.
The first winding L5 in the coupler 20A is wound around a core 141. A second winding L6 in the coupler 20A is wound around the core 141 in the same direction as the direction in which the first winding L5 is wound (same winding direction). The third winding L7 in the coupler 20A is wound around a core 142 in the same direction as the direction in which the first winding L5 is wound (same winding direction). A fourth winding L8 in the coupler 20A is wound around the core 142 in the same direction as the direction in which the third winding L7 is wound (same winding direction). One end of the second winding L6 and one end of the fourth winding L8 are electrically connected. The other end of the fourth winding L8 is electrically connected to the reference potential. The high frequency signal RFout is output from the other end of the second winding L6 through the capacitor 143.
Unlike the control circuit 21A (see
The high frequency signals RF45 and RF46 forming differential signals are input to the attenuator 24. Instead of the high frequency signals RF45 and RF46, the high frequency signals RF43 and RF44 may be input to the attenuator 24. The attenuator 24 outputs high frequency signals RF63 and RF64 obtained by attenuating the high frequency signals RF45 and RF46, respectively, to the variable attenuator 23. It is desirable that the amount of attenuation at the attenuator 24 be adjustable in accordance with a control signal S3 from the outside.
The high frequency signals RF63 and RF64 and the signal S1 indicating the drive level of the carrier amplifier 13A are input to the variable attenuator 23.
The control circuit 21B controls not only the bias circuit 19 that applies a bias to the final-stage peak amplifier 17A but also the bias circuit 18 that applies a bias to the initial-stage peak amplifier 16A.
Changes in features between the power amplifier circuit 101 according to the second embodiment (see
Firstly, in the case where the peak amplifiers 16 and 17 are single-end amplifiers as in the power amplifier circuit 101 according to the second embodiment, a high frequency signal causes the peak amplifiers 16 and 17 to oscillate and part of the high frequency signal causes the emitter of the transistor QDE10 inside the bias circuits 18 and 19 (see
In contrast, in the power amplifier circuit 111 according to the third embodiment, by using differential amplifiers as the all stages of carrier amplifiers and peak amplifiers, the possibility of high frequency signals flowing into the bias circuit side from bias voltage input terminals of the peak amplifiers 16A, 125, and 17A can be reduced.
Secondly, as described above, in the power amplifier circuit 111 according to the third embodiment, by using differential amplifiers as the peak amplifiers 16A, 125, and 17A, an unintended detection operation by the transistor QDE10 can be significantly reduced. However, even if differential amplifiers are used as the peak amplifiers 16A, 125, and 17A, the differential amplifiers are less likely to operate at exactly opposite phases. Thus, a high frequency signal may flow into the bias circuit side from the bias voltage input terminal of each of the peak amplifiers 16A, 125, and 17A.
In the power amplifier circuit 111 according to the third embodiment, the control circuit 21B controls the bias circuit 18 that applies a bias to the initial-stage peak amplifier 16A as well as the bias circuit 19 that applies a bias to the final-stage peak amplifier 17A. Thus, since a high frequency signal that flows into the bias circuit 18 side from the peak amplifier 16A can be suppressed, the possibility that the transistor QDE10 performs a detection operation can further be reduced.
Thirdly, for example, the case where environmental temperature drops and the total gain of all stages of carrier amplifiers increases will be considered. In such a case, typically, since the gain increases, the final-stage carrier amplifier 13A may saturate even when input power is low.
In the power amplifier circuit 1 according to the first embodiment (see
Thus, the power amplifier circuit 111 according to the third embodiment includes the attenuator 24 that is capable of adjusting the amount of attenuation in accordance with the control signal S3 from the outside. It is desirable that adjustment of the amount of attenuation at the attenuator 24 be performed in the case where it is clear from a change in environment or conditions that input power for causing the peak amplifier 16A (17A) to rise has been changed. In the power amplifier circuit 111 according to the third embodiment, it is desirable that the amount of attenuation at the attenuator 24 be externally adjusted on the basis of information about ambient temperature, external load conditions, or characteristics of an input signal (center frequency, average power, PAPR (Peak to Average Power Ratio), etc.), or history information about the ambient temperature, the external load conditions, or the characteristics of the input signal.
Thus, even if environment or conditions change, the power amplifier circuit 111 according to the third embodiment can reduce the possibility that the carrier amplifier 13A saturates.
Although the control circuit 21B controls the bias circuits 18 and 19 in the third embodiment, the present disclosure is not limited to this example. The control circuit 21B may also control the bias circuit 126. The control circuit 21B may control at least the bias circuit 18 that applies a bias to the initial-stage peak amplifier 16A and the bias circuit 19 that applies a bias to the final-stage peak amplifier 17A.
Component elements of a power amplifier circuit according to a fourth embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
Although the signal S1 indicating the drive level of the carrier amplifier 13 is processed at the detection circuit 22 or in a stage preceding the detection circuit 22 and the processed signal S1 is reflected in the signal S2 in the first embodiment and the second embodiment, the present disclosure is not limited to this example. The signal S1 indicating the drive level of the carrier amplifier 13 may be added to a signal output from the detection circuit 22.
Unlike the power amplifier circuit 1 according to the first embodiment (see
The adder circuit 25 corresponds to an example of a “bias control circuit” according to the present disclosure.
The number of stages of the Doherty amplifier circuit 10E is two. However, the present disclosure is not limited to this example. The number of stages of the Doherty amplifier circuit 10E may be one or three or more.
The high frequency signal RFin is input to the detection circuit 22. Instead of the high frequency signal RFin, the high frequency signal RF1 may be input to the detection circuit 22.
The detection circuit 22 outputs a signal S4 to the adder circuit 25 on the basis of the high frequency signal RFin.
The signal S1 indicating the drive level of the carrier amplifier 13 is input to the adder circuit 25. The signal S1 may be output from the bias circuit 15 or may be output from the carrier amplifier 13.
The adder circuit 25 outputs the signal S2, which is obtained by adding the signal S1 and the signal S4, to the bias circuits 18 and 19.
The adder circuit 25 includes a resistor ROP and a transistor QOP.
One end of the resistor ROP is electrically connected to the emitter of the transistor QDE10. The other end of the resistor ROP is electrically connected to the collector of the transistor QOP. The base of the transistor QOP is electrically connected to the other end of the resistor RLPF and one end of the capacitor CLPF. The emitter of the transistor QOP is electrically connected to the reference potential. The bias voltage BIAS16 (BIAS17) is output from a connection point of the other end of the resistor ROP and the collector of the transistor QOP.
As described above in other embodiments, the signal S1 is a signal (inversion signal) that changes in a complementary manner according to the drive level of the carrier amplifier 13. Thus, the adder circuit 25 subtracts the signal S1 from the signal S2 (adds a minus S1 signal) and thus outputs the bias voltage BIAS16 (BIAS7).
The transistor QOP converts the signal S1 input to the base thereof into a collector current. The bias voltage BIAS16 (BIAS17) is a voltage obtained by subtracting a voltage drop represented by the product of the collector current value of the transistor QOP and the resistance of the resistor ROP from the output voltage of the bias circuit 18 (19).
As in the first modification (see
Component elements of a power amplifier circuit according to a fifth embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
Unlike the power amplifier circuit 1 according to the first embodiment (see
The number of stages of the Doherty amplifier circuit 10F is two. However, the present disclosure is not limited to this example. The number of stages of the Doherty amplifier circuit 10F may be one or three or more.
The drive level detection circuit 26 outputs the signal S1 indicating the drive level of the carrier amplifier 13 to the detection circuit 22 on the basis of the high frequency signal RF4 output from the carrier amplifier 13.
The high frequency signal RFin and the signal S1 are input to the detection circuit 22. Instead of the high frequency signal RFin, the high frequency signal RF1 may be input to the detection circuit 22.
The detection circuit 22 outputs the signal S2 for controlling the bias circuits 18 and 19 to the bias circuits 18 and 19 on the basis of the high frequency signal RFin and the signal S1. The bias circuit 18 applies a bias to the peak amplifier 16 on the basis of the signal S2. The bias circuit 19 applies a bias to the peak amplifier 17 on the basis of the signal S2.
The drive level detection circuit 26 includes resistors RMO1, RMO2, RMO3, RMO4, and RMO5, transistors QMO1, QMO2, QMO4, QMO5, QMO6, and QMO7, and a capacitor CMO1.
In this specific example, the carrier amplifier 13 (see
The high frequency signal RF71 is input to the emitter of the transistor QMO1. The emitter of the transistor QMO1 is illustrated as being electrically connected to an output terminal (the collector or drain of an output transistor) of one amplifier in the carrier amplifier 13.
The high frequency signal RF72 is input to the emitter of the transistor QMO2. The emitter of the transistor QMO2 is illustrated as being electrically connected to an output terminal (the collector or drain of an output transistor) of the other amplifier in the carrier amplifier 13.
The base of the transistor QMO1 and the base of the transistor QMO2 are electrically connected to a node N3.
The collector of the transistor QMO1 and the collector of the transistor QMO2 are electrically connected to a node N4.
The resistors RMO1, RMO2, and RMO3 and the transistor QMO4 apply voltages to the node N3. That is, the resistors RMO1, RMO2, and RMO3 and the transistor QMO4 apply biases to the base of the transistor QMO1 and the base of the transistor QMO2.
One end of the resistor RMO3 is electrically connected to the power supply potential Vcc. The other end of the resistor RMO3 is electrically connected to the node N3, the collector of the transistor QMO4, and one end of the resistor RMO1. The other end of the resistor RMO1 is electrically connected to the base of the transistor QMO4 and one end of the resistor RMO2. The emitter of the transistor QMO4 and the other end of the resistor RMO2 are electrically connected to the reference potential. The resistors RMO1 and RMO2 and the transistor QMO4 generate a constant voltage. This voltage serves as the voltage of the node N3.
The resistors RMO4 and RMO5 and the transistors QMO6 and QMO7 apply voltages to the node N4. That is, the resistors RMO4 and RMO5 and the transistors QMO6 and QMO7 apply biases to the collector of the transistor QMO1 and the collector of the transistor QMO2.
One end of the resistor RMO5 is electrically connected to the power supply potential Vcc. The other end of the resistor RMO5 is electrically connected to the collector and base of the transistor QMO6. That is, the transistor QMO6 is diode-connected. The emitter of the transistor QMO6 is electrically connected to the collector and base of the transistor QMO7. That is, the transistor QMO7 is diode-connected. The emitter of the transistor QMO7 is electrically connected to the reference potential. One end of the resistor RMO4 is electrically connected to the other end of the resistor RMO5 and the collector and base of the transistor QMO6. The other end of the resistor RMO4 is electrically connected to the node N4. The transistors QMO6 and QMO7 generate a constant voltage. This voltage serves as the voltage of the node N4 through the resistor RMO4.
The collector and base of the transistor QMO5 is electrically connected to the node N4. That is, the transistor QMO5 is diode-connected. The emitter of the transistor QMO5 is electrically connected to one end of the capacitor CMO1. The other end of the capacitor CMO5 is electrically connected to the reference potential.
The transistor QMO5 outputs, through the emitter thereof, the signal S1. The capacitor CMO1 smooths the signal S1 by shunting a high frequency component of the signal S1.
The resistors RMO1, RMO2, and RMO3 and the transistor QMO4 only need to output a roughly constant voltage and may be considered as a constant voltage source. The resistor RMO5 and the transistors QMO6 and QMO7 only need to output a roughly constant voltage and may be considered as a constant voltage source. The transistor QMO5 only needs to generate a roughly constant voltage drop and may be considered as a constant voltage source.
A constant voltage source VMO1 in
An operation of the drive level detection circuit 26 will be described with reference to the equivalent circuit of
Typically, the output terminal voltage of the final-stage carrier amplifier vibrates at a voltage amplitude of a high frequency signal centered at a bias voltage. When the final-stage carrier amplifier saturates, a situation in which the voltage amplitude of a high frequency signal increases to be substantially equal to the bias voltage occurs. In such a situation, the moment at which the output terminal voltage approaches 0 V occurs during the amplitude period of the high frequency signal. At this moment, no amplification effect is obtained, which leads to a phenomenon such as saturation of an amplifier.
A circuit in this specific example uses this principle of saturation and thus detects the drive level of the carrier amplifier 13.
Specifically, in the periods of the high frequency signals RF71 and RF72, for only the periods during which the voltages of the high frequency signals RF71 and RF72 are lower than a voltage obtained by subtracting a voltage drop equivalent to a threshold voltage for the transistors QMO1 and QMO2 from the voltage of the constant voltage source VMO1, the transistors QMO1 and QMO2 are in the ON state.
When the carrier amplifier 13 operates in a state in which saturation is least likely to occur, the transistors QMO1 and QMO2 do not have an ON period, and collector current does not flow. Therefore, no current flows to the resistor RMO4, and no voltage drop occurs. Thus, the signal S1 is a voltage obtained by subtracting the voltage of the constant voltage source VMO3 from the voltage of the constant voltage source VMO2.
In contrast, when the amplitude of the high frequency signals RF71 and RF72 increases, the transistors QMO1 and QMO2 have an ON period, and collector current flows. Therefore, current flows to the resistor RMO4, and a voltage drop occurs.
When the amplitude of the high frequency signals RF71 and RF72 further increases, the length of the ON period of the transistors QMO1 and QMO2 increases. Thus, a larger amount of collector current flows. Therefore, a larger amount of current flows to the resistor RMO4, and a larger voltage drop occurs.
Thus, as the drive level of the carrier amplifier 13 increases, the voltage of the signal S1 becomes a value reduced by the voltage drop at the resistor RMO4 from the voltage when the high frequency signals RF71 and RF72 are small. The signal S1 can be regarded as a signal (inversion signal) that changes in a complementary manner according to the drive level of the carrier amplifier 13. Thus, the bias of the detection circuit 22 and the circuit configurations of the variable attenuator 23 and the adder circuit 25 described above in the first to fourth embodiments can also be used in this embodiment.
As in the first modification (see
As in the second embodiment, the variable attenuator 23 may be provided in the stage preceding the detection circuit 22 in the fifth embodiment so that the drive level detection circuit 26 can output the signal S1 to the variable attenuator 23.
As in the third embodiment, the attenuator 24 may be provided in the stage preceding the variable attenuator 23 in the fifth embodiment.
As in the fourth embodiment, the adder circuit 25 may be provided in the stage following the detection circuit 22 in the fifth embodiment so that the adder circuit 25 can add the signal S4 output from the detection circuit 22 and the signal S1 output from the drive level detection circuit 26.
Component elements of a power amplifier circuit according to a sixth embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
Unlike the power amplifier circuit 1 according to the first embodiment (see
One end of the inductor 211a is electrically connected to a wire 201 between the bias circuit 15 and the control circuit 21. The other end of the inductor 211a is electrically connected to one end of the capacitor 211b. The other end of the capacitor 211b is electrically connected to the reference potential.
The series resonant circuit 211 shunts and reduces a resonant frequency component of the series resonant circuit 211 in the signal S1 to the reference potential.
Thus, the Doherty amplifier circuit 10G can reduce oscillation caused by a feedback loop.
In this embodiment, the series resonant circuit 211 includes the inductor 211a and the capacitor 211b. However, the present disclosure is not limited to this arrangement. The series resonant circuit 211 may have a circuit configuration including a resonator including a piezoelectric element.
Furthermore, in the case where the series resonant circuit 211 has a low resonant frequency, the low resonant frequency may affect communication quality. Thus, it is desirable that the resonant frequency be higher than the band width of a modulation signal.
Component elements of a power amplifier circuit according to a seventh embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
Unlike the power amplifier circuit 1 according to the first embodiment (see
The inductor 221a is inserted in series into the wire 201 between the bias circuit 15 and the control circuit 21. The capacitor 221b is electrically connected in parallel to the inductor 221a.
The parallel resonant circuit 221 reduces a resonant frequency component of the parallel resonant circuit 221 in the signal S1.
Thus, the Doherty amplifier circuit 10H can reduce oscillation caused by a feedback loop.
In this embodiment, the parallel resonant circuit 221 includes the inductor 221a and the capacitor 221b. However, the present disclosure is not limited to this arrangement. The parallel resonant circuit 221 may have a circuit configuration including a resonator including a piezoelectric element.
Furthermore, in the case where the parallel resonant circuit 221 has a low resonant frequency, the low resonant frequency may affect communication quality. Thus, it is desirable that the resonant frequency be higher than the band width of a modulation signal.
Component elements of a power amplifier circuit according to an eighth embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
Unlike the power amplifier circuit 1 according to the first embodiment (see
One end of the inductor 211a is electrically connected to a wire 202 between the control circuit 21 and the bias circuits 18 and 19. The other end of the inductor 211a is electrically connected to one end of the capacitor 211b. The other end of the capacitor 211b is electrically connected to the reference potential.
The series resonant circuit 211 shunts and reduces a resonant frequency component of the series resonant circuit 211 in the signal S2 to the reference potential.
Thus, the Doherty amplifier circuit 10I can reduce oscillation caused by a feedback loop.
In this embodiment, the series resonant circuit 211 is electrically connected to the wire 202. However, the present disclosure is not limited to this arrangement. The series resonant circuit 211 may be electrically connected to a wire 203 between the bias circuit 18 and the peak amplifier 16. Alternatively, the series resonant circuit 211 may be electrically connected to the wire 204 between the bias circuit 19 and the peak amplifier 17.
Component elements of a power amplifier circuit according to a ninth embodiment that are the same as component elements in other embodiments are denoted by the same reference signs, and description of the same component elements will be omitted.
Unlike the power amplifier circuit 1 according to the first embodiment (see
The inductor 221a is inserted in series into the wire 202 between the control circuit 21 and the bias circuits 18 and 19. The capacitor 221b is electrically connected in parallel to the inductor 221a.
The parallel resonant circuit 221 reduces a resonant frequency component of the parallel resonant circuit 221 in the signal S2.
Thus, the Doherty amplifier circuit 10J can reduce oscillation caused by a feedback loop.
In this embodiment, the parallel resonant circuit 221 is inserted into the wire 202. However, the present disclosure is not limited to this arrangement. The parallel resonant circuit 221 may be inserted into the wire 203 between the bias circuit 18 and the peak amplifier 16. Alternatively, the parallel resonant circuit 221 may be inserted into the wire 204 between the bias circuit 19 and the peak amplifier 17.
The embodiments described above are provided for easier understanding of the present disclosure and are not intended to be construed as limiting the present disclosure. The present disclosure may be altered/improved without necessarily departing from the spirit of the present disclosure and encompass equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-168430 | Oct 2021 | JP | national |
This is a continuation of International Application No. PCT/JP2022/037884 filed on Oct. 11, 2022, which claims priority from Japanese Patent Application No. 2021-168430 filed on Oct. 13, 2021. The contents of these applications are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/037884 | Oct 2022 | WO |
| Child | 18441291 | US |
