Patent Application
20240204729
This application claims priority based on Japanese Patent Application No. 2022-203419 filed on Dec. 20, 2022, and the entire contents of the Japanese patent applications are incorporated herein by reference.
The present disclosure relates to a Doherty amplifier.
A Doherty amplifier is known as an amplifier for amplifying a high frequency signal such as a microwave. In the Doherty amplifier, a main amplifier and a peak amplifier amplify input signals in parallel, and amplified signals are combined by a combiner. It is known that a chip having a main amplifier and a chip having a peak amplifier are mounted on a substrate (for example, U.S. patent Ser. No. 10/381,984).
A Doherty amplifier according to the present disclosure includes a substrate; a first transistor provided on the substrate, the first transistor including: a plurality of first gate electrodes extending in a first direction; a plurality of first drain electrodes extending in the first direction; a first gate bus bar to which a first signal of two signals obtained by dividing an input signal is input and to which the plurality of first gate electrodes are electrically connected; and a first drain bus bar provided so as to dispose the plurality of first gate electrodes and the plurality of first drain electrodes between the first gate bus bar and the first drain bus bar, the plurality of first drain electrodes being electrically connected to the first drain bus bar; a second transistor provided on the substrate, the transistor including: a plurality of second gate electrodes extending in a second direction; a plurality of second drain electrodes extending in the second direction; a second gate bus bar having a first end to which a second signal of the two signals is input, the plurality of second gate electrodes being electrically connected to the second gate bus bar; and a second drain bus bar provided so as to dispose the plurality of second gate electrodes and the plurality of second drain electrodes between the second gate bus bar and the second drain bus bar, the plurality of second drain electrodes being electrically connected to the second drain bus bar; a combining node provided on the substrate and combining the first signal amplified by the first transistor and the second signal amplified by the second transistor; a first line provided on the substrate and connecting the first drain bus bar and the combining node; and a second line provided on the substrate, connecting the second drain bus bar and the combining node, and connected to a second end of the second drain bus bar located diagonally across the second transistor with respect to the first end.
However, in the case where the main amplifier and the peak amplifier are formed on a single substrate to form a single chip, a size of the chip becomes large in order to suppress the deterioration of characteristics.
The present disclosure has been made in view of the above-described problems, and an object of the present disclosure is to reduce the size.
First, the contents of the embodiments of this disclosure are listed and explained.
Specific examples of the Doherty amplifier in accordance with embodiments of the present disclosure are described below with reference to the drawings. The present disclosure is not limited to these examples, but is indicated by the claims, which are intended to include all modifications within the meaning and scope of the claims.
The signal Si1 passes through a matching circuit 33 and is input to the main amplifier 30. The matching circuit 33 matches an impedance seen from the divider 37 to the matching circuit 33 with an impedance seen from the matching circuit 33 to the main amplifier 30. The main amplifier 30 amplifies the signal Si1 and outputs an amplified signal. A signal So1 amplified by the main amplifier 30 passes through a matching circuit 34 and is output to a node N1. The matching circuit 34 matches an impedance seen from the main amplifier 30 to the matching circuit 34 with an impedance seen from the matching circuit 34 to the node N1.
The signal Si2 passes through a matching circuit 35 and is input to the peak amplifier 32. The matching circuit 35 matches an impedance seen from the divider 37 to the matching circuit 35 with an impedance seen from the matching circuit 35 to the peak amplifier 32. The peak amplifier 32 amplifies the signal Si2 and outputs an amplified signal. A signal So2 amplified by the peak amplifier 32 passes through a matching circuit 36 and an impedance converter 38 and is output to the node N1. The matching circuit 36 matches an impedance seen from the peak amplifier 32 to the matching circuit 36 to an impedance seen from the matching circuit 36 to the impedance converter 38.
The node N1, which is a combining node, combines the signal So1 output from the main amplifier 30 and the signal So2 output from the peak amplifier 32, and outputs the combined signal as an output signal So to the output terminal Tout. A bias circuit for supplying a bias voltage to the main amplifier 30 and the peak amplifier 32 and a phase adjustment circuit for adjusting the phases of the signals So1 and So2 are not illustrated.
The main amplifier 30 and the peak amplifier 32 include transistors Q1 and Q2, respectively. The transistors Q1 and Q2 are field effect transistors (FETs). A source S of the transistor Q1 is grounded, the signal Si1 is input to a gate G of the transistor Q1, and the signal So1 is output from a drain D of the transistor Q1. A source S of the transistor Q2 is grounded, the signal Si2 is input to a gate G of the transistor Q2, and the signal So2 is output from a drain D of the transistor Q2.
The transistors Q1 and Q2 are, for example, GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or LDMOS (Laterally Diffused Metal Oxide Semiconductor). The sizes of the main amplifier 30 and the peak amplifier 32 (for example, the gate widths of the transistors Q1 and Q2) may be the same or different. For example, the gate width of the transistor Q2 is twice the gate width of the transistor Q1. At this time, a saturated electric power of the peak amplifier 32 is about twice as large as that of the main amplifier 30.
The main amplifier 30 performs class AB or class B operation, and the peak amplifier 32 performs class C operation. When the input power of the input signal Si is small, the main amplifier 30 mainly amplifies the input signal Si. When the input power becomes large, the peak amplifier 32 amplifies the peak of the input signal Si in addition to the main amplifier 30. Thus, the main amplifier 30 and the peak amplifier 32 amplify the input signal Si.
When the input power is small and the peak amplifier 32 does not operate, the matching circuit 36 substantially opens the impedance seen from the impedance converter 38 to the matching circuit 36. Therefore, the matching circuit 36 has a transmission line for converting the impedance. Thus, the impedance seen from the matching circuit 34 to the node N1 when the peak amplifier 32 operates is different from that when the peak amplifier 32 does not operate. The matching circuit 34 is designed such that the main amplifier 30 operates optimally at the saturated electric power (e.g. the efficiency is maximized) at any impedance. When the input power is large and the peak amplifier 32 operates, the matching circuit 36 is designed such that the peak amplifier 32 operates optimally at the saturated electric power (e.g. efficiency is maximized).
The impedance converter 38 is a transmission line having a length of approximately λ/4, for example (e.g. λ/8 or more and 3λ/8 or less). The “λ” is a wavelength at the center frequency of the operating band. The impedance is converted by appropriately selecting a characteristic impedance of the transmission line. The impedance seen from the matching circuit 36 to the impedance converter 38 is converted into the impedance seen from the impedance converter 38 to the node N1. The matching circuits 34 and 36 and the impedance converter 38 are set so that a phase difference between the signals So1 and So2 at the node N1 becomes small.
The transistors Q1 and Q2, the main amplifier 30, the peak amplifier 32, the matching circuits 34 and 36, the impedance converter 38 and the node N1 are provided in a semiconductor chip 100.
As illustrated in
The transistor Q1 has the plurality of source electrodes 12a (first source electrodes), the plurality of gate electrodes 14a (first gate electrodes), and the plurality of drain electrodes 16a (first drain electrodes). The source electrodes 12a, the gate electrodes 14a and the drain electrodes 16a are source fingers, gate fingers and drain fingers, respectively, and extend in the Y direction and are arranged in the X direction. In the X direction, one source electrode 12a and one drain electrode 16a are alternately provided. The gate electrode 14a is provided between one source electrode 12a and one drain electrode 16a in the X direction.
The source electrodes 12a are electrically connected to and short-circuited with a metal layer that is provided on a lower surface of the substrate 10 and supplied with a reference potential through via holes 22a. The gate electrodes 14a are electrically connected to and short-circuited to a gate bus bar 24a (first gate bus bar) at a negative end (−end) in the Y direction. The drain electrodes 16a are electrically connected to a drain bus bar 26a (first drain bus bar) at a positive end (+end) in the Y direction. The gate bus bar 24a and the drain bus bar 26a sandwich the source electrodes 12a, the gate electrodes 14a and the drain electrodes 16a. The gate bus bar 24a extends in the X direction and also serves as a gate pad. A plurality of bonding wires 25a arranged in the X direction are bonded to the gate bus bar 24a.
The transistor Q2 is provided in a region in a positive direction (+direction) of the X direction and in the negative direction (−direction) of the Y direction on the upper surface of the substrate 10. The gate width of the transistor Q2 is larger than that of transistor Q1, for example, twice the gate width of transistor Q1. The transistor Q2 has a plurality of source electrodes 12b (second source electrodes), a plurality of gate electrodes 14b (second gate electrodes), and a plurality of drain electrodes 16b (second drain electrodes). The source electrodes 12b, the gate electrodes 14b and the drain electrodes 16b are source fingers, gate fingers and drain fingers, respectively, and extend in the X direction and are arranged in the Y direction. In the Y direction, one source electrode 12b and one drain electrode 16b are alternately provided. The gate electrode 14b is provided between one source electrode 12b and one drain electrode 16b in the Y direction. The extending direction of the source electrodes 12a, the gate electrodes 14a, and the drain electrodes 16a of the transistor Q1 is substantially orthogonal to the extending direction of the source electrodes 12b, the gate electrodes 14b, and the drain electrodes 16b of the transistor Q2.
The source electrodes 12b are electrically connected to and short-circuited with a metal layer that is provided on the lower surface of the substrate 10 and supplied with a reference potential through via holes 22b. The gate electrodes 14b are electrically connected to and short-circuited to a gate bus bar 24b (second gate bus bar) at the −end in the X direction. The drain electrodes 16b are electrically connected to a drain bus bar 26b (second drain bus bar) at the +end in the X direction. The gate bus bar 24b and the drain bus bar 26b sandwich the source electrodes 12b, the gate electrodes 14b and the drain electrodes 16b. A gate pad 28 is electrically connected to a −end of the gate bus bar 24b in the Y direction. The gate pad 28 extends in the X direction, and a plurality of bonding wires 25b arranged in the X direction are bonded to the gate pad 28.
A wiring layer 27 is provided on the upper surface of the substrate 10. The wiring layer 27 forms a line 27a (first line), a line 27b, a line 27c (second line) and the node N1 (combining node). The line 27a extends in the Y direction. A −end of the line 27a in the Y direction is electrically connected near the center of the drain bus bar 26a in the X direction, and a +end of the line 27a in the Y direction is electrically connected to the node N1. Thus, the line 27a electrically connects the drain bus bar 26a and the node N1. At least a part of the line 27b also serves as the drain bus bar 26b. The line 27c extends in the X direction. A+end of the line 27c in the X direction is electrically connected to the line 27b, and a −end of the line 27c in the X direction is electrically connected to the node N1. Thus, the line 27c electrically connects the drain bus bar 26b and the node N1.
Each of the lines 27a to 27c and the metal layer provided on the lower surface of the substrate 10 forms a transmission line (microstrip line). By appropriately designing the length and the width of the line 27a, the transmission line including the line 27a forms at least a part of the matching circuit 34. By appropriately designing the length and the width of line 27b, the transmission line including line 27b forms at least a part of the matching circuit 36. By appropriately designing the length and the width of the line 27c, the transmission line including the line 27c forms the impedance converter 38 of approximately λ/4 length. Bonding wires 25c are bonded to the node N1.
The signal Si1 is input from the bonding wires 25a to the gate bus bar 24a. The signal So1 amplified by the transistor Q1 passes through the line 27a and reaches the node N1. The signal Si2 is input from the bonding wires 25b to the gate pad 28. The signal So2 amplified by the transistor Q2 passes through the lines 27b and 27c and reaches the node N1. At the node N1, the signals So1 and So2 are combined, and the combined signal So is output from the bonding wires 25c.
When the transistors Q1 and Q2 are GaN HEMTs, the substrate 10 includes, for example, a substrate and a semiconductor layer provided on the substrate. The substrate is, for example, a silicon carbide (SiC) substrate, a diamond substrate, a silicon substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. The semiconductor layer includes, for example, a gallium nitride electron transport layer and an aluminum gallium nitride (AlGaN) barrier layer provided on the gallium nitride electron transport layer. The source electrodes 12a and 12b and the drain electrodes 16a and 16b are, for example, an adhesion film (for example, a titanium film) provided on the substrate 10 and a metal film such as an aluminum film provided on the adhesion film. A wiring layer such as a gold layer may be provided on the aluminum film. The gate electrodes 14a and 14b are, for example, an adhesion film (for example, a nickel film) provided on the substrate 10 and a metal film such as a gold film provided on the adhesion film. The wiring layer 27 is, for example, a metal layer such as a gold layer.
The line 27b is provided separately from the drain bus bar 26b. A −end of the line 27b in the Y direction is electrically connected to a +end of the drain bus bar 26b in the X direction. Other configurations are the same as those of the first embodiment, and description thereof is omitted.
In the first comparative example, a signal 52a input near a −end in the X direction of the gate bus bar 24b passes through the gate electrode 14b, the drain electrode 16b, and the drain bus bar 26b near the −end of the gate bus bar 24b in the X direction. A signal 52b input near a +end in the X direction of the gate bus bar 24b passes through the gate electrode 14b and the drain electrode 16b near the +end of the gate bus bar 24b in the X direction. The signals 52a and 52b are combined near the +end in the X direction of the drain bus bar 26b and output to the line 27b as a signal 54. The signal 52a passes through the drain bus bar 26b, while the signal 52b hardly passes through the drain bus bar 26b. Therefore, a phase difference between the signals 52a and 52b becomes large. Therefore, when the signals 52a and 52b are combined, a combined loss due to the phase difference occurs.
As described above, in the second comparative example, the phase difference between the signals 52a and 52b in the transistor Q2 is less likely to occur than in the first comparative example, and the combined loss can be suppressed. However, when the width of the transistor Q2 in the X direction is large, a phase difference occurs between a signal 52c that has passed through the gate electrode 14b of the central portion in the X direction and the signals 52a and 52b. Thereby, a combined loss smaller than that of the first comparative example occurs. The lines 27a to 27c are provided on the upper surface of the substrate 10. Since the line 27c functions as the impedance converter 38, the line 27c has a length of about λ/4. The line 27b has a length that functions as the matching circuit 36. The line 27a and the lines 27b and 27c are set so that the phase difference between the signals So1 and So2 at the node N1 becomes small. Therefore, in order to secure the total length of the lines 27b and 27c, the line 27b extends in the Y direction and the line 27c extends in the X direction. As a result, an area of the substrate 10 is increased, and a size of the semiconductor chip 112 is increased. In an asymmetric Doherty amplifier, the gate width of the transistor Q2 is larger than that of the transistor Q1. In this case, an output impedance of the peak amplifier 32 becomes lower than an output impedance of the main amplifier 30. For example, the output impedance of the peak amplifier 32 is 0.8 times or less and 0.5 times or more of the output impedance of the main amplifier 30. Therefore, the line 27b functioning as the matching circuit is longer than the line 27a. Therefore, the size of the semiconductor chip 112 is more increased.
According to the first embodiment, as illustrated in
The node N1 is provided in a region located in the first direction (+direction in the Y direction) of the transistor Q1. The first end 56 is closer to the transistor Q1 than the second end 58 and is further from the node N1 than the second end 58 in the first direction (Y direction). In such an arrangement, since a distance between the second end 58 and the node N1 can be secured, the line 27c having a long line length can be provided. Therefore, the semiconductor chip can be reduced in size.
The width of the transistor Q2 in the Y direction is larger than the width of the transistor Q1 in the Y direction, and when viewed from the X direction, the transistor Q2 overlaps with the transistor Q1 and overlaps with at least a part of the line 27a. Thus, the length of the line 27a functioning as the matching circuit 34 can be secured.
When the Doherty amplifier is the asymmetric Doherty amplifier, the saturated electric power of the peak amplifier 32 is made larger than that of the main amplifier 30. Therefore, the gate width of the transistor Q2 is larger than that of the transistor Q1. In this case, the gate bus bar 24b and the drain bus bar 26b of the transistor Q2 become long, and the phase difference between the signals 52a and 52b becomes large as in the first comparative example. Therefore, by inputting the signal Si2 to the first end 56 and outputting the signal So2 from the second end 58, the combined loss can be suppressed. Further, the output impedance of the transistor Q2 is lower than the output impedance of the transistor Q1. Therefore, the line 27b is longer than the line 27a for impedance matching.
Since the gate width of the transistor Q1 is small, even if the line 27a is connected to the vicinity of the center in the X direction of the drain bus bar 26a, the phase difference between the signal passing through the gate electrode 14a near the −end in the X direction and the signal passing through the gate electrode 14a near the +end in the X direction is less likely to occur. The gate width of the transistor Q2 is, for example, 1.2 times or more and 1.5 times or more of the gate width of the transistor Q1. In addition, a portion of the line 27a close to the drain bus bar 26a has a tapered shape in which the width becomes wider as it approaches the drain bus bar 26a. As a result, the bandwidth can be widened.
Since the gate bus bar 24b and the drain bus bar 26b are long, a first direction in which the source electrodes 12a, the gate electrodes 14a and the drain electrodes 16a of the transistor Q1 extend intersects with a second direction in which the source electrodes 12b, the gate electrodes 14b and the drain electrodes 16b of the transistor Q2 extend. Thus, the length of the line 27a can be secured. Further, coupling of the high frequency signals between the transistors Q1 and Q2 is suppressed.
By making the first direction and the second direction orthogonal to each other, the semiconductor chip can be reduced in size. In addition, coupling of the high frequency signals between the transistors Q1 and Q2 is further suppressed. The term “the first direction and the second direction are orthogonal (or substantially orthogonal) to each other” means that the first direction and the second direction do not have to be geometrically orthogonal, and an angle formed by the first direction and the second direction may be within a range of 90 degrees±10 degrees.
The line 27c includes the impedance converter 38. The impedance converter 38 converts an impedance of a nearly resistive component to an impedance of a nearly resistive component having a different magnitude of resistive component. Therefore, the length of the line 27c is about λ/4 (for example, λ/8 or more and 3λ/8 or less). Therefore, the long line 27c is provided. As a result, by ensuring the distance between the drain bus bar 26b and the node N1, the semiconductor chip can be reduced in size.
Since the line 27c is connected to the end portion of the drain bus bar 26b, the drain bus bar 26b can also function as the line 27b having the function of the matching circuit 36. Thus, the semiconductor chip can be reduced in size. When the line is connected to the central portion of the drain bus bar 26b as illustrated in
By adjusting the position of the bonding wire 25c bonded to the node N1, the phase difference between the signals So1 and So2 combined at the node N1 can be reduced.
One gate electrode 14a is disposed between one source electrode 12a and one drain electrode 16a, and one gate electrode 14b is disposed between one source electrode 12b and one drain electrode 16b. Thus, the transistors Q1 and Q2 can be multi-finger transistors. In
When the saturated electric power of the peak amplifier 32 is made larger than the saturated electric power of the main amplifier 30, the transistor Q1 is the main amplifier 30 and the transistor Q2 is the peak amplifier 32. The transistor Q1 may be the peak amplifier 32, and the transistor Q2 may be the main amplifier 30.
In the third embodiment, the signal 52a of the signals 50 input to the first end 56 passes through the gate electrode 14b near the −end in the X direction, the drain electrode 16b and the drain bus bar 26b. The signal 52b of the signals 50 passes through the gate bus bar 24b, the gate electrode 14b near the +end in the X direction and the drain electrode 16b. The signals 52a and 52b are combined at the second end 58 of the drain bus bar 26b and output to the line 27c as the signal 54. The signals 52a and 52b pass through the gate bus bar 24b and the drain bus bar 26b by an equal distance, respectively. Therefore, the phase difference between the signals 52a and 52b becomes small. Therefore, when the signals 52a and 52b are combined, the combined loss due to the phase difference is less likely to occur. As a result, the deterioration of characteristics can be suppressed.
As in the third embodiment, the first direction in which the source electrodes 12a, the gate electrodes 14a, and the drain electrodes 16a of the transistor Q1 extend may be the same as the second direction in which the source electrodes 12b, the gate electrodes 14b, and the drain electrodes 16b of the transistor Q2 extend.
The embodiments disclosed here should be considered illustrative in all respects and not restrictive. The present disclosure is not limited to the specific embodiments described above, but various variations and changes are possible within the scope of the gist of the present disclosure as described in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-203419 | Dec 2022 | JP | national |
