Patent Application
20250015763
The present disclosure relates to a Doherty amplifier.
PTL 1 discloses a Doherty amplifier in which main transistors of two stages are integrated on one semiconductor chip, peak transistors of two stages are integrated on one semiconductor chip, and these semiconductor chips are mounted on a resin substrate.
Sufficient reduction of characteristic fluctuation caused by manufacturing variation is important for the amplifier in order to improve yield. The manufacturing variation generally occurs in each lot, each wafer, or each semiconductor chip. In a transistor, the manufacturing variation is caused by, for example, a parasitic capacitance Cds between a source and a drain. In a matching circuit, the manufacturing variation is caused by, for example, a MIM (Metal-Insulator-Metal) capacitance.
In the Doherty amplifier, a signal amplified by a main transistor path and a signal amplified by a peak transistor path are preferably power-combined without loss. In other words, in a case where a passing phase of the entire main transistor path is denoted by θmain, and a passing phase of the entire peak transistor path is denoted by θpeak, the passing phase θmain and the passing phase θpeak are desirably equal to each other. If a phase difference occurs between the passing phase θmain and the passing phase θpeak, combination loss occurs, and saturation output power of the Doherty amplifier is reduced. Therefore, the Doherty amplifier is generally designed such that the difference between the passing phase θmain and the passing phase Øpeak becomes zero.
In PTL 1, for example, a case where the parasitic capacitance Cds and the MIM capacitance are varied to be increased in the main transistor path, and the parasitic capacitance Cds and the MIM capacitance are varied to be reduced in the peak transistor path may occur due to semiconductor manufacturing variation. When the capacitances are increased, the passing phase is delayed, whereas when the capacitances are reduced, the passing phase is advanced. As a result, in the above-described case, the difference between the passing phase θmain and the passing phase θpeak may be excessively increased, and the saturation output power may be reduced.
An object of the present disclosure is to provide a Doherty amplifier that can suppress reduction in saturation output power caused by manufacturing variation.
A Doherty amplifier according to the first disclosure includes an input terminal; an output terminal; a first main transistor provided in a first signal path connecting the input terminal and the output terminal; a second main transistor provided on the output terminal side of the first main transistor in the first signal path; a first peak transistor provided in a second signal path connecting the input terminal and the output terminal; and a second peak transistor provided on the output terminal side of the first peak transistor in the second signal path, wherein one of the first peak transistor and the second peak transistor, and the first main transistor are provided on a first semiconductor chip, and another of the first peak transistor and the second peak transistor, and the second main transistor are provided on a second semiconductor chip.
A Doherty amplifier according to the second disclosure includes an input terminal; an output terminal; a first main transistor provided in a first signal path connecting the input terminal and the output terminal; a first peak transistor provided in a second signal path connecting the input terminal and the output terminal; a first matching circuit provided in the first signal path; and a second matching circuit provided in the second signal path, wherein the first main transistor and the first peak transistor are provided on a first semiconductor chip, and the first matching circuit and the second matching circuit are provided on a second semiconductor chip.
The Doherty amplifier according to the first disclosure, one of the first peak transistor and the second peak transistor, and the first main transistor are provided on the first semiconductor chip. The other of the first peak transistor and the second peak transistor, and the second main transistor are provided on the second semiconductor chip. As a result, the one of the first peak transistor and the second peak transistor, and the first main transistor can be caused to have similar variation. Further, the other of the first peak transistor and the second peak transistor, and the second main transistor can be caused to have similar variation. This makes it possible to suppress a phase difference between the first signal path and the second signal path.
In the Doherty amplifier according to the second disclosure, the first main transistor and the first peak transistor are provided on the first semiconductor chip, and the first matching circuit and the second matching circuit are provided on the second semiconductor chip. As a result, the first main transistor and the first peak transistor can be caused to have similar variation. In addition, the first matching circuit and the second matching circuit can be caused to have similar variation. This makes it possible to suppress a phase difference between the first signal path and the second signal path.
A Doherty amplifier according to each embodiment will be described with reference to the drawings. Identical or corresponding constitutional elements are given the same reference numerals, and the repeated description of such constitutional elements may be omitted.
The first peak transistor 41 and the first main transistor 40 are provided on a semiconductor chip 20. The second peak transistor 43 and the second main transistor 42 are provided on a semiconductor chip 22. In other words, the first peak transistor 41 and the first main transistor 40 are provided on the same semiconductor substrate. Further, the second peak transistor 43 and the second main transistor 42 are provided on the same semiconductor substrate.
In the first signal path P1, a first interstage matching circuit 50 is provided between the first main transistor 40 and the second main transistor 42. In the second signal path P2, a second interstage matching circuit 51 is provided between the first peak transistor 41 and the second peak transistor 43. The first interstage matching circuit 50 and the second interstage matching circuit 51 are provided on a semiconductor chip 21. In other words, the first interstage matching circuit 50 and the second interstage matching circuit 51 are provided on the same semiconductor substrate.
The Doherty amplifier 100 is integrated on a resin substrate 10. The input terminal 1 is connected to a circuit 30 provided on the resin substrate 10. The circuit 30 includes a divider circuit 70, an input delay line 80, an input matching circuit 90 of the main transistor, and an input matching circuit 91 of the peak transistor. The circuit 30 is connected to a gate terminal of the first main transistor 40 and a gate terminal of the first peak transistor 41 through bonding wires 60 and 64, respectively.
The semiconductor chip 20, the semiconductor chip 21, and the semiconductor chip 22 are die-bonded to a die pad 11. The semiconductor chip 20 and the semiconductor chip 21 are connected by bonding wires 61 and 65. The semiconductor chip 21 and the semiconductor chip 22 are connected by bonding wires 62 and 66. A drain terminal of the second main transistor 42 and a drain terminal of the second peak transistor 43 are connected to a circuit 31 provided on the resin substrate 10 by bonding wires 63 and 67, respectively. The circuit 31 includes a combiner circuit 71, an output delay line 81, an output matching circuit 92 of the main transistor, and an output matching circuit 93 of the peak transistor. The circuit 31 is connected to the output terminal 2.
Each of the semiconductor chips 20 and 22 is formed of, for example, a SiC substrate. Each of the first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 is, for example, a GaN-HEMT (High Electron Mobility Transistor). Each of the first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 includes a parasitic capacitance Cds between a source and a drain.
The semiconductor chip 21 is formed of an inexpensive substrate made of, for example, GaAs or Si. For example, an MIM capacitor is integrated on the semiconductor chip 21. Each of the first interstage matching circuit 50 and the second interstage matching circuit 51 includes, for example, two parallel capacitances, one series capacitance, and one series inductor. The first interstage matching circuit 50 and the second interstage matching circuit 51 may be designed in consideration of parasitic inductances of the bonding wires 61, 62, 65, and 66.
The resin substrate 10 is made of a material, for example, FR4. A thickness of the resin substrate 10 is 200 μm to 500 μm. Reduction in thickness of the resin substrate 10 enables reduction in thermal resistances of the transistors. In contrast, increase in thickness of the resin substrate 10 enables multilayer wiring. As a result, an integration degree of the circuit can be enhanced to achieve downsizing and cost reduction. Note that, in
The Doherty amplifier that has high efficiency and low distortion is used as, for example, a transmission power amplifier of a communication base station. In the Doherty amplifier 100, a main transistor biased in class AB or B and a peak transistor biased in class C are combined in parallel by using 24 lines. The λ/4 lines are arranged at an output of one of amplifiers and at an input of the other of the amplifiers. The λ/4 lines correspond to the input delay line 80 and the output delay line 81.
When a large signal is input, the main transistor and the peak transistor operate in a similar manner, and are combined in phase. Therefore, characteristics similar to characteristics of a 2-combined amplifier are obtained, and large saturation output power can be achieved. In contrast, when a small signal is input, only the main transistor operates, and the 24 line connected to the output side of the main transistor functions as an impedance inverter. Therefore, high efficiency caused by high load impedance can be achieved. Accordingly, the Doherty amplifier 100 can achieve high efficiency within a wide output power range.
Likewise, a passing phase of the entire second signal path P2 on the peak transistor side is denoted by θpeak. A passing phase from the input signal terminal to an input end of a first-stage transistor chip is denoted by θPI. A passing phase of the first-stage transistor chip is denoted by θP1. A passing phase of an interstage matching circuit is denoted by θP2. A passing phase of a final-stage transistor chip is denoted by θP3. A passing phase from an output end of the final-stage transistor to the combination point is denoted by θPO. The passing phase θmain is a sum of the passing phases θPI, θP1, θP2, θP3, and θPO.
In the Doherty amplifier, to power-combine the signal amplified by the first signal path P1 and the signal amplified by the second signal path P2 without loss, the passing phase θmain and the passing phase θpeak are required to be equal to each other. If a phase difference occurs therebetween, combination loss occurs, and the saturation output power of the Doherty amplifier is reduced.
Next, a comparative example of the present embodiment is described. As the Doherty amplifier, for example, there is an MMIC (Monolithic Microwave Integrated Circuit) in which most part of the two-stage Doherty amplifier circuit is integrated on one semiconductor chip. In a millimeter waveband, a circuit size is not generally ignorable as compared with a wavelength. Therefore, it is necessary to configure the Doherty amplifier by a distributed constant circuit. The MMIC can be manufactured with precise dimensions. Further, the Doherty amplifier can be downsized. On the other hand, in a case where a high-performance semiconductor substrate such as a GaN on SiC is used, a manufacturing cost may be increased because a chip area is large in the MMIC.
In the Doherty amplifiers 800 and 900, the parasitic capacitances Cds of the transistors and the MIM capacitance of the matching circuit may be simultaneously increased in the first signal path P1, and the parasitic capacitances Cds of the transistors and the MIM capacitance of the matching circuit may be simultaneously reduced in the second signal path P2, due to semiconductor manufacturing variation. When the capacities are increased, the passing phases are delayed, whereas when the capacities are reduced, the passing phases are advanced. In other words, the passing phases θM1, θM2, and θM3 are increased together, and the passing phases θP1, θP2, and θP3 are reduced together. As a result, a passing phase difference Δ between the passing phase θmain and the passing phase θpeak may be excessively increased. At this time, the saturation output power is reduced.
In contrast, in the present embodiment, the final-stage transistors are integrated on one semiconductor chip, the interstage matching circuits are integrated on one semiconductor chip, and the first-stage transistors are integrated on one semiconductor chip. Variation in the same chip is typically similar. Therefore, even when the parasitic capacitances Cds or the MIM capacitances are varied, each of differences θM1-θP1, θM2-θP2, and θM3-θP3 becomes a value close to zero. Accordingly, the passing phase difference Δ caused by manufacturing variation can be suppressed, and reduction of the saturation output power can be suppressed. Further, in the present embodiment, since the Doherty amplifier 100 includes the plurality of semiconductor chips, the manufacturing cost can be suppressed as compared with the MMIC.
Next, a calculation result of RF characteristic variation of the Doherty amplifier is described.
In
In contrast, in the Doherty amplifier 100 according to the present embodiment, even in consideration of all of variation combinations, the maximum value of the passing phase difference is 22 degrees, and the saturation output power is reduced by 0.3 dB at the maximum. As described above, in the present embodiment, it is found that variation of the passing phase difference Δ is suppressed, and reduction of the saturation output power is suppressed.
As a modification of the present embodiment, the first interstage matching circuit 50 and the second interstage matching circuit 51 may be provided on different semiconductor chips. Even in this case, variation of the passing phase difference Δ can be suppressed as compared with the Doherty amplifier 900 by integrating the first-stage transistors on one semiconductor chip, and integrating the final-stage transistors on one semiconductor chip.
Further, the second main transistor 42 and the second peak transistor 43 may be provided on different semiconductor chips. Even in this case, variation of the passing phase difference Δ can be suppressed by providing the first main transistor 40 and the first peak transistor 41 on one semiconductor chip 20, and providing the first interstage matching circuit 50 and the second interstage matching circuit 51 on one semiconductor chip 21.
Likewise, the first main transistor 40 and the first peak transistor 41 may be provided on different semiconductor chips. Even in this case, variation of the passing phase difference Δ can be suppressed by providing the second main transistor 42 and the second peak transistor 43 on one semiconductor chip 22, and providing the first interstage matching circuit 50 and the second interstage matching circuit 51 on one semiconductor chip 21. As described above, a part of the circuit in
In the present embodiment, the first interstage matching circuit 50 and the second interstage matching circuit 51 are provided on one semiconductor chip 21. The configuration is not limited thereto, and input matching circuits of the main transistor and the peak transistor may be provided on one semiconductor chip. In addition, output matching circuits of the main transistor and the peak transistor may be provided on one semiconductor chip.
The configurations of the first interstage matching circuit 50 and the second interstage matching circuit 51 are not limited, and the first interstage matching circuit 50 and the second interstage matching circuit 51 may have the other configurations as long as functions similar to the functions of the circuit illustrated in
The configuration of the circuit 30 is not limited as long as functions similar to the functions of the circuit illustrated in
These modifications can be applied, as appropriate, to Doherty amplifiers according to the following embodiments. Note that the Doherty amplifiers according to the following embodiments are similar to that of Embodiment 1 in many respects, and thus differences between the Doherty amplifiers according to the following embodiments and those of Embodiment 1 will be mainly described below.
The first main transistor 40 and the first peak transistor 41 at a first stage are arranged outside the second main transistor 42 and the second peak transistor 43 at a final stage. In addition, the input matching circuit 52 and 53 are arranged outside the first interstage matching circuit 50 and the second interstage matching circuit 51.
In the present embodiment, the passing phase difference Δ caused by manufacturing variation can be suppressed, and reduction of the saturation output power can be suppressed. Further, in the present embodiment, the number of chips can be reduced as compared with Embodiment 1. This makes it possible to further downsize the Doherty amplifier 200.
The first main transistor 40 and the first peak transistor 41 may have the same gate width, and the second main transistor 42 and the second peak transistor 43 may have the same gate width.
A signal from the input terminal 1 is input to the first peak transistor 41 through a divider circuit 101 and an input matching delay circuit 102. The input matching delay circuit 102 has functions of an input matching circuit and a delay circuit. The signal from the input terminal 1 is also input to the first main transistor 40 through the divider circuit 101 and an input matching circuit 103. The functions of the divider circuit 101, the input matching delay circuit 102, and the input matching circuit 103 are similar to the functions of the circuit 30.
A signal from the second main transistor 42 is output from the output terminal 2 through an output matching delay circuit 104 and a combiner circuit 106. The output matching delay circuit 104 has functions of an output matching circuit and a delay circuit. A signal from the second peak transistor 43 is output from the output terminal 2 through an output matching circuit 105 and the combiner circuit 106. The functions of the output matching delay circuit 104, the output matching circuit 105, and the combiner circuit 106 are similar to the functions of the circuit 31.
In the present embodiment, even when the parasitic capacitances Cds or the MIM capacitances are varied, it is possible to suppress each of differences θM3−θP1, θM2−θP2, and θM1−θP3. Accordingly, the passing phase difference Δ caused by manufacturing variation can be suppressed, and reduction of the saturation output power can be suppressed.
Further, the first main transistor 40 and the first peak transistor 41 have the same transistor size, and the second main transistor 42 and the second peak transistor 43 have the same transistor size. Therefore, as the semiconductor chip 420 and the semiconductor chip 422, the semiconductor chip of the same type or the same specification can be used. In other words, the semiconductor chip 420 and the semiconductor chip 422 can be acquired from the same wafer.
As the semiconductor chip 420 and the semiconductor chip 422, for example, chips adjacent to each other on the wafer are used, which makes it possible to further suppress semiconductor manufacturing variation between the chips. In Embodiment 1, it is necessary to prepare two types of semiconductor chips 20 and 22. In contrast, in the present embodiment, it is sufficient to prepare one type of semiconductor chips 420 and 422. Therefore, this makes it possible to enhance productivity.
As a modification of the present embodiment, the first interstage matching circuit 50 and the second interstage matching circuit 51 may be provided on different semiconductor chips. Even in this case, variation of the passing phase difference Δ can be suppressed as compared with the Doherty amplifier 900 by integrating the first main transistor 40 and the second main transistor 43 on one semiconductor chip, and integrating the second main transistor 42 and the first peak transistor 41 on one semiconductor chip.
Further, the second main transistor 42 and the first peak transistor 41 may be provided on different semiconductor chips. Even in this case, variation of the passing phase difference Δ can be suppressed by providing the first main transistor 40 and the second peak transistor 43 on one semiconductor chip 420, and providing the first interstage matching circuit 50 and the second interstage matching circuit 51 on one semiconductor chip 21.
Likewise, the first main transistor 40 and the second peak transistor 43 may be provided on different semiconductor chips. Even in this case, variation of the passing phase difference Δ can be suppressed by providing the second main transistor 42 and the first peak transistor 41 on one semiconductor chip 422, and providing the first interstage matching circuit 50 and the second interstage matching circuit 51 on one semiconductor chip 21. As described above, a part of the circuit in
An interval between the bonding wires is narrowed on the semiconductor chip 20 side and on the semiconductor chip 22 side on which the transistors are integrated. In other words, an interval between the bonding wires 61 and 65 connecting the semiconductor chip 20 and the semiconductor chip 21 adjacent to the semiconductor chip 20 is widened toward the semiconductor chip 21. Likewise, an interval between the bonding wires 62 and 66 connecting the semiconductor chip 22 and the semiconductor chip 21 adjacent to the semiconductor chip 22 is widened toward the semiconductor chip 21.
In a case where two transistors are integrated on one semiconductor chip, the transistors are adjacent to each other. As a result, the bonding wires connected to the transistors are also adjacent to each other. Electromagnetic fields of the bonding wires adjacent to each other are coupled, which may deteriorate the RF characteristics. In the present embodiment, the bonding wires adjacent to each other are arranged so as not to be parallel to each other, which makes it possible to suppress electromagnetic field coupling between the wires while suppressing the chip sizes.
Further, narrowing the interval between the bonding wires on the semiconductor chip 20 side and on the semiconductor chip 22 side makes it possible to downsize the semiconductor chips 20 and 22. As a result, the Doherty amplifier 500 can be manufactured at low cost.
An output of the second peak transistor 743 is connected to the drain pad 121 arranged perpendicularly to a gate pad through a lead-out line 120. The bonding wire 67 connected to the drain pad 121 is connected to the circuit 31 through a pad 123. The bonding wire 67 connected to the drain pad 121 of the second peak transistor 743 is inclined by 90 degrees or more relative to the bonding wire 63 connected to the drain pad of the second main transistor 42. The other configurations are similar to the configurations in Embodiment 4.
The Doherty amplifier 700 according to the present embodiment is an asymmetric Doherty amplifier in which a total gate width of the second peak transistor 743 is greater than a total gate width of the second main transistor 42. The asymmetric Doherty amplifier can achieve high efficiency at lower output power as compared with a symmetric Doherty amplifier.
In a case where the transistors having different unit gate widths W1 are integrated on one semiconductor chip, there is an issue that a blank space is generated by a difference of the unit gate widths W1. In the present embodiment, the thin lead-out line 120 for the output signal of the second peak transistor 743 is laid up to center of the semiconductor chip 22. This makes it possible to provide the drain pad 121 between the second main transistor 42 and the second peak transistor 743. Accordingly, it is possible to prevent the semiconductor chip 22 from becoming long in the signal propagation direction, and to reduce the blank space caused by the difference of the unit gate widths. In addition, the interval between the bonding wires 62 and 66 can be widely secured, and the electromagnetic field coupling can be suppressed. Further, the electromagnetic field coupling between the bonding wires 63 and 68 can also be suppressed. Note that the technical features described in the above embodiments may be combined as appropriate.
1 input terminal, 2 output terminal, 10 resin substrate, 11 die pad, 20, 20a, 21, 22, 22a, 23, 24 semiconductor chip, 30, 31 circuit, 40 first main transistor, 41 first peak transistor, 42 second main transistor, 43 second peak transistor, 50 first interstage matching circuit, 50a interstage matching circuit, 51 second interstage matching circuit, 51a interstage matching circuit, 52, 53 input matching circuit, 60˜68 bonding wire, 70 divider circuit, 71 combiner circuit, 80 input delay line, 81 output delay line, 90, 91 input matching circuit, 92, 93 output matching circuit, 100 Doherty amplifier, 101 divider circuit, 102 input matching delay circuit, 103 input matching circuit, 104 output matching delay circuit, 105 output matching circuit, 106 combiner circuit, 120 line, 121, 122 drain pad, 123 pad, 200 Doherty amplifier, 220, 221 semiconductor chip, 300, 400 Doherty amplifier, 420, 422 semiconductor chip, 500, 600, 700 Doherty amplifier, 743 second peak transistor, 800, 900 Doherty amplifier, Cds parasitic capacitance, P1 first signal path, P2 second signal path, W1 unit gate width, Δ passing phase difference
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/015098 | 3/28/2022 | WO |
