DOHERTY AMPLIFIER

Abstract

An N-way Doherty Amplifier (N>3) is disclosed. The Doherty Amplifier includes an N-way power divider that evenly divides an input signal, a delay adjustor, one carrier amplifier and N-1 peak amplifiers each including offset lines for converting output impedance thereof to be substantially short circuit when the amplifiers are turned off, and an output combiner including a common node. The carrier amplifier, the first peak amplifier, and the rest peak amplifiers are coupled with the common node directly, through one λ/4 line, and respective λ/4 lines connected in series to the common node, respectively. The delay adjustor makes up a number of λ/4 lines in respective paths.

Description

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a Doherty amplifier, in particular, relates to Doherty amplifiers having two or more peak amplifiers.

2. Related Prior Arts

In most communication systems, a power amplifier is requested to be operable in high efficiencies with high linearity. However, the efficinecy and the linearity in an amplifier generally show a tradeoff relation. Besides, many wireless communications systems, such as GSM (Global

System Mobile communication)/EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access)/LTE (Long Tei in Evolution), or the like, require that a power amplifier is able to deliver a wide range of output power. As a result, when the highest power level is designed accompanied with maximum available efficiency, the power amplifiers implemented in base stations tend to show lesser efficiently at lower power levels, which resuts in consumption of a lot of extra dc power. Accordingly, it is a real challenge to design a power amplifier implemented within the base station that has high efficiency not only at maximum output power but also at lower power levels typically ranging from −6 dB and less, with minimum size and lower cost.

SUMMARY OF INVENTION

The present invention relates to an N-way (N>3) Doherty Amplifier coupled with a load that has characteristic impedance of Z₀. The N-way Doherty Amplifier comprises a carrier amplifier (CA), (N−1) counts of peak amplifiers (PAs), an N-way power divider, a phase compensator, and an output combiner. The carrier amplifier includes an offset line with characteristic impedance in an output thereof. The offset line convers output impedance of the carrier amplifier into a substantially short-circuit when the carrier amplifier is turned off. The (N−1) counts of peak amplifiers include a first, second, and rest N−2 peak amplifiers. Each of the peak amplifiers has a configuration same with a configuration of the carrier amplifier and includes an offset line in an output thereof that converts output impedance thereof into a substantially short circuit when the peak amplifier being turned off. The N-way power divider evenly divides an input signal into N-counts of divided signals each provided to the carrier amplifier and the peak amplifiers each having phases substantially aligned to each other. The phase compensator includes a first quarter-wavelength line corresponding to the carrier amplifier, a second quarter-wavelength line corresponding to a first peak amplifier, and other quarter-wavelength lines corresponding to the rest peak amplifiers. The first quarter-wavelength line has an electrical length of (N−2)*λ/4, where λ is a wavelength of the input signal. The second quarter-wavelength line has an electrical length of (N−3)*λ/4. The other quarter-wavelength lines have an electrical length of (N−k−1)*λ/4, where k is a consecutive number from 2 to N−1. The quarter-wavelength lines have the characteristic impedance Z₀. The output combiner includes a common node and (N−1) counts of quarter-wavelength lines including a first and rest quarter-wavelength lines each corresponding to the first peak amplifier and the rest peak amplifiers, respectively. The carrier amplifier is directly coupled with the common node. The first peak amplifier is coupled with the common node through the first quarter-wavelength line. The j-th peak amplifier, j=2 to N−1, in the rest peak amplifiers is coupled with the common node through i-th quarter-wavelength lines, i=j−1 to 2, that are connected in series to the common node.

BRIEF DESCRIPTION OF DRAWINGS

The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

FIG. 1 shows a functional block diagram of a conventional multi-way Doherty amplifier that is comparable with the present invention;

FIG. 2 shows a functional block diagram of a Doherty amplifier according to the first embodiment of the present invention;

FIG. 3 shows a functional block diagram of a Doherty amplifier according to the second embodiment of the present invention;

FIG. 4 shows a functional block diagram of a Doherty amplifier modified from the second embodiment shown in FIG. 3; and

FIG. 5A schematically shows a circuit diagram of an offset unit for a carrier amplifier and a peak amplifier, and FIG. 5B shows an impedance behavior of the offset unit shown in FIG. 5A.

DESCRIPTION OF EMBODIMENTS

FIG. 1 schematically shows the functional block diagram of a conventional four-way Doherty amplifier that implements amplifiers having sizes of 1:1:1:1, where one carrier amplifier (CA) 10₀ and three peaking amplifiers (PAs), 10₁ to 10₃, are combined in a four-way Doherty configuration. The configuration of the Doherty amplifier 100 shown in FIG.1 shows the maximum efficiency at back-off of −12 dB from the saturation. In the arrangement of FIG. 1, all amplifiers, 10₀ to 10₃, are turned on at saturation, and only the CA 10₀ is turned on so as to show the maximum efficiency at the back-off that is smaller than the saturation by 12 dB where the CA 10₀ sees the load of 200 Ω for R_L=Z₀₄=Z₀₅=Z₀₈=50 Ω. The CA 10₀ is biased in Class AB to perform linear amplification for low envelope signals, while the PAs, 10₁ to 10₃, are biased in Class C with different bias voltages below the threshold to amplify the higher envelope signals. The input power divider includes three quadrature couplers, 20a to 20c, that split input power equally over the CA 10₀ and the PAs, 10₁ to 10₃, and provide the required phase shifts. Each of the PAs, 10₁ to 10₃, also includes the output matching circuit and offset lines therein to provide the high impedance viewed from the outputs thereof when the respective PAs, 10₁ to 10₃, are turned off.

However, in view of presence of the parasitic components around the amplifiers or transistors implemented within the amplifiers, such as shunt output capacitance, a bonding wire connected in series thereto, and lead inductor of the packages; the PAs, 10₁ to 10₃, in the output thereof easier provide a characteristic of a short circuit rather than an open circuit in a low-power region at turning off. In such a case, the shunt capacitance and series inductance compose the series resonant circuit with the series resonance frequency close to the carrier frequency subject to the Doherty amplifier. Using an additional offset line with a short-length; the resonant point may be properly tuned to the carrier frequency. Accordingly, the overall structure of the four-way Doherty amplifier may be simplified for practical implementation providing the maximum efficiency peak at the back-off point smaller by 12 dB from the saturation. Besides, a difference in the characteristic impedance between Z₀₆ and Z₀₈ in FIG. 1 becomes significant, with ratio of 3 in a 50 Ω environment when Z₀₄=Z₀₅=Z₀₈=50 Ω while Z₀₇=25 Ω and Z₀₆=16.7 Ω.

First Embodiment

FIG. 2 schematically shows a functional block diagram of the inverted four-way Doherty configuration with the device size ratio of 1:1:1:1,where the maximum ratio between the transmission-line characteristic impedances of 50 Ω/25 Ω=2 only in a 50 Ω environment when Z₀=R_L=50 Ω. Three quadrature couplers, 20a to 20c, are used at the input to equally split the input signal over four amplifiers, 10₀ to 10₃. The description below assumes that the CA means the carrier amplifier, and PA₁ to PA₃ mean the first to third peaking amplifiers, 10₁ to 10₃, respectively. All amplifiers, 10₀ to 10₃, include the input and output matching circuits, whose configurations fully depend on the corresponding device impedances for particular applications to match to 50 Ω source and the load impedance.

The offset unit 30 is necessary to provide the low impedance at outputs thereof when the PAs, 10₁ to 10₃, are turned off. All amplifiers, 10₀ to 10₃, are turned on at the saturation, while only the CA is turned on but the PAs, 10₁ to 10₃, are turned off to provide a peak efficiency of the Doherty amplifier 1 at a back-off that is smaller by 12 dB from the saturation. The CA 10₀ and only the first PA 10₁ are turned on to provide efficiency peak at another output power back-off that is smaller by 6 dB from the saturation, then, the CA 10₀ and two PAs, 10₁ and 10₂, are turned on for providing another peak efficiency at an output power smaller than the saturation but higher than the second back-off level, namely, smaller than the saturation by 6 dB. In a low power region where all PAs, 10₁ to 10₃, are turned off, the output matching circuit of CA in conjunction with the corresponding series quarter-wavelength line TLRo in the offset unit 30 should provide the impedance transformation when the high impedance is seen by the transistor in the CA 10₀. An additional efficiency peak at the power level smaller than the saturation by 6 dB may be achieved by turning off the PA₃ but the CA, the PA₁ and the PA₂ are turned on. The common node N₀ in the output combiner 40 is coupled to the load with impedance of 50 Ω through the Ω/4 impedance converter TL_T.

In lower output power where only the CA 10₀ operates, all of the PAs, 10₁ to 10₃, are turned off so as to show output impedance thereof large enough; but the devices in the PAs, 10₁ to 10₃, are strictly not regarded as an open circuit. For instance, when the peak amplifiers, 10₁ to 10₃, are configured with respective field effect transistor (FET), a junction capacitor between the drain and the source thereof, parasitic inductance due to bonding wires wire-boned with the drain electrode, and so on makes the output impedance of the FET not to be an open circuit. FIG. 5A schematically illustrates a primary portion of a circuit diagram around an FET implemented within the amplifiers, 10₀ to 10₃, while, FIG. 5B indicates a smith chart of the circuit shown in FIG. 5A.

The FET in the amplifier inevitably accompanies with the junction capacitance between the drain and the source, and the inductance due to the bonding wire to extract an output from the drain. Assuming the output impedance of the FET seeing the inside at the drain thereof to be Z_{OUT_OFF}, this impedance Z_{OUT_OFF} shifts from the open circuit ∞ on the smith chart as shown in FIG. 5B. Referring to FIG. 5A, the FET in the drain thereof couples with a matching circuit including, for instance, a capacitor C and an inductor L, where the capacitor C is not the junction capacitance between the drain and the source of the FET but the inductor L corresponding to the inductance attributed to the bonding wire connected between the drain of the FET and the offset transmission line TL_On. The matching circuit moves, or rotates clockwise from the Z_{OUT_OFF} to the Z_{LC_OFF}, that is, the impedance Z_{LC_OFF} corresponds to impedance seeing the FET at the end of the offset transmission line TL_On.

The offset transmission lines, TL₀₀ to TL₀₃, in the offset unit 30 have the electrical length corresponding to rotate the point Z_{LC_OFF} to the short circuit (Z=0). Because the point Z_{LC_OFF} positions in the edge on the smith chart, the offset transmission lines, TL₀₀ to TL₀₃ , have the characteristic impedance of Z₀, and the electrical length L_OFF so as to rotate the point from the point Z_{LC_OFF} to the short circuit (Z=0) in the left end, where an example shown in FIG. 5B has the electrical length about λ/16.

Second Embodiment

FIG. 3 shows a general extension of the basic four-way Doherty arrangement to an N-way Doherty arrangement in a general form thereof where the general form of a Doherty amplifier 1A comprises one CA 10₀ that is coupled with the common node N₀ through an offset line TLR₀, the first peaking amplifier 10₁ that is coupled with the common node No through the offset line TLR₁ and the quarter-wavelength line TLO₁. The arrangemnet shown in FIG. 3 further includes N−2 counts of the PAs, 10₂ to 10_N−1, that are coupled with the common node No through offsett lines, TLR₂ to TLR_N−1, and λ/4 impedance converters, TLO₂ to TLO_N−1, each connected in series to the common node N₀.

Specifically, the first quarter-wavelength line TLI₀ has a length of (N−2)×λ/4, the second quarter-wavelength line TLI₁ has a length of (N−3)×λ/4; while, other quarter-wavelength lines corresponding to the PAs 10_k, k=2 to N−1, have lengths of (N−k−1)* λ/4, respectively. According to the arrangement for the phase compensator 50 thus described, the quarter-wavelength line for the second PA 10₂, namely k=2, has the length of (N−3)*λ/4, which is equal to the quarter-wavelength line TLI₁ for the first PA 10₁; that for the PA 10_N−3 has the length of (N−N+3−1)*λ/4=2*λ/4; that for the PA 10_N−2 has the length of (N−N+2−1)*λ/4=λ/4;and that for the last PA 10_N−1 has no length. That is, the phase compensator 50 omits the quarter-wavelength line in the Nth path.

The amplifiers, 10₀ to 10_{N −1}, in outputs thereof are coupled with the common node N₀ through the offset lines, TLRto TLR_N−1, and quarter-wavelength lines, TLO₁ to TLO_N−1. The functions of the offset lines, TLR₀ to TLR_N−1, are same with those already described in FIG. 5; that is, the offset lines, TLO₀ to TLO_N−1, convert the impedance of the PAs, 10₁ to 10_N−1, in a short circuit when the PAs, 10₁ to 10N_1, are turned off. The first offset line TLR₀ for the CA 10₀ is directly coupled with the common node N₀, while, the offset line TLR₁ for the first PA 10₁ is coupled with the common node through the quarter-wavelength line TLO₁. Rest of the offset lines, TLR₂ to TLR_N−1, are coupled with the common node through offset lines set upstream to the common node N₀. That is, the third offset line TLR₂ is coupled with the common node N₀ through the quarter-wavelength line TLO₂; and generally, the k-th offset line TLR_k, k=2 to N−1, is coupled with the common node N₀ through the impedance converters TLO_j, j=k to 2. Accordingly, the last offset line TLR_N−1 for the last PA 10_N−1 is coupled with the common node N₀ through the impedance converters, TLO_N−1 to TLO₂.

Thus, the first path that includes the CA 10₀ has (N−2) counts of the quarter-wavelength lines from the N-way power divider 20 to the common node N₀; the second path that includes the first PA 10₁ also has (N−2) counts of the quarter-wavelength lines; third path for the second PA 10₂ also has (N−2) counts of the quarter-wavelength lines; and the Nth path for the last PA 10N−1 also has (N−2) counts of the quarter-wavelength lines. Accordingly, signals passing through the respective paths are aligned in the phases thereof at the common node No.

The common node N₀ is coupled with the load whose impedance is Zo through the λ/4 impedance converter TLT whose impedance ZT is given by:

Z_r=Z₀/√{square root over (N)}, where Z₀=50 Ω and N is the total number of the amplifiers, namely, the count of the PAs plus one (1) for the CA 10₀.

In some cases, especially when the CA 10₀ is necessary to output very high power with small impedance at the output thereof, the CA 100 becomes hard to be physically connected to the common node N₀ through no substantial length. In such a case, the CA 10₀ in the output thereof may interpose an additional transmission line TLO₀ with a half wavelength λ/2 for a signal subject to the Doherty amplifier 1B between the offset line and the common node N₀ as shown in FIG. 4.

In summary, the Doherty amplifier of the present invention provides an N-way inverted configuration, where one embodiment of the Doherty amplifier provides the four-way configuration that includes one CA 10₀ and three PAs, 10₁ to 10₃, the input power divider 20, the offset unit 30, and the output combiner 40. Each of the CA 10₀ and the PAs, 10₁ to 10₃, has input and output matching circuits therein. The CA 10₀ and the PAs, 10₁ to 10₃, are configured to operate such that the PAs, 10₁ to 10₃, sequentially switch as an increase of the input power in this turn.

The N-way power divider 20 is coupled between an input terminal RFIN and respective inputs of the CA 10₀ and the PAs, 10₁ to 10₃. The outputs of the CA 10₀ and the PAs, 10₁ to 10₃, are coupled with an output terminal RFour through the offset unit 30 and the output combiner 40. The CA 10₀ is coupled with the common node N₀ through the offset line TLR₀ in the first path without any impedance inverters, namely, quarter-wavelength lines. The second path is coupled with the common node N₀ from the first PA 10₁ through the offset line TLR₁ and the impedance converter TLO₁ with a quarter-wavelength. Each of the remaining paths includes a PA 10_k(k=2 to N−1), the offset line TLRk (k=2 to N−1), and the impedance converters, TLO_J (j=k to 2). The PAs, 10₁ to 10_N−1, are connected in parallel with respect to the common node N₀ through the impedance converters TLO_j(j−k to 2), where the impedance converter TLO_k provides an open circuit in the output thereof when the PA_k is turned off because the output of the offset line TLR_k may be regarded as substantially a short circuit. The impedance of each of the impedance converters TLOk is selected to provide the power combining when the CA 10₀ and all N−1 counts of the PAs, 10₁ to 10_N−1, are turned on. The common node N₀ is coupled with the load through the impedance converter TL_T with a quarter wavelength whose impedance depends on a number of the PAs, 10₁ to 10_N−1.

Although this invention has been described in certain specific exemplary embodiments, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that this invention may be practiced otherwise than as specifically described. Thus, the present embodiments of the invention should be considered in all respects as illustrative and not restrictive, the scope of the invention to be determined by the appended claims and their equivalents.

Claims

1. An N-way Doherty Amplifier coupled with a load having characteristic impedance of Z0, where N is an integer greater than three (3), the N-way Doherty Amplifier comprising: a carrier amplifier including an offset line with characteristic impedance in an output thereof, the offset line converting output impedance of the carrier amplifier into a substantially short-circuit when the carrier amplifier is turned off;(N−1) counts of peak amplifiers including a first peak amplifier, a second peak amplifier, and rest peak amplifiers, the peak amplifiers having configuration same with a configuration of the carrier amplifier, each of the peak amplifiers including an offset line in an output thereof to convert output impedance thereof into a substantially short circuit when the peak amplifier being turned off;an N-way power divider that evenly divides an input signal into N-counts of divided signals each provided to the carrier amplifier and the peak amplifiers, the divided signals having phases aligned from each other;a phase compensator that includes a first quarter wavelength line corresponding to the carrier amplifier, a second quarter-wavelength line corresponding to a first peak amplifier, and other quarter-wavelength lines corresponding to the rest peak amplifiers, the first quarter-wavelength line having an electrical length of (N−2)*λ/4, where λ is a wavelength of the input signal, the second quarter-wavelength line having an electrical length of (N−3)*λ/4, the other quarter-wavelength lines having an electrical length of (N−k−1)*λ/4, k=2 to N−1, the quarter-wavelength lines having the characteristic impedance; andan output combiner including a common node and (N−1) counts of quarter-wavelength lines including a first quarter-wavelength line and rest quarter-wavelength lines that correspond to the first peak amplifier and the rest peak amplifiers, respectively, the carrier amplifier being directly coupled with the common node, the first peak amplifier being coupled with the common node through the first quarter-wavelength line, j-th peak amplifiers, j=2 to N−1, in the rest peak amplifiers being coupled with the common node through i-th quarter-wavelength lines, i=j to 2, that are connected in series with respect to the common node.

2. The N-way Doherty amplifier according to claim 1, wherein the output combiner further includes an additional line having an electrical length of λ/2, the carrier amplifier being coupled with the common node through the additional line.

3. The N-way Doherty amplifier according to claim 1, wherein the j-th quarter-wavelength line in the output combiner has impedance of Z0/(N−j).

4. The N-way Doherty amplifier according to claim 1, further including an output quarter-wavelength line provided between the common node and the load, the output quarter-wavelength line having an electrical length of λ/4 and impedance of Z0/√N.

5. A 4-way Doherty Amplifier coupled with a load having characteristic impedance of Z0, the 4-way Doherty Amplifier comprising: a carrier amplifier including an offset line with characteristic impedance in an output thereof, the offset line converting output impedance of the carrier amplifier into substantially short circuit when the carrier amplifier is turned off;a first peak amplifier, a second peak amplifier, and a third peak amplifier, the first to third peak amplifiers having a configuration same with a configuration of the carrier amplifier, each of the first to third peak amplifiers including an offset line in an output thereof that converts output impedance of the peak amplifiers into substantially short circuit when the peak amplifiers being turned off;an input power divider that evenly divides an input signal into carrier amplifier and the first to third peak amplifiers as relatively delaying a phase of n for the carrier amplifier, π/2 for the first and second peak amplifiers, and 0 for the third peak amplifier; andan output combiner including a common node, a first quarter-wavelength line, a second quarter-wavelength line, and third quarter wave line each corresponding to the first to third peak amplifiers, respectively, the carrier amplifier being directly coupled with the common node, the first peak amplifier being coupled with the common node through the first quarter-wavelength line, the second peak amplifier being coupled with the common node through the second quarter-wavelength line, and the third peak amplifier being coupled with the common node through the second and third quarter-wavelength lines that are connected in series against the common node.

6. The 4-way Doherty amplifier according to claim 5, wherein the input power divider includes three quadrature couplers, one of which receives an input signal and rest two couples are coupled parallel with the one of the coupler, the rest two couplers outputting four divided signal each having relative phase of π, π/2, π/2, and 0.

7. The 4-way Doherty amplifier according to claim 5, wherein the output combiner further includes an additional line having an electrical length of λ/2, the carrier amplifier being coupled with the common node through the additional line.

8. The 4-way Doherty amplifier according to claim 5, wherein the second quarter-wavelength line in the output combiner has impedance of Z0/2 and the third quarter-wavelength line in the output combiner has the characteristic impedance.

9. The N-way Doherty amplifier according to claim 5, further including an output quarter-wavelength line provided between the common node and the load, the output quarter-wavelength line having an electrical length of λ/4 and impedance of Z0/2.