Patent Application
20180254747
The present invention relates to a Doherty amplifier.
Higher demand for data rates as increasing end-users to ensure seamless usage on mobile phones has requested to adopt further complex forms of signal algorithms, which results in modern mobile signals having extremely large Peak-to-Average signal ratios (PAR). However, when an amplifier architecture applied thereto is neither suitable nor capable of efficiently amplifying such signals to the end-users, an amplifier implemented therein would result in large thermal dissipation and energy consumption. There is currently a practical limit to implementation of such complex signal formats due to hardware limitations, for instance operable speed of Field Programmable Gate Array (FPGA), Digital to Analog Converter (DAC), Analog to Digital Converter (ADC), and so on.
In order to address the increasing demand for supporting user capacity, mobile operators have adopted the simplest and a most cost efficient solution of increasing the spectral power. As a result, amplifier solutions need to be able to provide both average power and efficiency, as well and addressing the large signal peaks.
In order to address high powers (average and peak); an ideal and simple solution is to use a transistor having an enhanced die size. Unfortunately, a transistor with an enhanced die size inherently has subjects below to be solved:
Effective thermal dissipation of the transistor chip itself has serious challenges and extremely large transistor devices, for instance, the power consumption thereof greater than 500 W in the single-ended from, is almost impossible to be available in the market. Amplifier designers are limited to select devices and architectures to address the power (average and peak) demands.
Considering a requirement of an average power of 100 W, with a signal PAR of 10, the amplifier architecture needs to be capable to be operable up to 1 kW in RF power. As mentioned above, no known transistor devices/dies in single-ended form in excess of 500 W is available in the market. Table below illustrates the options (prior arts) based on existing largest transistor device/die in single-ended form that are operable in excess 250 W.
An aspect of the present invention relates to a Doherty amplifier. The Doherty amplifier has a back-off level that is smaller than a present amount from saturated power in an output thereof. The Doherty amplifier includes a carrier amplifier (CA), a peak amplifier (PA), a combining node, a transmission line, and a impedance line. The CA, which amplifies an input RF signal, saturates output power thereof at the back-off level. The PA, which has characteristics identical with the CA, is configured to show a substantial leak when the Doherty amplifier shows an output thereof smaller than the back-off level. The PA saturates output power thereof at the saturated power. The combining node combines an output of the CA with the PA. The transmission line, which is provided between the CA and the combining node, has an electrical length of π/2 radian, namely, a quarter-wavelength (λ/4) of the input RF signal. A feature of the Doherty amplifier of the present invention is that the impedance line increases impedance viewing the peak amplifier from the combining node when the Doherty amplifier in the output power thereof is smaller than the back-off level.
The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Next, configurations and operations of a Doherty amplifier according to an embodiment of the present invention will be described as referring to accompanying drawings.
The carrier amplifier 100 in the output thereof is coupled with a combining node N0 through a transmission line TL1 having an electrical length of π/2 radian, namely, a quarter-wavelength (λ/4) of the RF signal subject to the present Doherty amplifier, which means that the signal rotates a phase thereof by π/2 radian during the propagation on the transmission line. While, the two peak amplifiers, 101 and 102, in outputs thereof also couple with respective lines, ZP1 and ZP2, where the lines, ZP1 and ZP2, in electrical lengths thereof are unnecessary to be set in π/2 radian but impedance thereof is set higher than characteristic impedance (ZN0) at the combining node N0 and the characteristic line impedance of TL2 (ZTL2).
In an general design of a Doherty amplifier, when an RF signal is small such that a peak amplifier is turned off, which means that impedance viewing the peak amplifier at the combining node becomes substantially infinite, the carrier amplifier in an output thereof is extracted through two transmission lines, TL1 and TL2, each having electrical lengths of π/2 radian. Increasing the power of the input RF signal so as to turn on the peak amplifier, that is, at the back-off level, the impedance of the peak amplifier viewing from the combining node becomes substantial, and that viewing from the carrier amplifier to the combining node gradually decreases. At saturation where the carrier amplifier and the peak amplifier generate respective maximum power, the impedance viewing from the carrier amplifier to the combining node N0 and that viewing from the peak amplifier to the combining node N0 presents constructive impedance that may be represented by an equation of:
Z
N0
=Z
TL2
2
/Z
signal
_
out,
where Zsignal_out is generally 50Ω but not restricted thereto.
However, increasing a size of a transistor implemented in the amplifiers, for instance, a transistor with a type of Field Effect Transistor (FET) and a gate width thereof becomes longer; a signal leak from a drain to a source of the FET due to parasitic capacitance therebetween becomes substantial even when the FET in the gate thereof is biased to turn of the FET. This signal leak becomes large not only as the FET becomes large but the RF signal in a frequency thereof becomes higher.
The lines, ZP1 and ZP2, coupled with the peak amplifiers, 101 and 102, having higher impedance are provided for suppressing signal leak from the drain to the source when the peak amplifiers, 101 and 102, are unable to be reliably turned off. The impedance viewing from the combining node N0 to the peak amplifiers, 101 and 102, becomes substantial even when the peak amplifiers, 101 and 102, have sizes, or gate widths thereof, large enough and are biased so as to be turned off.
When the lines, ZP1 and ZP2, with the high impedance exist between the peak amplifiers, 101 and 102, and the peak amplifiers, 101 and 102, do not implement output matching circuits, the impedance configuration at the combining node N0 becomes those shown in
The amplifiers, 100 to 102, accompany with gate patterns, 10G to 12G, that receive gate biases from respective gate pads, VG0 to VG2, where the gate pads, VG0 to VG2, are connected with the gate patterns, 10G and 12G, immediate to the amplifiers, 100 to 102. The gate pads, VG0 to VG2, are accompanied with ground patterns GND and bypassing capacitors are connected between the gate pads, VG0 to VG2, and the ground patterns GND. The ground patterns GND is electrically connected with a back metal in the input board 1A, which is grounded in a practical operation, through ground vias in the input board 1A.
In the output board 1B, the carrier amplifier 100 in the output thereof is extracted through an output pattern 10D, to which output lead terminals of the carrier amplifier 100 are directly attached. The output pattern 10D is coupled with a combining node N0 through a coupling capacitor CD0 and the transmission line TL1, where the coupling capacitor CD0 cuts DC or low frequency (LF) components contained in the signal output from the carrier amplifier 100; while, the transmission line TL1 has a quarter wavelength (λ/4), that is the transmission line TL1 is an impedance converter.
On the other hands, the peak amplifiers, 101 and 102, which also have two output lead terminals directly connected with the respective output patterns, 11D and 12D, are coupled with the combining node N0 through the output patterns, 11D and 12D, coupling capacitors, CD1 and CD2, and high-impedance lines, ZP1 and ZP2. The high-impedance lines, ZP1 and ZP2, are directly coupled with the combining node N0 without interposing any conductive lines. That is, the high-impedance lines, ZP1 and ZP2, extend diagonally from the coupling capacitors, CD1 and CD2, to the combining node N0. The transmission line TL1 also directly couples with the combining node N0; that is, one of ends of the transmission line TL1 is terminated at the combining node N0. The combining node N0 couples with the output terminal of the Doherty amplifier 1 of the present invention.
The output patterns, 10D to 12D, for the respective amplifies, 100 to 102, accompany with drain pads, VD0 to VD2, to which drain biases provided to the amplifiers, 100 to 102, are supplied. The drain pads, VD0 to VD2, also accompany many bypassing capacitors connected to the ground.
As described, the transmission line TL1 has the quarter wavelength (λ/4) for the RF signal subject to the Doherty amplifier 1, which means that the carrier amplifier 100 has a substantial load greater than characteristic impedance when the peak amplifiers, 101 and 102, are turned off. On the other hand, the peak amplifiers, 101 and 102, in the outputs thereof are provided to the combining node N0 through the high-impedance lines, ZP1 and ZP2. As the amplifiers, 100 to 102, installs larger transistors, for instance, a field effect transistor (FET) with a greater gate width inherently has substantial or large parasitic capacitance between a drain and a source such that the FET leaks the signal from the drain to the source even when the gate bias is supplied so as to turn off the transistor. Thus, the peak amplifiers, 101 and 102, are not practically turned off viewing from the combining node N0.
The Doherty amplifier 1 of the present embodiment provides the high-impedance lines, ZP1 and ZP2, between the peak amplifiers, 101 and 102, and the combining node N0; that is, the outputs of the peak amplifiers, 101 and 102, are provided to the combining node N0 through the high-impedance lines, ZP1 and ZP2, and the impedance viewing the peak amplifiers, 101 and 102, from the combining node N0 may be enhanced when the peak amplifiers, 101 and 102, are turned off. The outputs coming from the amplifiers, 100 to 102, to the combining node N0 is output through the transmission line TL2 with the quarter-wavelength (λ/4).
The carrier amplifier 100 implements two semiconductor chips, 10A and 10B, therein. Specifically, the carrier amplifier 100 includes a metal base 10b and a ceramic wall 10w, where the base 10b directly mounts the semiconductor chips 10A and 10B thereon within a space formed by the base 10b and the wall 10w. This space is air-tightly sealed by a lid that is not illustrated in
The base 10b provides a pair of cuts in longitudinal ends thereof, where the cuts receive screws for fixing the amplifier on the mounting substrate 2. The ceramic wall 10w provides metalized areas 10s in a top thereof for respective terminals 10t, to which the terminals 10t are brazed there. The lid is brazed onto a hatched area on the top of the ceramic wall 10w, namely, the top except for the metalized areas 10s to air-tightly seal the semiconductor chips, 10A and 10B, within the space.
The semiconductor chips, 10A and 10B, and input matching circuits, 10m and 10n, are fixed onto the base 10b with, for instance, eutectic alloy of gold tin (AuSn), or conductive resin containing silver (Ag) filler. The semiconductor chips, 10A and 10B, each provide a plurality of fingers for electrodes of the gate, the source, and the drain. The semiconductor chips, 10A and 10B, of the present embodiment each have a total gate width of 3 mm; that is, the amplifiers, 100 to 102, have a size of 6 mm in the gate width thereof, respectively. The gate pads on the semiconductor chips, 10A and 10B, receive not only an RF signal from the terminals 10t through the input matching circuits, 10m and 10n, but the gate biases. Specifically, the input matching circuits, 10m and 10n, which has an arrangement of a die-capacitor with a top electrode and a bottom electrode. The top electrode is connected with the terminals 10t and the gate pads on the semiconductor chips, 10A and 10B, each through bonding wires; while, the bottom electrode thereof faces to and is directly bonded with the base 10b. Thus, the input matching circuits, 10m and 10n, combined with the bonding wires may constitute T-shaped LCL circuit, where L correspond to inductance attributed to the bonding wires.
On the other hand for an output of the amplifier 100, the drain pads of the semiconductor chips, 10A and 10B, are connected with the terminals 10t without interposing any matching circuits. This is because a transistor having a large size, or large gate width, is hard, or almost impossible, to design an adequate matching circuit because such a transistor with a large size is unable to show large impedance even when the transistor is given a bias to be turned off due to enhanced parasitic components thereof. Accordingly, the Doherty amplifier of the present embodiment provides the high-impedance lines, ZP1 and ZP2, between the outputs of the peak amplifiers, 101 and 102, and the combining node N0 to enhance impedance viewing the peak amplifiers, 101 and 102, from the combining node N0 when the output power is smaller than the back-off level. The high-impedance lines, ZP1 and ZP2, may realize an adequate back-off performance even when the amplifiers, 100 to 102, have an exceptionally large size such that the amplifiers, 100 to 102, show a substantial leak, or insufficient impedance when the output power of the Doherty amplifier 1 is smaller than the back-off level.
While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
The present application claims the priority under 35 U.S.C. § 119 of U.S. Provisional Application Ser. No. 62/465,529, filed on Mar. 1, 2017, the contents of which is relied upon and incorporated herein by reference in its/their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62465529 | Mar 2017 | US |
