This disclosure relates generally to a millimeter wave (mmWave) antenna and, more particularly, to a mmWave phased array antenna including interconnected back-drilled vias.
Cellular telecommunications companies began deploying fifth generation (5G) radio technology standard for cellular networks in 2019. The 5G radio standard utilizes a higher frequency spectrum than previous generations of commercial communications technologies. MmW phased array antennas are being designed and developed for the 5G protocol that provides increased performance over 4G systems while also reducing costs. 5G mmWave antennas typically require precise manufacturing of printed circuit boards (PCBs) because antenna features on the order of a wavelength are at the limits of manufacturing tolerance of the PCB fabrication process.
One of the most challenging RF circuits for the development of a PCB based phased array antenna design is the transition structures, i.e., vias, between layers in the PCB. For example, the transition from the feed layer to the radiating elements, where these vias tend to be the largest vias on the PCB structure, is difficult to produce. Generally, these antenna designs include a high layer count PCB that tends toward using microvias as interconnect structures between the layers. This makes for a complex PCB fabrication process that is not suited to low cost high volume manufacturing. Furthermore, there have been PCB fabrication development methods to support fine pitch ball grid array (BGA) packages in application specific integrated circuit (ASIC) designs, where a conventional PCB is used, with plated through hole (PTH) vias, and then a number of subsequent prepreg layers using microvias are added to the PCB structure as a technique to provide trace routing to “break out” of the fine pitch BGA, which otherwise using PTH via technology would prove challenging, or even impossible as pin counts on the BGA ASIC increase.
The following discussion discloses and describes a mmWave phased array antenna that has particular application to be used in a 5G radio. The antenna includes a PCB structure having a plurality of layers. The PCB structure includes a first via hole formed into the layers through one side of the PCB structure and partially filled with a first via and a second via hole formed into the layers through an opposite side of the PCB structure and partially filled with a second via, where the first and second vias are electrically coupled by an interconnect. Prepreg buildup layers are formed on the one side of the PCB structure and prepreg buildup layers are formed on the opposite side of the PCB structure. At least one beamforming integrated circuit (IC) is formed on the prepreg buildup layers on the one side of the PCB structure and at least one antenna radiating element is formed on the prepreg buildup layers on the opposite side of the PCB structure.
Additional features of the disclosure will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.
The following discussion of the embodiments of the disclosure directed to a mmWave phased array antenna including interconnected back-drilled vias is merely exemplary in nature, and is in no way intended to limit the disclosure or its applications or uses. For example, the discussion herein refers to the antenna as being part of a phased array antenna for a 5G radio. However, as will be appreciated by those skilled in the art, the antenna will have other applications.
Prior to the layers 26 and 36 being formed on the PCB structure 12, a via structure 50 is formed in the PCB structure 12 to provide an electrical connection between the vias 28 and 38, and thus between the beamforming IC 32 and the radiating element 40. A hole 52 is drilled from the top side of the PCB structure 12 and a via 54 is formed in part of the hole 52 and the rest of the hole 52 is filled with a dielectric 56. A hole 60 is drilled from the bottom side of the PCB structure 12 and a via 62 is formed in part of the hole 60 and the rest of the hole 60 is filled with a dielectric 64, where the holes 52 and 60 are provided as close together as the manufacturing tolerances will allow. An interconnect 66 in the feed layer 22 electrically couples the vias 54 and 62. A stub 68 of the via 54 extends past the interconnect 66 adjacent to the dielectric 56 and a stub 70 of the via 62 extends past the interconnect 66 adjacent to the dielectric 64 and have a length for impedance matching purposes between the vias 54 and 62.
The foregoing discussion discloses and describes merely exemplary embodiments of the present disclosure. One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims that various changes, modifications and variations can be made therein without departing from the spirit and scope of the disclosure as defined in the following claims.
Filing Document | Filing Date | Country | Kind |
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PCT/US2022/076544 | 9/16/2022 | WO |
Number | Date | Country | |
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63261477 | Sep 2021 | US |