Double bootstrapped clock buffer circuit

Abstract

A buffer circuit has first and second boot-strap circuits. The first boot-strap circuit charges the gate of an output MOS transistor to a voltage above a supply voltage when an input signal has a first logic level. The gate of a precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit so as to precharge a capacitor in the first boot-strap circuit to a voltage above the supply voltage when the input signal has a second logic level.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a buffer circuit for amplifying input signals such as clock signals.

2. Description of the Prior Art

A known buffer circuit used in integrated semiconductor circuits, e.g., in a clock generator in memory devices, charges the gate of an output metal oxide semiconductor (MOS) transistor to a voltage above a supply voltage V.sub.CC so that an output signal OUT thereof rises rapidly to a voltage equal to V.sub.CC.

A boot-strap circuit is in general provided in such a buffer circuit to charge the gate of the output MOS transistor to the high voltage. The boot-strap circuit in the buffer circuit according to prior art, however, does not have sufficient charging capacity.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved buffer circuit with an increased reset efficiency and a faster rising output signal.

The above object is achieved by a buffer circuit which includes: first and second output MOS transistors connected in series between a supply voltage and ground; an output terminal connected between the first and second output MOS transistors and a first boot-strap circuit connected to the gate of the first output MOS transistor. The first boot-strap circuit charges the gate of the first output MOS transistor to a voltage above the supply voltage when an input signal has a first logic level, thus turning on the first output MOS transistor and charging the output terminal to the supply voltage. The first boot-strap circuit includes a capacitor and a MOS transistor which precharges the capacitor. Also included in the buffer circuit is a second boot-strap circuit having an output node connected to the gate of the precharging MOS transistor in the first boot-strap circuit, for driving the gate of the precharging MOS transistor to a precharged voltage above the supply voltage when the input signal is a second logic level.

According to the present invention as described above, since the gate of the precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit to precharge the capacitor in the first boot-strap circuit to a voltage above the supply voltage during a certain time, the reset efficiency of the buffer circuit can be increased and the rising speed of the output signal can be increased. Furthermore, according to the present invention, these effects can be obtained by just adding a simple circuit to the prior buffer circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other related objects and features of the present invention will be apparent from the description of the present invention set forth below, with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of an embodiment of the present invention;

FIG. 2 is a waveform diagram for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a circuit diagram of another embodiment of the present invention; and

FIG. 4 is a waveform diagram for explaining the operation of the embodiment of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 which illustrates an embodiment of the present invention, reference symbol BST.sub.1 indicates a first boot-strap circuit and BST.sub.2 indicates a second boot-strap circuit which is added according to the present invention.

First, the operation of a conventional buffer circuit without the second boot-strap circuit BST.sub.2 and, thus, with the gate of transistor Q.sub.1 directly connected to the supply voltage V.sub.CC will be discribed. In FIG. 1, Q.sub.10 to Q.sub.12 indicate depletion-mode MOS transistors and Q.sub.1 to Q.sub.4 and Q.sub.13 to Q.sub.19 indicate enhancement-mode MOS transistors. The MOS transistor Q.sub.1 and a capacitor C.sub.2 comprise the first boot-strap circuit BST.sub.1.

When an input signal IN applied to the gate of the MOS transistor Q.sub.13 rises from a low logic level to a high logic level, the MOS transistor Q.sub.13 turns on and, thus, node N.sub.1 is discharged to a low logic level as shown in FIG. 2. As a result, the MOS transistor Q.sub.14 turns off and node N.sub.2 is pulled up to V.sub.CC by the MOS transistor Q.sub.11, causing the MOS transistors Q.sub.15 to Q.sub.17 to turn on. As the MOS transistor Q.sub.16 turns on, node N.sub.6 is discharged to a low logic level or ground V.sub.SS. Also, as the MOS transistor Q.sub.17 turns on, the output terminal OUT is discharged to ground V.sub.SS. Furthermore, since the MOS transistor Q.sub.15 turns on, current flows from V.sub.CC to V.sub.SS via Q.sub.1 --N.sub.4 --Q.sub.12 --N.sub.5 --Q.sub.15 --N.sub.1 --Q.sub.13, which causes node N.sub.5 to be discharged to a low logic level and the MOS transistors Q.sub.18 and Q.sub.19 to turn off.

Node N.sub.4 is boot-strapped by the capacitor C.sub.2 to a voltage above V.sub.CC when the MOS transistor Q.sub.16 is off, namely when the input signal IN has a low logic level. When the MOS transistor Q.sub.16 turns on, node N.sub.4 is lowered to a voltage equal to the supply voltage V.sub.CC minus one threshold voltage V.sub.th of the MOS transistor Q.sub.1. The capacitor C.sub.2 is precharged during the turning on of Q.sub.16. A broken line N.sub.4 ' in FIG. 2 shows the voltage at node N.sub.4 according to the above-described conventional circuit. Since node N.sub.4 is below V.sub.CC by the amount of the threshold voltage Vth when the input signal IN has the high logic level, node N.sub.5 is not charged to a sufficiently high voltage by the capacitor C.sub.2 via the boot-strapping node N.sub.4 when the input signal IN falls to a low logic level. At this time (low IN signal) node N.sub.1 is charged to a high logic level, node N.sub.2 is discharged to a low logic level, the transistor Q.sub.14 turns on, and the transistors Q.sub.15 to Q.sub.17 turn off, causing the voltage at node N.sub.6 to increase. A broken line N.sub.5 ' shown in FIG. 2 shows the voltage at node N.sub.5. The voltage N.sub.5 ' at node N.sub.5 causes the MOS transistor 19 to turn on. If the voltage N.sub.5 ' at node N.sub.5 is not sufficiently high, although the voltage N.sub.5 ' is higher than V.sub.CC, the output signal OUT will not increase to V.sub.CC or it will take a lot of time to increase the output signal to V.sub.CC.

Hereinafter, the operation of the buffer circuit according to the embodiment illustrated in FIG. 1 will be described. The present invention is intended to sufficiently increase the voltage at node N.sub.4 during the period when the input signal IN has a high logic level, hereinafter called the "reset period". In order to perform this operation, this embodiment of the present invention provides the second boot-strap circuit BST.sub.2, whose output node N.sub.3 is connected to the gate of the MOS transistor Q.sub.1. A boot-strapping capacitor C.sub.1 in the second boot-strap circuit BST.sub.2 is connected between node N.sub.2 and the output node N.sub.3. It should be noted that node N.sub.2 is maintained at a high logic level during the reset period. Thus, during the reset period, the gate of the MOS transistor Q.sub.1 (node N.sub.3) is charged to a voltage above V.sub.CC via the capacitor C.sub.1, causing node N.sub.4 to be charged to a voltage below but near V.sub.CC via the transistor Q.sub.1 during the reset period, as shown by a solid line N.sub.4 in FIG. 2.

When the input signal IN falls to a low logic level from a high logic level, the voltage at node N.sub.2 changes from a high logic level to a low logic level and thus node N.sub.3 is discharged to a voltage below V.sub.CC, causing the transistor Q.sub.1 to turn off. At the same time, the MOS transistor Q.sub.16 turns off, causing the voltage at node N.sub.6 to increase. As a result, node N.sub.4 is boot-strapped via the capacitor C.sub.2 to a voltage above V.sub.CC, and thus node N.sub.5 is charged to a voltage above V.sub.CC, as shown by the solid line N.sub.5 in FIG. 2. This charged voltage at node N.sub.5 is sufficiently high to drive the MOS transistors Q.sub.18 and Q.sub.19 and to rapidly raise the output signal OUT to V.sub.CC. The MOS transistor Q.sub.1 is in the on-state to cause the charging of capacitor C.sub.2 via V.sub.CC --Q.sub.1 --N.sub.4 --C.sub.2 --Q.sub.16 --V.sub.SS when the voltage at node N.sub.3 is above V.sub.CC. When the transistor Q.sub.14 turns on the voltage at N.sub.2 drops and the transistor Q.sub.16 turns off, thus as N.sub.3 becomes .ltoreq.V.sub.CC and N.sub.4 becomes <V.sub.CC, the MOS transistor Q.sub.1 turns off, whereby node N.sub.4 is prevented from being discharged to V.sub.CC.

Besides the boot-strapping capacitor C.sub.1 and the enhancement-mode MOS transistor Q.sub.2 connected as a diode for precharging the capacitor C.sub.1, the second boot-strap circuit BST.sub.2 preferably includes the enhancement-mode MOS transistor Q.sub.3 connected as a diode between node N.sub.3 and V.sub.CC. The transistor Q.sub.3, whose drain and gate are connected to node N.sub.3 and whose source is connected to V.sub.CC, prevents node N.sub.3 from being over-charged. In other words transistor Q.sub.3 clamps node N.sub.3 to a voltage which is higher than V.sub.CC by a predetermined voltage. As a result, if V.sub.CC decreases when the output signal OUT rises, since the maximum voltage at node N.sub.3 decreases depending upon V.sub.CC, the transistor Q.sub.1 will not turn on, causing node N.sub.4 not to discharge to V.sub.CC.

In addition, the second boot-strap circuit BST.sub.2 preferably includes the MOS transistor Q.sub.4, which is connected between node N.sub.3 and V.sub.CC and controlled by the voltage at node N.sub.4. This transistor Q.sub.4 prevents node N.sub.4 from being over-charged and also ensures cutting off operation of the transistor Q.sub.1. The transistor Q.sub.1 should be cut off during a period when the voltage at node N.sub.4 is above V.sub.CC. Therefore, if the transistor Q.sub.4 is conductive during this period, the voltage at node N.sub.3 is clamped to V.sub.CC. As a result, the transistor Q.sub.1 will remain turned off even if V.sub.CC drops.

FIG. 3 illustrates another embodiment of the present invention. In this embodiment, the drain of the MOS transistor Q.sub.14 is connected to node N.sub.4 and furthermore to the gates of the transistors Q.sub.18 and Q.sub.19. The boot-strapping capacitor C.sub.1 in the second boot-strap circuit BST.sub.2 is connected between node N.sub.4 and node N.sub.3. The drain (node N.sub.5) of the MOS transistor Q.sub.25 is connected to the gates of the MOS transistors Q.sub.16 and Q.sub.17. Node N.sub.5 is also connected via the MOS transistor Q.sub.12 to node N.sub.3. The remainder of this embodiment is essentially the same as that of the embodiment of FIG. 1.

Hereinafter the operation of the buffer circuit according to the embodiment of FIG. 3 will be described. When the input signal IN rises to a high logic level from a low logic level, the MOS transistor Q.sub.13 turns on and thus node N.sub.1 is gradually discharged to V.sub.SS as shown in FIG. 4. As a result, the MOS transistor Q.sub.14 turns off and thus node N.sub.4 is charged via Q.sub.14 causing the voltage at node N.sub.3 to be boot-strapped by the capacitor C.sub.1 to a voltage well above the supply voltage V.sub.CC as shown in FIG. 4. Therefore, the MOS transistor Q.sub.1 is maintained in the on-state and node N.sub.4 is charged nearly to V.sub.CC. When node N.sub.4 is charged to a voltage equal to the voltage at node N.sub.1 plus one threshold voltage V.sub.th, the MOS transistor Q.sub.25 turns on causing node N.sub.5 to be discharged as shown in FIG. 4. Thus the enhancement-type MOS transistor Q.sub.22 also turns on causing node N.sub.3 to rapidly discharge. Accordingly, the MOS transistors Q.sub.1, Q.sub.16 and Q.sub.17 turn off. Since, in this case, the MOS transistor Q.sub.18 is in the on-state, node N.sub.6 is boot-strapped to a voltage near to V.sub.CC. As a pulse-shaped voltage produced by boot-strapping is applied to node N.sub.4 via the capacitor C.sub.2, node N.sub.4 is boot-strapped to a voltage well above V.sub.CC. This charged voltage at node N.sub.4 is sufficiently high to drive the MOS transistors Q.sub.18 and Q.sub.19 and to rapidly raise the output signal OUT to V.sub.CC. Since the MOS transistor Q.sub.1 is in off-state in this case, node N.sub.4 can be prevented from being discharged to V.sub.CC.

Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims

1. A buffer circuit, operatively connected to a supply voltage and to receive an input signal, producing an output signal in response to the input signal, comprising:

first and second output transistors having their drain-source current paths operatively connected in series between the supply voltage and ground, thereby forming a junction between said first and second output transistors, each of said first and second output transistors having a gate;

an output terminal operatively connected to the junction between said first and second output transistors;

a first boot-strap circuit operatively connected to the gate of said first output transistor for charging the gate of said first output transistor to a charged voltage above the supply voltage when the input signal has a first logic level, turning on said first output transistor and charging said output terminal to the supply voltage, said first boot-strap circuit comprising:

a capacitor operatively connected to the gate of said first output transistor; and

a precharging transistor, having its drain-source current path coupled between the supply voltage and saidcapacitor, for precharging said capacitor and having a gate; and

a second boot-strap circuit having an output node operatively connected to the gate of said precharging transistor in said first boot-strap circuit, for driving the gate of said precharging transistor to a precharged voltage above the supply voltage when the input signal has a second logic level.

2. A buffer circuit as claimed in claim 1, wherein said second boot-strap circuit comprises a capacitor, operatively connected to the output node, which is precharged when the input signal has the first logic level.

3. A buffer circuit as claimed in claim 1, wherein said second boot-strap circuit further comprises diode means, operatively connected to the supply voltage and the output node, for clamping the output node to a precharge voltage which is higher than the supply voltage by a predetermined voltage.

4. A buffer circuit as claimed in claim 3, wherein said diode means comprises a clamping transistor having a gate and a drain operatively connected to the output node and a source operatively connected to the supply voltage.

5. A buffer circuit as claimed in claim 1,

wherein said first boot-strap circuit further comprises a junction node between said precharging transistor and said capacitor, and

wherein said second boot-strap circuit comprises clamping means operatively connected to the supply voltage and the junction node, for maintaining the output node at the supply voltage when the junction node between said precharging transistor and said capacitor in said first boot-strap circuit is above the supply voltage.

6. A buffer circuit as claimed in claim 5, wherein said clamping means comprises a clamping transistor having a source operatively connected to the output node, a drain operatively connected to the supply voltage and a gate operatively connected to the junction node.