Double Data Rate Chaining for Synchronous DDR Interfaces

Abstract

A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a logic block diagram of a double data rate driver with a 2-to-1 multiplexer so that the odd data can bypass the first stage of the latch in the odd path.

FIG. 2 is a logic block diagram of one embodiment of the system and method in accordance with the teachings of this invention

FIG. 3 is a timing diagram for the logic of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1 of the drawings, it shows a chip 200 with a double data rate driver that can be used in the practice of this invention. Like prior art double data rate drivers, it includes a master/slave latch 210 to latch the even data input (data_even) and a master/slave latch 104 to latch the odd data (data_odd). A 2-to-1 multiplexer 114 can be used to bypass the odd data latch 104. Alternatively, the latch 104 and the 2-to-1 multiplexer 114 could be physically removed from the circuit. A master latch 232 in the odd data path couples the odd data input 110 to multiplexer 206 that drives the double data rate bus, while master/slave latch 210 provides the even data input 112. The data on the DDR bus is thus split into 2 parts, the first (even) and second (odd) half. Each half is launched as soon as it is available, one on the normal chip cycle time (Master-Slave latch or Flip-Flop clocking), the other is launched to the chip (internal logic) from a Master latch a half cycle into the normal chip cycle time. The first data proceeds through the chip as a normal chip path to be captured by the driving interface's latch and launched again after only one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half. The DDR receiver delay is reduced by using the Master latch output port of the Odd data path instead of its Slave latch output port.

Referring now to FIGS. 2 and 3, a chip 200, which has a local clock C1/C2, separately latches each corresponding half (even half and odd half) of the data received from the double data rate bus 201. The even half (0, 2, 4 . . . ) is latched into the master side of master/slave latch 202 and is immediately available at 204 from the slave side of the latch to the chip's standard design path 206 as soon as it is available at the input to the latch 202, since the local clock C1 input to the master and local clock C2 input to the slave are 180 degrees out of phase. It will be appreciated that the chip's standard design path 206 is comprised of logic elements, and in this example it is assumed that its functions take less than one local clock cycle, although in some cases may take more, up to N local clock cycle. This data, having been processed through the standard design path 206, is latched into the master side of master/slave latch 210 at the beginning of the next clock cycle and is immediately available at the input 205 to the multiplexer 206, where it can be output on the double data rate bus 216 after an N on chip latency, in this example, of one local clock cycle.

One half of the local clock cycle after the even half of the data on the double data rate bus is latched, the corresponding odd half (1, 3, 5 . . . ) of the data is latched by the slave side of master/slave latch 220 and the master side master/slave latch 222 so that it is immediately available as an input 209 to the chip's standard design path 206. After having been processed by the logic in path 206, the data is latched in the slave side of master/slave latch 230 and the master side of master/slave latch 232 where it is immediately available as an input 215 to the multiplexer 206. Since the odd data is available at the multiplexer one half cycle after the even data, it can be outputted by the SELECT input to multiplexer 206 to the double data rate bus on the clock edge following the clock edge that outputted the even data, resulting in only an N plus one local clock cycle latency on the chip, where in this case N is zero since neither the even nor the odd data teaches a full latch during the on chip portion. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. The invention takes advantage of the early availability and late launch capability provided by the DDR interface to move data through the daisy-chained chip in a way to remove the added latency of serialization and provides flexibility on latch physical placement in the chip internal data path. Additional advantages are provided through the provision of a Master latch output port for the DDR receiver Odd data path, and using “alternating” Master-Slave latches in the Odd data path.

The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.

As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.

Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.

The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims

1. A method for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus, including the steps of: latching a first half of the synchronous data in a first input latch on a leading edge of a local clock signal, processing said first half of the synchronous data, and latching the processed first half of the synchronous data in a first output latch on a leading edge of said local clock;launching the processed first half of the synchronous data on said double data rate bus as soon as it is latched in said first output latch;latching a second half of the synchronous data in a second input latch one half local clock signal after said first half of the synchronous data is latched in said first input latch, processing said second half of the synchronous data, and latching the processed second half of the synchronous data in a second output latch one half of a local clock cycle after said first half of the synchronous data is latched in said first output latch; andlunching said second half of the synchronous data on said double data rate bus as soon as it is latched in said second output latch.

2. A method for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 1 wherein the on chip latency is one local clock cycle.

3. A method for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 1 wherein said first input latch is a master/slave latch and said first output latch is a master/slave latch.

4. A method for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 3 where in said second input latch is a slave/master latch and said second output latch is a slave/master latch.

5. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus, comprising in combination: means for latching a first half of the synchronous data in a first input latch on a leading edge of a local clock signal, means for processing said first half of the synchronous data, and means for latching the processed first half of the synchronous data in a first output latch on a leading edge of said local clock;means for launching the processed first half of the synchronous data on said double data rate bus as soon as it is latched in said first output latch;means for latching a second half of the synchronous data in a second input latch one half local clock signal after said first half of the synchronous data is latched in said first input latch, means for processing said second half of the synchronous data, and means latching the processed second half of the synchronous data in a second output latch one half of a local clock cycle after said first half of the synchronous data is latched in said first output latch; andmeans for launching the second half of the synchronous data on said double data rate bus as soon as it is latched in said second output latch.

6. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 5 wherein the on chip latency is one local clock cycle.

7. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 5 wherein said first input latch is a master/slave latch and said first output latch is a master/slave latch.

8. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 5 wherein said second input latch is a slave/master latch and said second output latch is a slave/master latch.

9. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 7 wherein said second input latch is a slave/master latch and said second output latch is a slave/master latch.

10. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus, comprising in combination: a first input latch latching a first half of said synchronous on a leading edge of a local clock signal, processing logic processing said first half of the synchronous data, and a first output latch latching the processed first half of the synchronous data in a first output latch on a leading edge of said local clock;said first output latch launching the processed first half of the synchronous data on said double data rate bus as soon as it is latched in said first output latch;a second input latch latching a second half of the synchronous data one half local clock signal after said first half of the synchronous data is latched in said first input latch, processing logic processing said second half of the synchronous data, and a second output latch latching the processed second half of the synchronous data one half of a local clock cycle after said first half of the synchronous data is latched in said first output latch; andsaid second output latch launching the second half of the synchronous data on said double data rate bus as soon as it is latched in said second output latch.

11. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 10 wherein the on chip latency is one local clock cycle.

12. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 10 wherein said first input latch is a master/slave latch and said first output latch is a master/slave latch.

13. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 10 wherein said second input latch is a slave/master latch and said second output latch is a slave/master latch.

14. A system for clocking synchronous data on a chip between an input port coupled to a double data rate bus and an output port coupled to a double data rate bus as in claim 12 wherein said second input latch is a slave/master latch and said second output latch is a slave/master latch.