Patent Application
20150287709
1. Field
The present disclosure relates generally to a layout construction, and more particularly, to a double patterned stacking technique.
2. Background
A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. Reducing a size/area footprint of ASICs is beneficial. Accordingly, there is a need for reducing the size/area footprint of individual standard cells.
In an aspect of the disclosure, a complementary metal oxide semiconductor (CMOS) device includes a first set of stacked transistors including a first transistor and a second transistor. The first transistor has a first transistor active region and the second transistor has a second transistor active region. The CMOS device further includes a second set of stacked transistors adjacent the first set of stacked transistors. The second set of stacked transistors includes a third transistor and a fourth transistor. The third transistor has a third transistor active region and the fourth transistor has a fourth transistor active region. The CMOS device further includes a set of transistors adjacent the first set of stacked transistors. The set of transistors includes a fifth transistor. The fifth transistor has a fifth transistor active region. The first transistor active region is greater than or equal to a distance d from the second transistor active region. The third transistor active region is greater than or equal to the distance d from the fourth transistor active region. The distance d is a minimum distance based on a patterning process for the device. The first transistor active region is approximately greater than a distance 0.5d from the third transistor active region. The second transistor active region is approximately greater than the distance 0.5d from the fourth transistor active region. The fifth transistor active region is approximately greater than the distance 0.5d from the first transistor active region and the second transistor active region.
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Apparatuses and methods will be described in the following detailed description and may be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc.
In the schematic of the circuit 100, the first set of stacked transistors 130 and the second set of stacked transistors 140 are isolated from each other. However, in a layout of the circuit 100, the first set of stacked transistors 130 and the second set of stacked transistors 140 may be placed next to each other to satisfy a design rule check (DRC). A DRC may require that when a source/drain contact interconnect has a particular width (e.g., 26 nm) and a length less than a particular length (e.g., 150 nm), at least N (e.g., 5) source/drain interconnects be aligned to overlap by a particular percentage (e.g., 80%). The transistors 102-116 in the first and second sets of stacked transistors 130, 140 may be part of a scan chain and have smaller widths for a better scan hold margin. With the smaller widths, sets of the transistors 102-116 may be stacked within a height limited standard cell. For example, the first set of stacked transistors 130 may be stacked in a first stack and the second set of stacked transistors 140 may be stacked in a second stack within a standard cell.
Within the transistor 102, a source interconnect 260 contacts a source of the transistor 102 and a drain interconnect 262 contacts a drain of the transistor 102. Within the transistor 104, a source interconnect 264 contacts a source of the transistor 104 and a drain interconnect 266 contacts a drain of the transistor 104. Within the transistor 106, a source interconnect 268 contacts a source of the transistor 106 and a drain interconnect 270 contacts a drain of the transistor 106. Within the transistor 108, a source interconnect 272 contacts a source of the transistor 108 and a drain interconnect 274 contacts a drain of the transistor 108. Within the transistor 112, a source interconnect 280 contacts a source of the transistor 112 and a drain interconnect 282 contacts a drain of the transistor 112. Within the transistor 110, a source interconnect 284 contacts a source of the transistor 110 and a drain interconnect 286 contacts a drain of the transistor 110. Within the transistor 116, a source interconnect 288 contacts a source of the transistor 116 and a drain interconnect 290 contacts a drain of the transistor 116. Within the transistor 114, a source interconnect 292 contacts a source of the transistor 114 and a drain interconnect 294 contacts a drain of the transistor 114. Within the transistor 206, which may be a pMOS transistor, a source interconnect 242 contacts a source of the transistor 206 and a drain interconnect 244 contacts a drain of the transistor 206. Within the transistor 208, which may be an nMOS transistor, a source interconnect 246 contacts a source of the transistor 208 and a drain interconnect 248 contacts a drain of the transistor 208.
In one configuration, the source interconnect 260, the drain interconnect 262, the source interconnect 268, the drain interconnect 270, the source interconnect 242, and the drain interconnect 244 are aligned to overlap in a first direction. In one configuration, the source interconnect 264, the drain interconnect 266, the source interconnect 272, the drain interconnect 274, the source interconnect 242, and the drain interconnect 244 are aligned to overlap in the first direction. In one configuration, the source interconnect 280, the drain interconnect 282, the source interconnect 288, the drain interconnect 290, the source interconnect 246, and the drain interconnect 248 are aligned to overlap in the first direction (shown in
In one configuration, the distances d3, d4, and d5 are approximately less than the distance 0.6d. Accordingly, the distances d3, d4, and d5 may be greater than the distance 0.5d and less than the distance 0.6d. For example, if the distance d=94 nm, then the distances d3, d4, and d5 may be greater than 47 nm and less than 56.4 nm. In one configuration, the distances d3, d4, and d5 are greater than or equal to 50 nm. In one example, the d3, d4, and d5 are approximately equal to 50 nm. In one configuration, the distances d1 and d2 are less than or equal to the distance 1.2d. Accordingly, the distances d1 and d2 may be greater than or equal to the distance d and less than or equal to the distance 1.2d. In one configuration, the distances d1 and d2 are equal to the distance d. For example, if the distance d=94 nm, then the distances d1 and d2 are greater than or equal to 94 nm and less than or equal to 112.8 nm. In one example, the distances d1 and d2 are approximately equal to 94 nm.
As discussed supra, the fifth transistor active region 356, the third transistor active region 306, and the fourth transistor active region 308 are patterned together in one patterning process, and the first transistor active region 302 and the second transistor active region 304 are patterned together in another patterning process. The active regions 356, 306, 308 may be patterned before or after the active regions 302, 304.
The first transistor active region 302 includes a first transistor source and a first transistor drain. A first transistor source interconnect 260 contacts the first transistor source and a first transistor drain interconnect 262 contacts the first transistor drain. The third transistor active region 306 includes a third transistor source and a third transistor drain. A third transistor source interconnect 268 contacts the third transistor source and a third transistor drain interconnect 270 contacts the third transistor drain. The fifth transistor active region 356 includes a fifth transistor source and a fifth transistor drain. A fifth transistor source interconnect 242 contacts the fifth transistor source and a fifth transistor drain interconnect 244 contacts the fifth transistor drain. The first transistor source interconnect 260, the first transistor drain interconnect 262, the third transistor source interconnect 268, the third transistor drain interconnect 270, and at least one of the fifth transistor source interconnect 242 or the fifth transistor drain interconnect 244 (e.g., both the fifth transistor source interconnect 242 and the fifth transistor drain interconnect 244) are aligned to overlap in a first direction. In one configuration, the first transistor source interconnect 260, the first transistor drain interconnect 262, the third transistor source interconnect 268, the third transistor drain interconnect 270, and the at least one of the fifth transistor source interconnect 242 or the fifth transistor drain interconnect 244 (e.g., both the fifth transistor source interconnect 242 and the fifth transistor drain interconnect 244) are aligned to overlap in the first direction by at least 80% to satisfy the aforementioned DRC. Referring to
The second transistor active region 304 includes a second transistor source and a second transistor drain. A second transistor source interconnect 264 contacts the second transistor source and a second transistor drain interconnect 266 contacts the second transistor drain. The fourth transistor active region 308 includes a fourth transistor source and a fourth transistor drain. A fourth transistor source interconnect 272 contacts the fourth transistor source and a fourth transistor drain interconnect 274 contacts the fourth transistor drain. In one configuration, the second transistor source interconnect 264, the second transistor drain interconnect 266, the fourth transistor source interconnect 272, the fourth transistor drain interconnect 274, and the at least one of the fifth transistor source interconnect 242 or the fifth transistor drain interconnect 244 (e.g., both the fifth transistor source interconnect 242 and the fifth transistor drain interconnect 244) are aligned to overlap in the first direction. In one configuration, the second transistor source interconnect 264, the second transistor drain interconnect 266, the fourth transistor source interconnect 272, the fourth transistor drain interconnect 274, and the at least one of the fifth transistor source interconnect 242 or the fifth transistor drain interconnect 244 (e.g., both the fifth transistor source interconnect 242 and the fifth transistor drain interconnect 244) are aligned to overlap in the first direction by at least 80% to satisfy the aforementioned DRC. Referring to
The first set of stacked transistors 130 may further include a sixth transistor 110 and a seventh transistor 112. The sixth transistor 110 has a sixth transistor active region 310 and the seventh transistor 112 has a seventh transistor active region 312. The second set of stacked transistors 140 may further include an eighth transistor 114 and a ninth transistor 116. The eighth transistor 114 has an eighth transistor active region 314 and the ninth transistor 116 has a ninth transistor active region 316. The set of transistors 210 may further include a tenth transistor 208. The tenth transistor has a tenth transistor active region 358. The sixth transistor active region 310 is a distance d6 from the seventh transistor active region 312. The distance d6 may be greater than or equal to the distance d. The eighth transistor active region 314 is a distance d7 from the ninth transistor active region 316. The distance d7 may be greater than or equal to the distance d. The sixth transistor active region 310 is a distance d8 from the eighth transistor active region 314. The distance d8 may be approximately greater than the distance 0.5d. The seventh transistor active region 312 is a distance d9 from the ninth transistor active region 316. The distance d9 may be approximately greater than the distance 0.5d. The tenth transistor active region 358 is a distance d10 from the sixth transistor active region 310 and the seventh transistor active region 312. The distance d10 may be approximately greater than the distance 0.5d.
The distances d6 and d7 may be less than the distance 1.2d. Accordingly, the distances d6 and d7 may be greater than the distance d and less than the distance 1.2d. The distances d8, d9, and d10 may be less than 0.6d. Accordingly, the distances d8, d9, and d10 may be greater than the distance 0.5d and less than the distance 0.6d. In one configuration, as shown in
The tenth transistor active region 358, the eighth transistor active region 314, and the ninth transistor active region 316 may be patterned together in one patterning process, and the sixth transistor active region 310 and the seventh transistor active region 312 may be patterned together in another patterning process. The tenth transistor active region 358, the eighth transistor active region 314, and the ninth transistor active region 316 may be patterned together along with the fifth transistor active region 356, the third transistor active region 306, and the fourth transistor active region 308 in one patterning process. The sixth transistor active region 310 and the seventh transistor active region 312 may be patterned together along with the first transistor active region 302 and the second transistor active region 304 in another patterning process. The active regions 356, 358, 306, 308, 314, and 316 may be patterned before or after the active regions 302, 304, 310, and 312.
The sixth transistor active region 310 includes a sixth transistor source and a sixth transistor drain. A sixth transistor source interconnect 384 contacts the sixth transistor source and a sixth transistor drain interconnect 388 contacts the sixth transistor drain. The eighth transistor active region 314 includes an eighth transistor source and an eighth transistor drain. An eighth transistor source interconnect 292 contacts the eighth transistor source and an eighth transistor drain interconnect 294 contacts the eighth transistor drain. The tenth transistor active region 358 includes a tenth transistor source and a tenth transistor drain. A tenth transistor source interconnect 246 contacts the tenth transistor source and a tenth transistor drain interconnect 248 contacts the tenth transistor drain. The sixth transistor source interconnect 284, the sixth transistor drain interconnect 286, the eighth transistor source interconnect 292, the eighth transistor drain interconnect 294, and at least one of the tenth transistor source interconnect 246 or the tenth transistor drain interconnect 248 (e.g., both the tenth transistor source interconnect 246 and the tenth transistor drain interconnect 248) are aligned to overlap in the first direction. In one configuration, the sixth transistor source interconnect 284, the sixth transistor drain interconnect 286, the eighth transistor source interconnect 292, the eighth transistor drain interconnect 294, and the at least one of the tenth transistor source interconnect 246 or the tenth transistor drain interconnect 248 (e.g., both the tenth transistor source interconnect 246 and the tenth transistor drain interconnect 248) are aligned to overlap in the first direction by at least 80% to satisfy the aforementioned DRC. Referring to
The seventh transistor active region 312 includes a seventh transistor source and a seventh transistor drain. A seventh transistor source interconnect 280 contacts the seventh transistor source and a seventh transistor drain interconnect 282 contacts the seventh transistor drain. The ninth transistor active region 316 includes a ninth transistor source and a ninth transistor drain. A ninth transistor source interconnect 288 contacts the ninth transistor source and a ninth transistor drain interconnect 290 contacts the ninth transistor drain. The seventh transistor source interconnect 280, the seventh transistor drain interconnect 282, the ninth transistor source interconnect 288, the ninth transistor drain interconnect 290, and the at least one of the tenth transistor source interconnect 246 or the tenth transistor drain interconnect 248 (e.g., both the tenth transistor source interconnect 246 and the tenth transistor drain interconnect 248) are aligned to overlap in the first direction. In one configuration, the seventh transistor source interconnect 280, the seventh transistor drain interconnect 282, the ninth transistor source interconnect 288, the ninth transistor drain interconnect 290, and the at least one of the tenth transistor source interconnect 246 or the tenth transistor drain interconnect 248 (e.g., both the tenth transistor source interconnect 246 and the tenth transistor drain interconnect 248) are aligned to overlap in the first direction by at least 80% to satisfy the aforementioned DRC. Referring to
The first set of stacked transistors 130 operate as an inverter. The first transistor 102 and the second transistor 104 are pMOS transistors, and the sixth transistor 110 and the seventh transistor 112 are nMOS transistors. The second set of stacked transistors 140 operate as an inverter. The third transistor 106 and the fourth transistor 108 are pMOS transistors, and the eighth transistor 114 and the ninth transistor 116 are nMOS transistors.
Referring to the distances d1 through d10, the distances d3, d4, d5, d8, d9, and d10 may be greater than or equal to the distance 0.5d and less than or equal to the distance 0.6d, where d is the minimum distance based on a patterning process for the device (discussed supra). In one configuration, d=94 nm and the distances d3, d4, d5, d8, d9, and d10 are greater than or equal to 47 nm and less than or equal to 56.4 nm. In one configuration, the distances d3, d4, d5, d8, d9, and d10 are greater than or equal to 50 nm and less than or equal to 56.4 nm. In another configuration, the distances d3, d4, d5, d8, d9, and d10 are equal to 50 nm. The distances d1, d2, d6, and d7 may be greater than or equal to the distance d and less than or equal to the distance 1.2d. In one configuration, d=94 nm and the distances d1, d2, d6, and d7 are greater than or equal to 94 nm and less than or equal to 112.8 nm. In another configuration, the distances d1, d2, d6, and d7 are equal to the distance d. If d=94 nm, then the distances d1, d2, d6, and d7 are equal to 94 nm.
As discussed supra, a DRC may require that when interconnects have a particular width (e.g., 26 nm) and a length less than a particular length (e.g., 150 nm), at least N (e.g., 5) of the interconnects be aligned to overlap by a particular percentage (e.g., 80%). The configurations as provided supra may satisfy the DRC. The interconnects 260, 262, 268, 270, 242, and 244 may be a first group of interconnects; the interconnects 264, 266, 272, 274, 242, and 244 may be a second group of interconnects; the interconnects 284, 286, 292, 294, 246, and 248 may be a third group of interconnects; and the interconnects 280, 282, 288, 290, 246, and 248 may be a fourth group of interconnects. Each of the first, second, third, and fourth groups of interconnects may overlap by 80%. As shown in
It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.” Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
