Patent Application
20120271871
This application claims the benefit of Russian Application No. 2011115796, filed Apr. 22, 2011 and is hereby incorporated by reference in its entirety.
The present invention relates to calculating mathematical operations generally and, more particularly, to a method and/or apparatus for implementing a double precision approximation of a single precision operation.
Processors commonly have a set of basic operations that can be performed in hardware without resorting to software implementations. Such basic operations can be performed in a minimum number of processor cycles and so are efficient from a computational point of view. The fewer the number of basic operations that a processor implements, the lower the cost of the processor. Therefore, processor manufacturers often try to minimize the number of basic operations.
A minimal set of basic operations is often insufficient for real applications. Programmers are commonly forced to implement non-basic operations and higher-resolution basic operations in software. For example, many applications involve a calculation of a 32-bit integer result for a 1/X operation, where X is a 32-bit integer argument. If the processor executing the application only supports a 16-bit hardware calculation of the 1/X operation, where X is a 16-bit integer argument, the application will rely on a software routine to calculate the 32-bit integer result.
Known techniques to calculate 32-bit integer operations in software commonly use floating-point number calculations. The 32-bit integer values are converted to floating-point numbers. The calculations are performed with floating-point operations. A floating-point value that results from the floating-point operations is subsequently converted back into a 32-bit integer value. Hence, applying such techniques to fixed-point operations causes some technical issues. Most of the floating-point techniques use a polynomial approximation for the calculation, which is slow compared with the basic operations. Moreover, the floating-point techniques are applicable only to a narrow class of functions.
The present invention generally concerns a method for double precision approximation of a single precision operation. The method may include steps (A) to (B). Step (A) may store an input value in a processor. The processor generally implements a plurality of first operations in hardware. Each first operation may receive a first variable as an argument. The first variable may be implemented in a fixed point format at a single precision. The input value may be implemented in the fixed point format at a double precision. Step (B) may generate an output value by emulating a selected one of the first operations using the input value as the argument. The emulation may utilize the selected first operation in hardware. The output value may be implemented in the fixed point format at the double precision. The emulation is generally performed by a plurality of instructions executed by the processor.
The objects, features and advantages of the present invention include providing a method and/or apparatus for implementing a double precision approximation of a single precision operation that may (i) provide a technique to build an efficient software implementation of an arbitrary mathematical operation with double precision, (ii) utilize a single precision hardware implementation of the mathematical operation in calculating the double precision result, (iii) emulate with software a 2N-bit function F(X′), where X′ is a 2N-bit fixed point number, using a hardware implementation of an N-bit function F(X), where X is an N-bit fixed point number, (iv) consume less power in calculating a double precision fixed point result of a mathematical operation compared with a floating point-based calculation of the double precision fixed point result, (v) calculate a double precision fixed point result faster than a floating point-based calculation of the double precision fixed point result, (vi) generate the double precision result with a non-iterative set of calculations and/or (vii) use the single precision fixed point hardware in the emulation.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
When designing high-performance applications for use on a target processor, designs of the application may involve one or more double precision operations. If the target processor only has single precision implementations of the operations, a designer may emulate the operations using instructions (e.g., software, firmware, microcode, etc.) executed by the target processor. For example, the target processor may implement an inverse operation (e.g., Y=1/X), where X is a 16-bit fixed point (or integer) number. However, an application may specify that X is a 32-bit fixed point (or integer) number. Therefore, the software is generally utilized to emulate (or approximate) a 32-bit version of the operation.
Some embodiments of the present invention generally concern improving an accuracy of the software emulations (computations) where hardware implementations of single precision analogous operations may be available in the processor. For a processor having an N-bit precision mathematical operation (or function) Y=F(X), a software implementation of a 2N-bit precision mathematical operation Y=F(X) may be built with a low computational complexity. A mathematical operation is generally a relation that associates members of a set with members of another set.
To help keep the computational complexity of the mathematical operation low, the processor should implement a set of elementary operations. An elementary operation may be an operation involving at least one of the operations of addition, subtraction, multiplication and division. The elementary operations of addition and subtraction may be implemented for double precision values. The elementary multiplication operation of two N-bit numbers (e.g., A and B) generally produces a 2N-bit number for the product. The elementary division operation of two N-bit numbers A and B generally produces an N-bit number for the quotient. The software emulations may be applicable to both vector processors and processors performing operations in a scalar way.
Several example implementations of software implementations for double precision operations may be provided below. The examples generally include the operations 1/X, square root of X and square root of (1−X2). Other operations may be implemented to meet the criteria of a particular application. Many different operations Y=F(X) may be calculated at double precision using the software where single precision versions of the operations exists in the hardware of the processor. Each operation Y=F(X) should include an inverse operation X=G(Y). The inverse operations may be either (i) implemented in the processor at the single precision or (ii) expressed through processor commands with small complexity. The software technique described herein may generate a result value in a single pass through a set of calculations. An accuracy of the result value generally permits usage in real applications.
The software technique generally allows 2N-bit precision software implementations of complex functions to be built in terms of already implemented basic functions by applying superposition. An accuracy of such implementations generally depends on the basic functions and may be verified by direct testing. The technique described below was successfully tested on a 1/square root (x) operation as an example.
By way of a specific example, consider a function Y=1/X. Values X0 and Y0 may be N-bit fixed point numbers that satisfy several relationships as follows: X0=[X·2(N−1)], Y0=[Y·2(N−3)], Y=1/X, where ¼≦X≦1 and 1≦Y≦4. The notation “[Z]” generally means taking an integer portion of the value Z, where Z may be a fixed point number. The above conditions are generally fulfilled for many processors operating in with fixed point numbers. Typical values for N may include, but are not limited to, 16 or 32.
Referring to
The method 100 may be applied to a processor generally having the operations of addition, subtraction, multiplication and arithmetic shift right by a constant K (e.g., a division by 2K) implemented in hardware. The addition operation and the subtraction operation may be performed by the processor on 2N-bit numbers, where N is a digit capacity of the processor(e.g., N=16, 32, 64, 128, etc.). The multiplication operation may implement a double precision integer multiplication for single precision arguments. For example, the multiplication operation generally has two N-bit arguments and a 2N-bit result. The division operation may be implemented as an N-bit precision division of two N-bit arguments.
In the step 102, a function (or operation) Y=F(X) may be defined by the designer (or programmer or engineer). An analogous function Y0=F(X0) may be implemented in the hardware of the processor using an N-bit fixed point argument value so that Y0=F(X0) holds for any X, Y and Y=F(X) where X0=[X·2N] and Y0=[Y·2N]. In the step 104, an inverse function X=G(Y) may be defined. The function G is generally an inverse of the function F. The function G may be implemented in the hardware of the processor with an N-bit fixed point argument.
To implement the function Y=F(X) with double precision (e.g., 2N bits), an operation Φ may be determined such that (Y0, Y1)=Φ(X0, X1). The operation Φ generally provides for the transfer of the values X0, X1 to the values Y0,Y1. The values Y0, Y1, X0 and X1 may be defined as follows: X0=[X·2N], Y0=[Y·2N], X1=[X·2(2N)−2N·X0] and Y1=[Y·2(2N)−2N·Y0].
In the step 106, approximations for the values X and Y may be determined. The value of X may be approximated as X=(X0·2N+X1)/2(2N). The value of Y may be approximated as Y=(Y0·2N+Y1)/2(2N). The implicit equation X=G(X) may be solved by the designer for Y1 in the step 108 in terms of X, X0, X1 and Y0. The solution may be achieved by performing arithmetic operations that are inverse to the operations involved in G. Where possible, nonlinear conditions in the Y members may not be taken into account if the nonlinear conditions poorly influence calculation accuracy. Once the value of Y1 has been determined, the operation Y=F(X) may be expressed in step 110 as Y=(Y0·2N+Y1)/2(2N). An accuracy of the technique for calculating the (Y0, Y1)=Φ(X0, X1) function may by performed by either complete testing or representative random testing.
The method 100 described above in general form was tested for software increasing the precision for the following function implementations: Y=1/X, Y=√{square root over (X)} and Y=√{square root over (1−X2)}. The software complexity and error rate generally depend on the particular function that should be implemented. As the testing showed, in many cases the error rate is sufficiently valid for solving real problems. The speed of the technique may be high compared with existing approaches.
Referring to
In the step 122, based on the capabilities of a target processor, a value of N, an operation F1(X), a range of an argument (input) value X and a range of a result (output) value Y may be determined. Suppose that the processor has a function for calculating the inverse of the value X (e.g., Y=F1(X)=1/X) implemented with N-bit (e.g., 16-bit) precision. The range of the value X may be limited to unity or less (e.g., X≦1). For Y=1/X, the range of the value Y may be at least 1 (e.g., 1≦Y). To limit the upper value of Y, an upper boundary (e.g., 7) may be imposed on the range of Y (e.g., 1≦Y≦7).
In the step 124, a location of a radix point in the value X may be determined based on the range of the value X. In the above example, since the value X is no greater than unity, the radix point (e.g., period) may be located at position A such that the value X may be represented by a 1-bit integer portion (e.g., A=1) and a 31-bit fractional portion (see
In the step 126, a location of a radix point may be determined based on the range of the value Y. In the above example, since the value Y is no greater than seven, the radix point may be located a position B such that the value Y may be represented by a 3-bit integer portion (e.g., B=3) and a 29-bit fractional portion (see
In the step 128, a value X0 may be calculated. Generally, the value X0 may be a 16-bit integer that satisfies X=X0/215, Y=1/X and X is a real number. As such, the value X0 may be expressed as X0=[X·2(N−A)] (e.g., X0=[X·215]). By multiplying the value X by 215, the radix point is effectively moved right to a middle position of the 32-bit number (see
In the step 130, a value X1 may be calculated. The value X1 may be a 16-bit integer calculated as X1=[X·2(2N−A)−2N·X0] (e.g., X1=[X·2−−216·X0]). Multiplication of the value X by 231 may right-shift the radix point to the right end of the 32-bit number. Multiplication of the value X0 by 216 may expand the 16-bit value to a 32-bit value, with the lower 16 bits being zeros. Subtraction of the shifted value X0 from the shifted value X generally sets to zero the 16 upper bits leaving only the lower 16 bits in the result. The value X1 may be an integer representation of a least significant half (e.g., lower 16 bits) of the value X.
In the step 132, a value Y0 may be calculated. Generally, the value Y0 may be a 16-bit integer that satisfies Y=Y0/213, Y=1/X and Y is a real number. As such, the value Y0 may be expressed as Y0=[Y·2(N−B)] (e.g., Y0=[Y·213]) . By multiplying the value Y by 213, the radix point is effectively moved right to a middle position of the 32-bit number (see
In the step 134, a value Y1 may be calculated. The value Y1 may be a 16-bit integer calculated as Y1=[Y·2(2N−B)−2N·Y0] (e.g., Y1=[Y·229−216·Y0]). Multiplication of the value Y by 229 may right-shift the radix point to the right end of the 32-bit number. Multiplication of the value Y0 by 216 may expand the 16-bit value to a 32-bit value, with the lower 16 bits being zeros. Subtraction of the shifted value Y0 from the shifted value Y generally sets to zero the 16 upper bits leaving only the lower 16 bits in the result. The value Y1 may be an integer representation of a least significant half of the value Y.
In the step 136, an approximation of the value X may be calculated. The approximation of the value X may be the value X1 appended to the end of the value X0 and the radix point restored to the original position. Implementing the calculation in hardware and software may be achieved as X=(2N·X0·X1)/2(2N−A) (e.g., X=(216·X0+X1)/231).
In the step 138, an approximation of the value Y may be calculated. The approximation of the value Y may be the value Y1 appended to the end of the value Y0 and the radix point restored to the original position. Implementing the calculation in hardware and software may be achieved as Y=(2N·Y0+Y1)/2(2N−B) (e.g., Y=(216·Y0+Y1)/229).
The function (Y0,Y1)=Φ1(X0,X1) may be built using only processor arithmetic operations and the Y=F1(X) operation. In the step 140, an inverse function G1 may be determined for the function F1. For the example of F1(X)=1/X, the inverse may be G1(X)=X. The approximations for the value X and the value Y may be inserted into the implicit equation Y=G1(X) in the step 142. The implicit equation may be expressed as follows:
Y=(2·Y0+Y1)/229=G1((2≠·X0+X1)/2−)=(216·X0+X1)/231
The above implicit equation may be solved for the value Y1 in the step 144.
At the end of the step 144, an equation may be available to calculate the values X0 in terms of the value X. An equation may also be available to calculate the value X1 in terms of the values X and X0. The hardware function F1 may be available to calculate the value Y0 from the value X0 (e.g., Y0=F1(X0)). An equation may also be available to calculate the value Y1 in terms of the values X, X0 and Y0. Furthermore, an equation may be available to calculate the approximate value Y from the values Y0 and Y1. Using the available equations, software (e.g., processor executable instructions) may be generated to emulate the function F1 with double precision in the step 146. The software may be generated by the designer and/or by a common code generating machine that translates the equations into the software.
Everywhere above, a division by 2N may be produced by applying logical shift right. For example, a value A/2N=A>>N, where the notation “>>N” may represent the logical shift right by N bits.
Consider a situation where each of the above mentioned operations (e.g., multiplications, additions, 1/X and logical shifts) take place in a single processor cycle. Moreover, the domain of the functions may be restricted. Different cases generally result in different restrictions. Accordingly, a complexity for the 1/X computation may be approximately 7 processor cycles. Model testing generally shows that a maximum error in the value Y does not exceed 3 bit values, where 230≦X≦231 and Xε[½,1).
In another example implementation, a mathematical operation may be defined as Y′=F2(X)=√{square root over (X)}. Furthermore, the processor may include the operation Y=F1(X)=1/X in the hardware at the 16-bit precision. Therefore, the function Y′=F2(X) may be calculated, where X and Y′ may be 16-bit integers that satisfy X=X0/215, Y′=Y0′/215, Y′=√{square root over (X)} and X, Y may be real numbers.
The method 120 may be by followed to build a software implementation for a square root of X operation for 32-bit numbers. As in the example for Y=1/X, the value N, F2(X), range of X and range of Y′ may be determined in the step 122. In the steps 124 and 126, the values of A and B may be calculated (e.g., A=1 and B=1 in the example). The value X0 may be determined in the step 128 as X0=[X·215]. The value X1 may be calculated in the step 130 as X1=[X·231−216·X0].
In the step 132, the value Y0′ may be calculated as Y0′=[Y′·215]. The value Y1′ may be calculated in the step 134 as Y1′=[Y′·231−216·Y0′]. In the step 136, an approximation of the value X may be calculated as X=(216·X0+X1)/231. In the step 138, an approximation of the value Y′ may be calculated as Y′=(216·Y0′+Y1′)/231. The function (Y0′,Y1′)=Φ2(X0,X1) may be built using the processor arithmetic operations and the Y′=F2(X) operation. The inverse operation G may be determined in the step 140.
The solutions of the implicit equation for the function may be calculated in steps 142 and 144 as follows: Y′=F2(X) and Y1′=(Z·d1)/213+(Z·X1)/214 where d1=215·X0−(Y′)2 and Z=F1(Y′). In the step 146, software implementing the equations may be generated.
If a complexity of the F2(X) calculation may be considered as 1, a complexity of a 32-bit version of the F2(X) computation may be 10 processor cycles. Model testing generally shows that a maximum error in the value Y′ generally does not exceed 3 bit values, where 230≦X≦231 and Xε[½, 1).
In still another example implementation, a mathematical operation may be defined as Y″=F3(X)=√{square root over (1−X2)}. Furthermore, the processor may implement the operations F3(X) and F1(X) in the hardware at 16-bits precision. Therefore, the function Y″=F3(X) may be calculated, where X and Y″ may be 16-bit integers that satisfy X=X0/215, Y″=Y0″/215, Y″=√{square root over (1−X2)} and X, Y may be real numbers.
The method 120 may be by followed to build a software implementation for a square root of (1−X2) operation for 32-bit numbers. As in the earlier examples, the value N, F3(X), range of X and range of Y″ may be determined in the step 122. In the steps 124 and 126, the values of A and B may be calculated (e.g., A=1 and B=1 in the example). The value X0 may be determined in the step 128 as X0=[X·215]. The value X1 may be calculated in the step 130 as X1=[X·231−216·X0].
In the step 132, the value Y0″ may be calculated as Y0″=[Y″·215]. The value Y1″ may be calculated in the step 134 as Y1″=[Y″·231−216·Y0″]. In the step 136, an approximation of the value X may be calculated as X=(216·X0+X1)/231. In the step 138, an approximation of the value Y″ may be calculated as Y″=(216·Y0″+Y1″)/231. The function (Y0″,Y1″)=Φ3(X0,X1) may be built using only processor arithmetic operations and the Y″=F3(X) operation. The inverse operation G may be determined in the step 140.
The solutions of the implicit equation for the function may be calculated in steps 142 and 144 as follows: Y″=F3(X) and Y1″=(δZ″)/213−(X0X1)/220·(Z″/228,)where Z″=F1(Y″) and δ=230−(X0)2−(Y″)2. In the step 146, software implementing the equations may be generated.
If a complexity of the F3(X) operation may be considered as 1, a complexity of 32-bit version of F3(X) operation may be 14 processor cycles. Model testing generally shows that a maximum error of the value Y″ does not exceed 6 bit values, where 0≦X≦[(231√{square root over (3)})/2] and Xε[0,(√{square root over (3)})/2).
Referring to
The circuit 162 may implement a memory circuit. The circuit 162 is generally operational to store one or more software programs (e.g., sets of instructions) 166. Each software program 166 when executed by the circuit 164 may approximate a double precision mathematical operation. The calculations performed in generating the approximation may include using a single precision version of the mathematical operation implemented in the hardware of the circuit 164.
The circuit 164 may implement a processor circuit. The circuit 164 is generally operational to perform a variety of arithmetic operations and logical operations based on the software 166 received from the circuit 162. The circuit 164 may include a register 168 configured to buffer the value X. The register 168 may be sufficiently wide to store the value X in a fixed point format at a double precision (e.g., 2N bits). The circuit 164 may also include a register 170. The register 170 may be configured to buffer the value Y, Y′, Y″ or similar. The register 170 may be sufficiently wide to store the values in a fixed point format at the double precision. In some embodiments, the register 168 may be an input register used to store the argument values for one or more mathematical operations calculated by the software 166 executing on the circuit 164. The register 170 may be an output register used to store the result values calculated by the mathematical operations.
The circuit 164 may also include one or more operations (or functions) implemented in the hardware alone. The operations may include the elementary operations and one or more mathematical operations. The elementary operations may include, but are not limited to, addition, subtraction, multiplication and division.
Most to all of the elementary operations may by designed to operate with fixed point (or integer) numbers at double precision. The mathematical operations (e.g., Y=F(X)) may include, but are not limited to, at least one of the inverse operation, the square root operation and the square root of (1−X2) operation. All of the mathematical operations maybe designed to operate with fixed point (or integer) numbers at single precision. Other operations may be implemented to meet the criteria of a particular application.
Referring to
In the step 182, the value X representing an argument of a selected operation may be received in the register 168. The software 166 may have a previously coded determination that the selected operation is either a single precision operation or a double precision operation. If the selected operation is not a double precision operation (e.g., the NO branch of step 184), the value X may be transferred to the corresponding circuitry of the operation 172 implemented in the hardware of the circuit 164. The hardware operation 172 may calculate the result value Y in the step 186.
If the selected operation is a double precision operation (e.g., the YES branch of step 184), the software 166 may configure the circuit 164 to calculate the value X0 for the selected operation in the step 188. In the step 190, the software 166 may configure the circuit 164 to calculate the value X1 for the selected operation. The software 166 may further configure the circuit 164 in the step 192 to calculate the value Y0 using the selected operation, as implemented in the hardware, with the value X0 as the argument. In the step 194, the software 166 may configure the circuit 164 to calculate the value Y1. Once the values X0, X1, Y0 and Y1 have been generated, the software 166 may further configure to the circuit 164 to calculate an approximation for the value Y in the step 196. The value Y as calculated in either the step 186 or the step 196 may be buffered in the register 170 in the step 198. Hence, a combination of the software 166 and the hardware of the circuit 164 may emulate a double precision version of the selected operation. The emulation may utilize the single precision hardware version of the selected operation in calculating the value Y. The emulation may avoid the expense of converting to and from floating point numbers.
As mentioned above, superposition may be applied in some cases to several already implemented functions to obtain double precision implementations of the single precision operation. Sometimes, solving the implicit equation is not an easy task for the designer. In order to avoid a difficult solution, the function may be expressed in terms of existing functions.
The above techniques were tested for a 32-bit precision function 1//√{square root over (X)}, which is a superposition of the 32-bit precision functions 1/X and √{square root over (X)}. Complexity of the superposition approach may be approximately a sum of the complexities of each component. The function 1/√{square root over (X)} may have approximately a 17 processor cycle complexity. Testing of the 32-bit version of the function 1/√{square root over (X)} generally showed that not more than 7 low bits of the result may be incorrect.
The functions performed by the diagram of
The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more monolithic integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s).
The present invention thus may also include a computer product which may be a storage medium or media and/or a transmission medium or media including instructions which may be used to program a machine to perform one or more processes or methods in accordance with the present invention. Execution of instructions contained in the computer product by the machine, along with operations of surrounding circuitry, may transform input data into one or more files on the storage medium and/or one or more output signals representative of a physical object or substance, such as an audio and/or visual depiction. The storage medium may include, but is not limited to, any type of disk including floppy disk, hard drive, magnetic disk, optical disk, CD-ROM, DVD and magneto-optical disks and circuits such as ROMs (read-only memories), RAMs (random access memories), EPROMs (electronically programmable ROMs), EEPROMs (electronically erasable ROMs), UVPROM (ultra-violet erasable ROMs), Flash memory, magnetic cards, optical cards, and/or any type of media suitable for storing electronic instructions.
The elements of the invention may form part or all of one or more devices, units, components, systems, machines and/or apparatuses. The devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palm computers, personal digital assistants, portable electronic devices, battery powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers, cipher circuits, cellular telephones, digital cameras, positioning and/or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, storage and/or playback devices, video recording, storage and/or playback devices, game platforms, peripherals and/or multi-chip modules. Those skilled in the relevant art(s) would understand that the elements of the invention may be implemented in other types of devices to meet the criteria of a particular application.
As would be apparent to those skilled in the relevant art(s), the signals illustrated in
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011115796 | Apr 2011 | RU | national |
