DOUBLE QUADRATURE WITH ADAPTIVE PHASE SHIFT FOR IMPROVED PHASE REFERENCE PERFORMANCE

Abstract

A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.

Description

TECHNICAL FIELD

This disclosure relates to an equivalent time system in a sampling test and measurement instrument to reduce the amount of jitter in a test and measurement instrument. Specifically, the disclosure relates to calculating a timing correction via a clock signal to reduce the amount of jitter in a test and measurement instrument.

BACKGROUND

In an equivalent time sampling oscilloscope, a phase reference module is used to compensate for jitter in the time base of the oscilloscope. Two signals are measured—a data signal and a clock signal. The clock signal is a sinusoid or a similar sine-like signal that is aligned to the data signal. The data signal, on the other hand, can be almost any other type of signal. Traditionally, timing errors are calculated by the system shown in FIG. 1. The timing correction is made to the data signal by measuring the phase of the clock signal and using the clock signal phase measurement to adjust the timing of the data signal based on the calculated error.

FIG. 1 depicts a traditional timing correction system traditionally used in time sampling oscilloscopes. A clock signal 102 synchronized to the data is input into the system 100 through the clock signal input 100. The clock signal 102 is split into two clock signals 104 and 106 via a splitter 120.

Each clock signal 104 and 106 is sent to a respective sampler 108 and 110. Samplers 108 and 110 sample the clock signal at different phases that are ideally 90 degrees apart. That is, the samplers 108 and 110 are strobed by a strobe 122 at 90 degrees offset from each other. The samplers are set to strobe at times that are separated by 90 degrees so that the in-phase and quadrature components of the clock signal can be measured. When the phase between the two samples taken by the samplers 108 and 110 are exactly 90 degrees apart, the error made in estimating the phase of the clock signal is a function of only the amplitude noise of the clock and noise present in the samplers 108 and 110.

The output signals from the samplers 108 and 110 are each input into respective analog-to-digital converters (ADC) 112 and 114. The digitized signals are then sent to the phase measurement unit 116 so the phases of the digitized signals can be calculated. Once the phases have been calculated, a timing correction can be calculated in a processor 118. The in-phase and quadrature components of the digitized signal are used to estimate the phase of the clock, and from the phase of the clock the timing error of the sampling test and measurement instrument can be estimated.

Because the actual difference between the two samples is not exactly 90 degrees, the jitter measured by the scope becomes a function of the phase of the signal. This leads to non-repeatable results where different values or jitter are measured depending on the phase difference between the clock and a measured data signal by the oscilloscope. This causes different parts of the measured data signal to have potentially different amounts of jitter depending on the phase of the clock at the point of the measurement. This is non-ideal and can lead to user confusion.

SUMMARY

Certain embodiments of the disclosed technology include a method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal that is split into a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. The first clock signal is routed to a first sampler, the second clock signal is routed to a second sampler, the third clock signal is routed to a third sampler; and the fourth clock signal is routed to the fourth sampler. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.

Certain embodiments of the disclosed technology include a timing error correction system for use in a test and measurement instrument. The timing error correction system includes a clock input, a splitter configured to split the clock signal into four clock signals; four samplers, each sampler configured to receive one of the four clock signals and configured to output a sampled signal, at least two analog-to-digital converters configured to receive the output sampled signals from the four samplers, and a processor configured to calculate a timing correction error based on the digitized outputs of the four samplers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a traditional timing correction system used in a sampling test and measurement instrument.

FIGS. 2 and 3 illustrate block diagrams of embodiments of a timing correction system used in a sampling test and measurement instrument according to the disclosed technology.

DETAILED DESCRIPTION

In the drawings, which are not necessarily to scale, like or corresponding elements of the disclosed systems and methods are denoted by the same reference numerals.

The disclosed technology reduces the amount of jitter in an equivalent time sampling test and measurement instrument. The equivalent time system reduces jitter by accurately measuring and then correcting the timing errors of a sampling test and measurement instrument. The disclosed technology reduces the amount of error in the time estimation and thereby reduces the total jitter present in a measurement of a data signal, as discussed in more detail below. FIG. 2 depicts some embodiments of the equivalent time system of the disclosed technology. The system includes an input 200 for a clock signal 202. The clock signal 202 is a sinusoid or similar sine like signal that is aligned to a data signal. The clock signal 202 is split into four clock signals 204, 206, 208 and 210. The clock signal may be split by using a splitter 234. Each of the clock signals 204, 206, 208, and 210 are received at a respective sampler 212, 214, 216, and 218.

The first set of samplers 212 and 214 are strobed by a strobe 236 to be out of phase by 90 degrees, similar to samplers 108 and 110 in FIG. 1 discussed above. The phase delay is added not by delaying the incoming clock signal, but by adjusting the timing of the strobe. The phase delay is added by adjusting the timing of the strobe, rather than delaying the incoming clock signal. The strobe adjusts when the signal is measured. Because the timing of the strobe is not exact, a small amount of uncertainty is present in the timing of the strobe. The uncertainty causes a divergence from the ideal 90 degrees that is required for the optimal quadrature measurement.

Therefore, the second set of samplers 216 and 218 are also strobed by a strobe 236 to be out of phase by 90 degrees with each other. However, the second set of samplers 216 and 218 are strobed with a delay that is offset from the first set of samplers 212 and 214, so that a different portion of the clock signal can be measured. Therefore, sampler 216 is offset from sampler 212 by 45 degrees and sampler 218 is offset from sampler 214 by 45 degrees. Therefore each of the samplers are set to strobe at times separated by 45 degrees. This allows for greater accuracy in determining the timing error by measuring the signal at more phases. By adding the two additional samplers 216 and 218 that have an additional phase adjustment delay with reference to the first set of samplers 212 and 214, the total jitter as well as the variability can be reduced.

The outputs from each of the samplers 212, 214, 216, and 218 are digitized through respective analog-to-digital converters (ADC) 220, 222, 224, and 226. The digitized outputs from the first set of samplers 212 and 214 are inputted to a phase measurement unit 228 and the digitized outputs from the second set of samplers 216 and 218 are inputted to a phase measurement unit 230. The phase measurement units 228 and 230 may be, for example, processors. The phase measurement units 228 and 230 determine the phase difference between samplers 212 and 214, and 216 and 218, respectively. The phase differences are sent to processor 232 and processor 232 determines the average of the phase differences and calculates a timing correction based on the average. Alternatively, the phase measurement units 228 and 230 may be part of the processor 232. Or, phase measurement units 228 and 230 can be located in a single processor separate from processor 232.

Once the timing correction has been determined, the test and measurement instrument uses this correction to correct the timing of the measured data signal. This allows the measured data signal to be placed in the proper order of acquisition.

The advantage of the system shown in FIG. 2 is that when the delay is 45 degrees between each of the samplers, the jitter dependence on the phase of the clock is entirely removed. This eliminates the variation and reduces the total jitter by approximately 40%. Although the above system is preferred as it is the most accurate, it requires two additional analog-to-digital converters within the test and measurement instrument.

It may be preferable to use two ADCs to avoid the need for additional analog to digital converters (ADCs). FIG. 3 depicts an alternative embodiment of the disclosed technology using only two ADCs.

As seen in FIG. 3, this system also includes an input 300 for a clock signal 302. The clock signal 302 is also split into four clock signals 304, 306, 308 and 310 using a splitter 332. Each clock signal 304, 306, 308, and 310 is received by a respective sampler 312, 314, 316, and 318, as discussed above with respect to FIG. 2. Same as with the embodiment discussed with respect to FIG. 2, each of the samplers are strobed to be out of phase by 45 degrees by a strobe 334.

However, rather than the outputs of the samplers 321, 314, 316, and 318 being input into ADCs, as discussed above with respect to FIG. 2, the analog output from sampler 312 and the analog output from sampler 316 are summed together by a summer 320, and the analog output from sampler 314 and the analog output from sampler 318 are summed together by a summer 322.

Each of the outputs from the summers 320 and 322 are then digitally converted by ADCs 324 and 326, respectively. The output from the ADCs 324 and 326 are input to the phase measurement unit 328. The phase measurement unit 328 determines the phase difference between the output of the summer 320 and the output of the summer 322. Then, a timing correction can be calculated via processor 330. Again, the phase measurement unit 328 may be located within the processor 330.

As mentioned above, the timing error correction system includes a processor and a memory (not shown) to store executable instructions for implementing the above discussed processors of the test and measurement instrument. Computer readable code embodied on a computer readable medium, when executed, causes the computer to perform any of the above-described operations. As used here, a computer is any device that can execute code. Microprocessors, programmable logic devices, multiprocessor systems, digital signal processors, personal computers, or the like are all examples of such a computer. In some embodiments, the computer readable medium can be a tangible computer readable medium that is configured to store the computer readable code in a non-transitory manner.

Having described and illustrated the principles of the disclosed technology in a preferred embodiment thereof, it should be apparent that the disclosed technology can be modified in arrangement and detail without departing from such principles. We claim all modifications and variations coming within the spirit and scope of the following claims.

Claims

1. A method for correcting a timing error in a test and measurement instrument, comprising: receiving a clock signal;splitting the clock signal into a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal;routing the first clock signal to a first sampler, a second clock signal to a second sampler, a third clock signal to a third sampler; and a fourth clock signal to a fourth sampler;sampling the first clock signal at the first sampler at a first phase, sampling the second clock signal at the second sampler at a second phase that is 90 degrees offset from the first phase, sampling the third clock signal at the third sampler at a third phase that is 45 degrees offset from the first phase, and sampling the fourth clock signal at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase;digitizing each of the outputs from the samplers; andcalculating a timing correction based on the digitized outputs from the digitized outputs.

2. The method of claim 1, wherein the outputs from the first sampler and the third sampler are summed, and the outputs from the second sampler and the fourth sampler are summed prior to the digitizing.

3. The method of claim 1, wherein the calculating a time correction includes: calculating a first phase measurement between the first sampler and the second sampler,calculating a second phase measurement between the third sampler and the fourth sampler, andaveraging the first and the second phase measurement.

4. The method of claim 1, further including modifying timing of a data signal based on the calculated timing correction.

5. A timing error correction system for use in a test and measurement instrument, comprising: a clock signal input configured to receive a clock signal;a splitter configured to split the clock signal into four clock signals;four samplers, each sampler configured to receive one of the four clock signals and configured to output a sampled signal;at least two analog-to-digital converters configured to receive the output sampled signals from the four samplers; anda processor configured to calculate a timing correction error based on the digitized outputs of the four samplers.

6. The timing error correction system of claim 5, wherein each sampler of the four samplers is strobed to be offset 45 degrees from at least one of the other samplers.

7. The timing error correction system of claim 5, further comprising four analog-to-digital converters, each analog-to-digital converter configured to receive one of the four outputs from the four samplers, wherein the processor is configured to calculate the timing correction error by calculating a first phase measurement between the first sampler and the second sampler, calculating a second phase measurement between the third sampler and the fourth sampler, and averaging the first and the second phase measurement.

8. The timing error correction system of claim 5, further comprising: a first summer configured to sum the output from the first sampler and the output from the third sampler;a second summer configured to sum the output from the second sampler and the output from the fourth sampler,wherein the outputs from the first summer and the second summer are each sent to the at least two analog-to-digital converters.

9. The timing error correction system of claim 5, wherein the processor is further configured to correct a timing of a data signal based on the calculated timing correction.