Patent Grant
7016211
The present invention relates to integrated circuit content addressable memories (CAMs). More specifically, the present invention relates to dynamic random-access-memory-based (DRAM-based) CAMs.
Conventional read-write or “random access” memories (RAMs) include RAM cells arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells. That is, data words stored in the rows of conventional RAM cells are accessed by applying address signals to the RAM input terminals. In response to each write or read command a RAM receives, a data word is written to or read from a portion of the RAM array designated by the address.
In addition to the read-write capability of conventional RAMs, content addressable memories (CAMs) include memory cells that are selected in response to their content. Specifically, a CAM receives a (search key) data value that is compared with all of the (entry) data values stored in the many rows of the CAM. In response to each unique (search term) data value applied to the CAM input terminals, the rows of CAM cells within the CAM assert or de-assert associated match signals indicating whether or not the stored (entry) data values in that respective row of CAM cells matches the (search key) data value being searched by and applied to the CAM. CAMs are useful in many applications, such as search engines.
Similar to conventional RAM devices, CAM devices can either be formed utilizing dynamic random access memory (DRAM) cells, in which data values are stored using capacitors, or formed utilizing static random access memory (SRAM) cells, in which data values are stored using bistable flip flops.
During a data write operation (or during the write phase of a refresh operation), a data value to be stored is written to dynamic storage nodes a and b by applying appropriate voltage signals (e.g., VCC or ground) on bit lines BL1 and BL2, and then applying a high voltage signal on write word lines WL1 and WL2, which may be combined to form a single word line. The high voltage on write word lines WL1 and WL2 turn on transistor Q1 and Q2, thereby passing the voltage signals (data to be stored) to dynamic storage nodes a and b without Vt loss due to NMOS threshold voltage. Because the voltage signals are stored using capacitors C1 and C2 and the charge slowly leaks off, the stored data value decays over time. Refresh circuitry is required that periodically reads and rewrites (refreshes) the stored data value before it is lost.
This CAM cell can stores three different states, “1”, “0”, or “masked” (don't care). When the CAM cell stores the data value “1”, node “a” stores “1” and node “b” stores “0”. When the CAM cell stores the data value “0”, node “a” stores “0” and node “b” stores “1”. When the CAM cell is in masked (don't care) state, both node “a” and “b” store “0”. The data value stored at storage nodes a and b is applied to the gate terminals of transistors Q3 and Q5 of comparator circuit 14. Comparator circuit 14 is utilized to perform match (comparison) operations by precharging a match line MATCH and transmitting an applied data value on data lines D1-bar and D1 to the gate terminals of transistor Q4 and Q6, respectively. A no-match condition is detected when match line MATCH is discharged to ground through the signal path formed by transistors Q3 and Q4, or through the signal path formed by transistors Q5 and Q6 in any CAM cell connected to the match line. For example, when the stored data bit is “1” ,which means node “a” is “1” and node “b” is “0”, and the applied data signal is “0”, which means D1 is “0” and D1-bar is “1”, then both NMOS transistors Q3 and Q4 are turned on because both gate inputs, “a” and “D1-bar”, are logic “1”, to discharge match line MATCH to discharge line DISCHARGE when discharge line DISCHARGE is driven to a low voltage (e.g., ground). When a match condition occurs, match line MATCH remains in its precharged state (i.e., no signal path is formed by transistors Q3 and Q4, or transistors Q5 and Q6 in any of the CAM cells connected to the match line).
A problem with DRAM-based CAM 10 arises because of the construction of the capacitor C1 and C2 using a special multi-layer polysilicon fabrication process that significantly increases fabrication time and expense, which reduces the cost efficiency of smaller cell size. In addition to time and cost problems, thermal process step during polysilicon process reduces the transistor performance.
More significantly, conventional DRAM-based CAM cell 10 is limited in that a match (lookup or search) operation performed by comparator circuit 14 will be disturbed by a simultaneous read or refresh operation. When conventional DRAM cells 12 and 16 are refreshed (or read), the voltage on the storage node (a or b) initially shares its (positive or negative) charge with its associated bit line, which is precharged to about half of Vcc. If data in the cell is “1”, the voltage levels on both storage node and bit line after charge sharing become slightly higher than initial precharge level of bit line. If data in the cell is “0”, the voltage levels on both storage node and bit line after charge sharing become slightly lower than initial precharge level of bit line. The slight increase or decrease in bit line voltage is detected and amplified by a sense amplifier (not shown), which in turn drives the bit line high or low as needed to return the storage capacitor of the memory cell to its initial (undecayed) voltage. Between the time the charge from the storage capacitor is transferred to the bit line and the time the charge (voltage) is restored, comparator circuit 14 cannot be used for search operations because the voltage on the storage nodes (a and b) are about one-half of the system voltage, rather than being its normal logic level (i.e., either the system voltage or ground voltage). That is, the periodic refreshing needed by DRAM cells 12 and 16 interrupts search or lookup operations.
Accordingly, what is needed is a CAM cell that provides a size (cost) advantage over that provided by a SRAM-based CAM cell, but avoids the problems associated with conventional DRAM-based CAM cells.
The present invention is directed to DRAM-based ternary (ternary CAM cells store a “1”, a “0”, or a “don't care” which is called “masked”) CAM cells that overcome the problems associated with conventional CAM cells by utilizing a pair of three-transistor (3T) DRAM cells and only two pairs of bit lines to facilitate refresh, read, and write operations, where a read port of each DRAM is coupled to a write port of either DRAM via the bit bines. A compare circuit and a second pair of data (bit) lines allow search (compare) operations to occur simultaneously with read, write, or refresh operations. By using 3T DRAM cells and only two bit line pairs, less substrate area is required to fabricate each CAM cell, when compared to conventional CAM cells utilizing larger SRAM memory cells and/or DRAM memory cells utilizing more than two bit line pairs for the read, write and restore functions. By allowing refresh operations to be performed simultaneously with search operations, CAM arrays of the present invention allow uninterrupted search operations, whereas, with conventional 1T DRAM CAM arrays, simultaneous search and refresh operations are not possible.
In accordance with the embodiments disclosed herein, a CAM cell array includes DRAM-based CAM cells arranged in rows and columns, with each column of CAM cells being connected to an associated pair of bit lines and an associated pair of data lines, and each row of CAM cells being connected to an associated match line, an associated write word line, an associated read word line, and an associated discharge line. Each of these signal lines is controlled using well-known techniques to produce the operations described below.
In accordance with a first embodiment of the present invention, a ternary CAM array is disclosed that includes an array of ten transistor (10T) DRAM-based CAM cells. Each CAM cell includes a pair of 3T DRAM cells, a true cell and a complementary cell, for storing two data value (i.e., a two-bit value representing a logic “1” (storage nodes are high for true cell, low for complementary cell), a logic “0” (storage nodes are low for true cell, high for complementary cell), or a mask value (storage nodes are low for true cell, low for complementary cell)), and a four transistor comparator circuit that discharges a match line when the (unmasked) data value stored by the 3T DRAM cells is not equal to an applied (unmasked) data value provided from an external source. Each 3T DRAM cell is connected to an associated bit line, and each of these bit lines is connected to an inverting refresh circuit, and to a precharge circuit. Each 3T DRAM cell includes a write transistor connected between its associated bit line and a storage node, a pull-down transistor having one terminal connected to ground and a gate terminal connected to the storage node, and a read transistor connected between a second terminal of the pull-down transistor and the same bit line that is connected to the write transistor. The storage node of the first transistor is also connected to a first terminal of the comparator (specifically, to the gate terminal of a pull-down transistor, which is connected in series with a second transistor that is controlled by an applied data value). During refresh, the read transistor is turned on to pass an inverted data signal (i.e., the logical inverse of the data bit stored at the storage node) onto the bit line, which had been precharged high by the precharge circuit. The inverted data signal is then re-inverted by the inverting refresh circuit (at one end of the column of CAM cells), and the write transistor is then turned on to pass the re-inverted data signal from the bit line to the storage node. The read and restore portions of the refresh operation are performed without ever compromising the voltage level of the stored data bit allowing search to occur during refresh operations. This is possible because the stored data bit is only used to control pull-down transistors of the 3T DRAM cell and of the comparator, thereby avoiding the charge sharing problems associated with 1T DRAM cells, and allowing increased bit line lengths (i.e., array size).
In accordance with a second embodiment of the present invention, each 10T DRAM-based CAM cell of a ternary CAM array includes a pair of 3T DRAM cells for storing a two-bit data value, and a four-transistor comparator circuit, which are constructed similar to the arrangement of the first embodiment (described above). However, unlike the first embodiment, each 3T DRAM cell is cross-coupled to the associated pair of bit lines. Specifically, the write transistor of a first 3T DRAM cell is connected to the first bit line, and the read transistor of the first 3T DRAM cell is connected to the second bit line. Conversely, the write transistor of a second 3T DRAM cell is connected to the second bit line, and the read transistor of the second 3T DRAM cell is connected to the first bit line. In addition, an inverting refresh circuit includes first and second portions that pass inverted data signals between the pair of associated bit lines during refresh operations. That is, a first portion of the inverting refresh circuit reads and inverts a data signal from the first bit line, and then transmits the inverted data signal to the second bit line. Conversely, the second portion of the inverting refresh circuit reads and inverts a data signal from the second bit line, and then transmits the inverted data signal to the first bit line. In addition to providing the benefits associated with the first embodiment, the second embodiment reduces power consumption by reducing bit line cycling during the refresh operation.
In accordance with a third embodiment of the present invention, a binary CAM array includes the cross-coupled, 10T DRAM-based CAM cells, but omits the inverting refresh circuits.
In yet another embodiment of the present invention, a DRAM memory array includes pairs of 3T DRAM cells that are cross-coupled in the manner described in the third embodiment, but omits the comparator circuit utilized to perform CAM functions.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:
Referring to the center of
Referring to the right side of CAM cell 110A, DRAM cell 210-1 includes a write (first) transistor T1, a pull-down (second) transistor T2, and a read (third) transistor T3. Write transistor T1 is connected between storage node S1 and a (first) write port WP1, which is connected to bit line BL1, and has a gate terminal connected to (controlled by) write word line WL. Pull-down transistor T2 includes a gate terminal connected to storage node S1, a first terminal connected to ground, and a second terminal connected to read transistor T3. Read transistor T3 is connected between the second terminal of pull-down transistor T2 and a (first) read port RP1, which is connected to bit line BL1, and has a gate terminal connected to (controlled by) read word line RL.
Referring to the left side of
Logic XOR-type comparator 220 is located between DRAM cells 210-1 and 210-2, and includes a first input terminal 221 connected to storage node S1 of DRAM cell 210-1, a second input terminal 222 connected to receive a true (non-inverted) bit of the applied data value transmitted on lookup line L, a third input terminal 223 connected to storage node S2, and a fourth input terminal 224 connected to receive an inverted bit of the applied data value transmitted on inverted lookup line L-bar. Comparator 220 includes a pull-down (fourth) transistor T4 connected in series with a search (fifth) transistor T5 between associated match line ML and discharge line DL (or ground). A gate terminal of pull-down transistor T4 is connected via first input terminal 221 to storage node S1. A gate terminal of search transistor T5 is connected to second input terminal 222 of comparator circuit 220. Accordingly, during search operations, pull-down transistor T4 and search transistor T5 turn on to discharge match line ML when both the data bit applied to first input terminal 221 (i.e., the data bit stored at storage node S1) and the data bit applied to second input terminal 222 (i.e., the true bit of the searched-for data value on lookup line L) are logic “one” (high voltage) data values. Comparator 220 also includes a pull-down (ninth) transistor T9 connected in series with a search (tenth) transistor T10 between associated match line ML and discharge line DL (or ground). A gate terminal of pull-down transistor T9 is connected via third input terminal 223 to storage node S2. A gate terminal of search transistor T10 is connected to fourth input terminal 224. Accordingly, during search operations, pull-down transistor T9 and search transistor T10 turn on to discharge match line ML when both the data value applied to third input terminal 223 (i.e., the data bit stored at storage node S2) and the data bit applied to fourth input terminal 224 (i.e., the inverted bit of the searched-for data value on inverted lookup line L-bar) are logic “one” (high voltage) data values.
In accordance with an embodiment of the present invention, both storage nodes S1 and S2 are formed by intrinsic capacitance produced primarily but not entirely by the gate to channel capacitance of the pull-down transistors respectively forming these nodes. For example, storage node S1 is formed primarily by the gate to channel capacitance of pull-down transistors T2 and T4. Similarly, storage node S2 is formed primarily by the gate to channel capacitance of pull-down transistors T7 and T9. These intrinsic capacitances are sufficient to avoid the need for a discrete capacitor structure that typically requires a complex, triple layer polysilicon fabrication process. Accordingly, although 3T DRAM cell 210-1 or 210-2 is substantially larger than a conventional 1T DRAM cell, the fabrication process required to produce 3T DRAM cell 110A is less complex than that required to produce conventional 1T DRAM cells. In another embodiment, an optional discrete capacitor structure C1, shown coupled to an intermediate voltage source VCP, may be utilized to enhance the capacitance of 3T DRAM cell 110A.
Referring to the lower portion of
Referring to the upper portion of
During operation, ternary CAM array 100A controls the above circuits to perform write, search, and refresh operations on DRAM-based CAM cell 110A as described below.
During write and the restore portion of refresh operations, each ternary CAM cell 110A stores one of a logic “zero” data value, a logic “one” data value, or a masked (i.e., “don't care”) data value that are applied to the CAM cell in the selected row of CAM cells (WL selected high) via bit lines BL1 and BL2. According to one selected convention, a logic “zero” value is stored in ternary CAM cell 110A by applying a high voltage value on bit line BL1, applying a low voltage value on bit line BL2, and then applying a high voltage value on write word line WL to turn on write transistors T1 and T6, thereby passing the high voltage value from bit line BL1 to storage node S1 and passing the low voltage value from bit line BL2 to storage node S2. The voltage level of write word line WL needs to be higher than voltage level of “high” bit line plus threshold voltage of write transistor. Conversely, a logic “one” value is stored in ternary CAM cell 110A by applying a low voltage value on bit line BL1, applying a high voltage value on bit line BL2, and then applying a high voltage value on write word line WL, thereby passing the low voltage value to storage node S1 and the high voltage value to storage node S2. A mask value is written to ternary CAM cell 110A by applying low voltages on both bit lines BL1 and BL2, and then turning on write transistors T1 and T6 to pass the low voltage values to storage nodes S1 and S2.
During subsequent search operations, the two-bit data value stored in storage nodes S1 and S2 is compared with an applied two-bit (search key) data value, which is transmitted on lookup lines L and L-bar to all CAM cells of a selected column. A logic “one” (search key) data value is applied to lookup lines L and L-bar by applying a high voltage signal to true lookup line L and a low voltage signal to inverted lookup line L-bar. Conversely, a logic “zero” is applied to lookup lines L and L-bar by applying a low voltage signal to true lookup line L and a high voltage signal to inverted lookup line L-bar. When ternary CAM cell 110A stores a logic “zero” (using the convention established above) and a logic “one” search data value is applied on the lookup lines, the high voltage at storage node S1 turns on pull-down transistor T4 (pull-down transistor T9 is turned off by the low voltage stored on storage node S2), and the high voltage transmitted on lookup line L turns on search transistor T5, thereby discharging match line ML to ground through transistors T4 and T5 (no path is opened through transistors T9 and T10). Similarly, when ternary CAM cell 110A stores a logic “one” (using the convention established above) and a logic “zero” search data value is applied on the lookup lines, the high voltage at storage node S2 turns on pull-down transistor T9 (pull-down transistor T4 is turned off by storage node S1), and the high voltage transmitted on inverted lookup line L-bar turns on search transistor T10, thereby discharging match line ML to ground through transistors T9 and T10. When the applied search value matches the stored data value (i.e., both are logic “zero” or logic “one”), or when a mask value is stored by DRAM cells 210-1 and 210-2, i.e. both storage nodes S1 and S2 are low) or when a global mask is applied to the lookup lines (i.e. both L and L-bar are low) this cell will not discharge the match line during the search operation. For example, when a logic “zero” data value is stored and a logic “zero” search value is applied, the high voltage at storage node S1 turns on pull-down transistor T4, but the low voltage transmitted on true lookup line L causes search transistor T5 to remain turned off, thereby preventing discharge of match line ML through this discharge path. Similarly, the high voltage transmitted on compliment lookup line L-bar turns on search transistor T10, but the low voltage at storage node S2 causes pull-down transistor T9 to remain turned off, thereby preventing discharge of match line ML through that discharge path. When a mask value is stored, both pull-down transistors T4 and T9 remain turned off, thereby preventing discharge of match line ML by this CAM cell no matter what search value is applied. Likewise, when a mask value is applied to the lookup lines (both low), both search transistors T5 and T10 are off, thereby preventing discharge of match line ML no matter what data is stored in the cell.
In accordance with an aspect of the present invention, each CAM cell 110A performs simultaneous refresh and search operations using only two bit lines (i.e., bit lines BL1 and BL2) for the refresh operation and two lookup lines (i.e., L and L-bar) for search operation. The simultaneous performance of refresh and search operations is made possible by choosing a storage cell in which the voltage level of the storage nodes is not disturbed during the read phase of the refresh operation (i.e., a “non-destructive” read operation) and is unaltered or enhanced during the restore phase of the refresh operation. In particular, each 3T DRAM cell 210-1 and 210-2 and corresponding portion of comparator 220 are arranged such that the stored charge is applied to the gate terminal of pull-down transistors, and is not removed during read operations. For example, storage node S1 is connected to a terminal of write transistor T1 and to the gate terminals of pull-down transistors T2 and T4. Similarly, storage node S2 is connected to a terminal of write transistor T6 and to the gate terminals of pull-down transistors T7 and T9. As described in additional detail below, the refresh operation performed in accordance with the present invention only requires write transistors T1 and T6 to turn on during the restore phase, and that the charges stored in storage nodes S1 and S2 are not “shared” (i.e., transmitted through a transistor to a bit line) during the read phase of the refresh operation. Because the charges (voltages) stored at storage nodes S1 and S2 are not shared with the bit line which is precharged to about half Vcc as in conventional DRAM, the voltages applied to pull-down transistors T4 and T9 of comparator 220 remain relatively consistent during the read phase of the refresh operation and get enhanced during the write phase of the refresh operation. Since the voltages on the gates of the pull-down transistors T4 and T9 of comparator 220 remain valid throughout a refresh operation, the refresh operation does not interfere with a simultaneous search operation allowing both to occur simultaneously.
Referring briefly to
Referring to the top of
As mentioned above, essentially identical refresh operations are performed for data bits stored at storage node S2 of DRAM cell 210-2. In particular, the stored data bit is inverted and passed to bit line BL2, passed by transmission gate G4 to node A2 of refresh circuit 160A, re-inverted by inverter IN3, then passed from node B2 through transmission gate G45 to bit line BL2, and finally passed from bit line BL2 to storage node S2 via transmission gate T6.
As indicated in the examples illustrated in
Further, as set forth above, the refresh operation for CAM cell 110A is entirely performed using only two bit lines (i.e., BL1 and BL2), thereby reducing the substrate space required to fabricate CAM cell 110A when compared with conventional 10T CAM cells requiring four bit lines.
In accordance with one embodiment, write word line WL (see
In addition, discharge line DL is pulled high at the same time that match line ML is precharged high to allow lookup lines L and L-bar to maintain their previously applied signal levels. If discharge line DL were held low as match line were precharged high for example, high voltage signals on discharge line DL and at storage node S1 would establish a path through transistors T4 and T5, thereby causing a significant power dissipation during the match line precharge operation. To prevent this power dissipation, discharge line DL is pulled high during match line precharge, and then pulled low to start the search (lookup) operation only after valid search data exists on the lookup lines. In an alternative embodiment, discharge line DL may be fixed low (e.g., ground), but this would require lookup lines L and L-bar to both be cycled low during each match line precharge operation to prevent high power dissipation through comparator circuit 220. In another alternative embodiment, discharge line DL may be fixed low, and match line ML may be precharged to low level. This allows lookup data line L and L-bar to maintain previously applied value until it is driven to new value.
In accordance with one embodiment, bit line BL1 and BL2 are not discharged to ground completely during read cycle or read phase of refresh cycle. It may take a long time for series transistors T2 and T3 or T7 and T8 to discharge long, high capacitive bit lines B1 and B2. Instead of simple inverters IN1 and IN3, sense amplifiers can be used with reference voltages which are slightly lower than power supply level.
Although the embodiment of
Similar to CAM cell 110A, CAM cell 110B includes a (first) 3T dynamic random access memory (DRAM) cell 510-1 having a first storage node S1 for storing a first data bit, a (second) 3T DRAM cell 510-2 having a second storage node S2 for storing a second data bit, and a 4T comparator circuit 520 for discharging an associated match line ML to discharge line DL when complementary (unmasked) data applied on lookup lines L-bar and L is not equal to complimentary (unmasked) data stored at storage nodes S1 and S2, respectively.
Unlike CAM cell 110A, however, the read and write transistors of DRAM cells 510-1 and 510-2 are cross-coupled between bit lines BL1 and BL2. Referring to the right side of CAM cell 110B, DRAM cell 510-1 includes a write transistor T1 connected between storage node S1 and bit line BL1 via a first write port 511, a pull-down transistor T2 including a gate terminal connected to storage node S1, a first terminal connected to ground, and a second terminal connected to read transistor T3, and a read transistor T3 is connected between the second terminal of pull-down transistor T2 and (the other) bit line BL2 via a first read port 512. Similarly, second DRAM cell 510-2 includes a write transistor T6 connected between bit line BL2 (via a second write port 515) and storage node S2, a pull-down transistor T7 connected between read transistor T8 and ground, and a read transistor T8 connected between pull-down transistor T7 and bit line BL1 (via a second read port 516).
Similar to comparator 220 (
Referring to the lower portion of
During operation, a CAM array containing multiple CAM cells 110B is controlled to perform write, search, and refresh operations on the DRAM-based CAM cells 110B as described below. Write operations and search operations are performed essentially as described above with reference to CAM array 100A (see
Similar to CAM cell 110A, each CAM cell 110B performs simultaneous refresh and search operations using only two bit lines (i.e., bit lines BL1 and BL2) and two data lines L and L-bar. However, as set forth below, CAM array 100B reduces bit line cycling during refresh through the use of cross-coupled inverting refresh circuit 160B and the cross-coupled DRAM cells of CAM cell 110B.
The refresh operation of CAM array 100B is described in additional detail with reference to timing diagrams provided in
Referring to the top of
As in the first embodiment, the examples illustrated in
Moreover, the cross-coupled arrangement of CAM array 100B reduces bit line cycling, thereby reducing power consumption over the embodiment shown in
CAM cell 110B is not limited to use in ternary CAM arrays, such as CAM array 100B (shown in
During operation, binary CAM array 100C performs write, search, and refresh operations on DRAM-based CAM cell 110B as described below. Write operations and search operations are performed essentially as described above with reference to CAM array 100A and 100B (see
When the circuit 100C of
In addition to the CAM array embodiments described above, the cross-coupled 3T DRAM arrangement of the second and third embodiments may also be beneficially utilized in conventional 3T Cell DRAM circuits.
Although the present invention is described with reference to certain specific embodiments, several additional alternative embodiments are also possible. For example, in another embodiment the match line may be charged (instead of discharged) when mismatches occur by reversing the precharges applied to the match and discharge lines. Further, the pull-down transistors may be replaced with pull-up transistors that are connected between a high voltage source (e.g., VCC) and the read/access transistors. In view of these and other possible modifications, the invention is limited only by the following claims.
This application is claims priority of U.S. Provisional Patent Application 60/496,346, entitled “Dram-Based CAM Cell Array With Shared Bit Lines” filed Aug. 18, 2003.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5189640 | Huard | Feb 1993 | A |
| 6353552 | Sample et al. | Mar 2002 | B1 |
| Number | Date | Country | |
|---|---|---|---|
| 20050152199 A1 | Jul 2005 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60496346 | Aug 2003 | US |
