Patent Application
20240251546
The present disclosure relates to semiconductor structures and, more particularly, to a dynamic random-access memory (DRAM) transistor including pillars formed using a low-temperature ion implant process.
As DRAM devices scale to smaller dimensions, an increasing emphasis is placed on patterning for forming three dimensional structures, including trenches for storage nodes as well as access transistors. In current DRAM devices, transistors may be formed using narrow and tall, vertical semiconductor fin structures, often made from monocrystalline silicon. In accordance with current trends, the aspect ratio of such fin structures, meaning the height (depth) of a fin divided by the spacing between adjacent fins, may reach 20:1 or more in the coming years.
In an effort to continue scaling smaller, 4F2 DRAM devices have been developed. However, current 4F2 DRAM devices suffer from high common bitline (BL) resistance and floating-body effect.
It is with respect to these and other drawbacks of the current art that the present disclosure is provided.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.
In one aspect, a method may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants, and annealing the plurality of bridge layers. The method may further include forming a contact by directing second ions into an upper surface of the plurality of bridge layers while the substrate is at the low temperature, and forming a pillar over the contact.
In another aspect, a method of forming a dynamic random-access memory device may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants each performed at a different implant energy. The method may further include annealing the plurality of bridge layers, forming a contact by directing second ions into an upper surface of the plurality of bridge layers while the substrate is at the low temperature, and forming a pillar over the contact.
In yet another aspect, a DRAM transistor may include a plurality of bridge layers formed in a substrate, a contact formed in the plurality of bridge layers, and a pillar formed over the contact, wherein a gate surrounds the pillar.
The accompanying drawings illustrate exemplary approaches of the disclosure, including the practical application of the principles thereof, as follows:
The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict exemplary embodiments of the disclosure, and therefore are not to be considered as limiting in scope. In the drawings, like numbering represents like elements.
Furthermore, certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines otherwise visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
Devices, DRAM transistors, and methods in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, where various embodiments are shown. The devices, DRAM transistors, and methods may be embodied in many different forms and are not to be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so the disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.
To address the deficiencies of the prior art described above, disclosed herein are methods and devices (e.g., 4F2 vertical DRAM transistors) with pillars formed following a low-temperature ion implantation to a substrate (e.g., silicon substrate), which ensures less defects for high quality Epi-Si growth and addresses the floating body issue. Furthermore, low bitline (BL) resistance is possible with heavy doping at low-temperature, which enables a true 4F2 DRAM scheme (i.e., no need additional metal contact in the device.
The plurality of bridge layers 104A-104N may be formed by directing ions into the substrate 102 over a series of successive implants. For example, a first ion implant process (1) may be performed whereby ions (e.g., P+, As+, Sb+) are directed into an upper surface 106 of the substrate 102 at a first energy, such as 7 keV, 3E15 to, form first N+ bridge layer 104A. A second ion implant process (2), which may be performed following the first ion implant process, may include delivering ions at a second energy, such as 21 keV, 3E15, to form bridge layer 104B. A third ion implant process (3) may be performed following the second ion implant process, e.g., at an energy of 35 keV, 3E15, to form bridge layer 104C. The doping sequence is not critical, however, and may be reversed, for example. Embodiments of the disclosure are not limited to any particular number of implant processes and/or bridge layers. Although non-limiting, the implant angle may be perpendicular, or approximately perpendicular, to a plane defined by the top surface 106 of the substrate 102. The implantation angle may vary in other embodiments.
Each of the first, second, and third implant processes may be performed while the substrate 102 is at a low temperature. Said differently, the ions may be delivered as part of a cryogenic ion implant process, which is performed between 0 and −100 degrees C. In some embodiments, the cryogenic ion implant includes chilling a platen or substrate holder (not shown) upon which the substrate 102 is provided. The low-temperature ion implant enables higher-dose doping, which lowers defect levels and lowers contact and bridge layer resistance. Furthermore, the low-temperature implant provides a thicker pre-amorphizing implant (PAI), which leads to less end-of-range (EOR) defects.
Following the ion implants, the device 100 is annealed 110, as shown in
As shown in
With the upper surface 106 of the substrate 102 exposed, another low-temperature implantation process 128 may be performed to form a contact 130 in the plurality of bridge layers 104A-104N. More specifically, the contact 130 may be formed in bridge layer 104A by delivering ions (e.g., P+, As+, Sb+) into the upper surface 106 at a temperature between approximately 0 and −100° C. Although non-limiting, the ions may be delivered at an implant energy of approximately 7 keV, 5E15. In this case, no annealing step is performed following the low-temperature implantation process 128. Instead, a pillar 140 is then epitaxially grown within the opening 118, as demonstrated in
The processing apparatus 200 may also include a series of beam-line components. Examples of beam-line components may include extraction electrodes 203, a magnetic mass analyzer 211, a plurality of lenses 213, and a beam parallelizer 217. The processing apparatus 200 may also include a platen 219 for supporting a substrate 202 to be processed. The substrate 202 may be the same as the substrate 102 described above. The substrate 202 may be moved in one or more dimensions (e.g., translate, rotate, tilt, etc.) by a platform component sometimes referred to as a “roplat” (not shown). It is also contemplated that the platen 219 may be configured to perform the heated implantation processes described herein to modify one or more waveguide surfaces.
In operation, ions of the desired species, for example, dopant ions, are generated and extracted from the ion source 201. Thereafter, the extracted ions 235 travel in a beam-like state along the beam-line components and may be implanted in the substrate 202. Similar to a series of optical lenses that manipulate a light beam, the beam-line components manipulate the extracted ions 235 along the ion beam. In such a manner, the extracted ions 235 are manipulated by the beam-line components while the extracted ions 235 are directed toward the substrate 202. It is contemplated that the apparatus 200 may provide for improved mass selection to implant desired ions while reducing the probability of undesirable ions (impurities) being implanted in the substrate 202.
In some embodiments, the processing apparatus 200 can be controlled by a processor-based system controller such as controller 230. For example, the controller 230 may be configured to control beam-line components and processing parameters associated with beam-line ion implantation processes. The controller 230 may include a programmable central processing unit (CPU) 232 that is operable with a memory 234 and a mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input/output (I/O) circuits, and the like, coupled to the various components of the processing apparatus 200 to facilitate control of the substrate processing. The controller 230 also includes hardware for monitoring substrate processing through sensors in the processing apparatus 200, including sensors monitoring the substrate position and sensors configured to receive feedback from and control a heating apparatus coupled to the processing apparatus 200. Other sensors that measure system parameters such as substrate temperature and the like, may also provide information to the controller 230.
To facilitate control of the processing apparatus 200 described above, the CPU 232 may be one of any form of general-purpose computer processor that can be used in an industrial setting, such as a programmable logic controller (PLC), for controlling various chambers and sub-processors. The memory 234 is coupled to the CPU 232 and the memory 234 is non-transitory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. Support circuits 236 may be coupled to the CPU 232 for supporting the processor in a conventional manner. Implantation and other processes are generally stored in the memory 234, typically as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 232.
The memory 234 is in the form of computer-readable storage media that contains instructions, that when executed by the CPU 232, facilitates the operation of the apparatus 200. The instructions in the memory 234 are in the form of a program product such as a program that implements the method of the present disclosure. The program code may conform to any one of a number of different programming languages. In one example, the disclosure may be implemented as a program product stored on computer-readable storage media for use with a computer system. The program(s) of the program product define functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.
It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations. For ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and/or regions not explicitly shown are omitted from the actual semiconductor structures.
For the sake of convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” and “longitudinal” will be understood as describing the relative placement and orientation of components and their constituent parts as appearing in the figures. The terminology will include the words specifically mentioned, derivatives thereof, and words of similar import.
As used herein, an element or operation recited in the singular and proceeded with the word “a” or “an” is to be understood as including plural elements or operations, until such exclusion is explicitly recited. Furthermore, references to “one embodiment” of the present disclosure are not intended as limiting. Additional embodiments may also incorporating the recited features.
Furthermore, the terms “substantial” or “substantially,” as well as the terms “approximate” or “approximately,” can be used interchangeably in some embodiments, and can be described using any relative measures acceptable by one of ordinary skill in the art. For example, these terms can serve as a comparison to a reference parameter, to indicate a deviation capable of providing the intended function. Although non-limiting, the deviation from the reference parameter can be, for example, in an amount of less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.
Still furthermore, one of ordinary skill will understand when an element such as a layer, region, or substrate is referred to as being formed on, deposited on, or disposed “on,” “over” or “atop” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on,” “directly over” or “directly atop” another element, no intervening elements are present.
As used herein, “depositing” and/or “deposited” may include any now known or later developed techniques appropriate for the material to be deposited including yet not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), and plasma-enhanced CVD (PECVD). Additional techniques may include semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), and sputtering deposition. Additional techniques may include ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
While certain embodiments of the disclosure have been described herein, the disclosure is not limited thereto, as the disclosure is as broad in scope as the art will allow and the specification may be read likewise. Therefore, the above description is not to be construed as limiting. Instead, the above description is merely as exemplifications of particular embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto.
