Patent Application
20240292691
The present disclosure relates to the field of display technology, and specifically to a drive backplane, a display panel, and a display apparatus.
Organic Light-Emitting Diode (OLED) display panels have advantages such as self-illumination, wide color gamut, high contrast, flexibility, high response, etc., and have broad application prospects. However, existing display panels may experience abnormal display images such as black screen and flickering.
It should be noted that the information disclosed in the background section is only used to enhance understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.
The present disclosure provides a drive backplane, a display panel, and a display apparatus.
According to an aspect of the present disclosure, a drive backplane is provided. The drive backplane has a pixel area and a control area outside the pixel area. The control area includes a circuit area and a bus area separated between the circuit area and the pixel area. The circuit layer includes:
In an exemplary embodiment of the present disclosure, the gate connection line includes a first connection part and a second connection part connected to each other. The first connection part is connected to the gate shift register unit and passes through the bus area. The second connection part is spaced apart from the bus line and the pixel circuit, and is connected to at least one of the gate lines. At least one of the first connection part and the second connection part is located on a different layer from the gate line.
In an exemplary embodiment of the present disclosure, the first connection part and the gate line are arranged on the same layer, and the second connection part and the gate line are arranged on different layers.
In an exemplary embodiment of the present disclosure, the first connection part and the second connection part are provided on the same layer, but on a different layer from the gate line and the bus line.
In an exemplary embodiment of the present disclosure, the circuit layer further includes a power line, a data line, and a reset signal line. Both of the power line and the data line extend along the column direction, and are arranged along the row direction. The power line and the data line are arranged on the same layer as the bus line. The reset signal line extends along the row direction, and is arranged along the column direction. The reset signal line is located on a different layer from the gate line and the bus line.
The gate line includes a first gate line and a second gate line.
The pixel circuit includes a storage capacitor and a plurality of transistors. The transistor includes a drive transistor, a write transistor, a compensation transistor, and a first reset transistor. Gates of the compensation transistor and the write transistor are connected to the first gate line. The drive transistor has a first terminal connected to the power line, and a second terminal connected to the light-emitting device. The compensation transistor is connected to the second terminal and the gate of the drive transistor. The write transistor has a first terminal connected to the data line, and a second terminal connected to the first terminal of the drive transistor. The first reset transistor has a gate connected to the second gate line, a first terminal connected to the reset signal line, and a second terminal connected to the gate of the drive transistor. The storage capacitor has a first plate connected to the gate of the drive transistor, and a second plate connected to the power line.
The first gate line connecting the pixel circuit in the n-th row and the second gate line connecting the pixel circuit in the (n+1)-th row are connected to the same gate shift register unit through the same gate connection line.
In an exemplary embodiment of the present disclosure, the circuit layer includes:
In an exemplary embodiment of the present disclosure, the first connection part is arranged on the same layer as the gate line, but on a different layer from the second connection part.
The first connection part is connected to the second gate line. The second connection part is located on the source and drain layer, and extends along the column direction. The second connection part is connected to the first gate line through a contact hole.
In an exemplary embodiment of the present disclosure, the first connection part and the second connection part are arranged on the same layer.
The gate connection line is located on the second gate layer.
In an exemplary embodiment of the present disclosure, the first connection part is connected to the gate shift register unit and the second gate line through contact holes. The second connection part extends along the column direction, and is connected to the first connection part. The second connection part is connected to the first gate line through a contact hole.
In an exemplary embodiment of the present disclosure, the gate line further includes a third gate line. The pixel circuit further includes a second reset transistor, a first light emission control transistor, and a second light emission control transistor.
The first light emission control transistor has a gate connected to the third gate line, a first terminal connected to the power line, and a second terminal connected to the first terminal of the drive transistor.
The second light emission control transistor has a gate connected to the third gate line, a first terminal connected to the second terminal of the drive transistor, and a second terminal connected to the light-emitting device.
The second reset transistor has a gate connected to the first gate line, a first terminal connected to the reset signal line, and a second terminal connected to the second terminal of the second light emission control transistor.
In an exemplary embodiment of the present disclosure, the circuit layer further includes:
In an exemplary embodiment of the present disclosure, the light emission connection line is located on the second gate layer, and is connected to the light emission shift register unit and the third gate line through contact holes.
In an exemplary embodiment of the present disclosure, the light emission connection line includes a third connection part and a fourth connection part. The third connection part is provided in the same layer as the gate line, and is connected to the light emission shift register unit. The third connection part passes through the bus area along the direction. The fourth connection part is located on the source and drain layer or the second gate layer, and is connected to the third connection part and the third gate line through contact holes.
In an exemplary implementation of the present disclosure, the second reset transistor of the pixel circuit in the n-th row is connected to the second gate line of the pixel circuit in the (n+1)-th row.
In an exemplary embodiment of the present disclosure, the bus line includes a test bus line, a reset bus line, and a power bus line located one the source and drain layer. The power line is connected to the power bus line, and the reset signal line is connected to the reset bus line.
In an exemplary embodiment of the present disclosure, the reset bus line is located between the test bus line and the pixel area. The second connection part is located on a side of the reset bus line away from the test bus line, and is arranged adjacent to the reset bus line. The distance between the second connection part and the reset bus line along the row direction is 3 μm-10 μm.
In an exemplary embodiment of the present disclosure, the width of the second connection part is 20%-40% of the width of the reset bus line.
In an exemplary embodiment of the present disclosure, the control area of the drive backplane includes a lead-out area, which extends along the row direction and is spaced apart from the pixel area along the column direction. The bus line, the data line, and the power line are connected to the lead-out area.
The bus area includes side bus areas arranged on both sides of the pixel area along the row direction and a connection bus area connected between the two side bus areas. The connection bus area is located between the lead-out area and the pixel area.
The power bus line is located in the connection bus area.
According to an aspect of the present disclosure, a display panel is provided, including the drive backplane described in any one of the above embodiments.
According to an aspect of the present disclosure, a display apparatus is provided, including the display panel according to any one of the above embodiments.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the present disclosure. It is noted that the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
The terms “a”, “an”, “the”, “said”, and “at least one” are used to indicate the presence of one or more elements or components/etc. The terms “include” and “have” are used to indicate a non-exclusive inclusion, and mean that there may be additional elements or components, etc. in addition to those listed. The terms “first”, “second”, “third” etc. are only used as markers, not a limit on the number of the relavant objects.
The row direction X and the column direction Y in the description are only two mutually perpendicular directions. In the drawings of the present disclosure, the row direction may be tranverse and the column direction may be vertical, but the present disclosure is not limited in this regard. If the display panel is rotated, the actual orientations of row direction X and column direction Y may change.
The “overlapping” characteristic between feature A and feature B in the description means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap. The “non-overlapping” characteristic between feature A and feature B in the description means that the overlapping area between the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate is zero.
Feature A and feature B being on the “same layer” in the description means that feature A and feature B may be formed at the same time. Feature A and feature B being on “different layers” means that feature A and feature B are spaced apart in a direction perpendicular to the substrate, and they are separated by another film layer.
As shown in
The light-emitting device LD may be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a Micro LED, or a Mini LED, etc., and may include a first electrode ANO, a second electrode CAT, and a light-emitting layer EL located between the first electrode ANO and the second electrode CAT.
The display panel may be divided into at least a display area the can emit light and a peripheral area outside the display area that cannot emit light. The drive circuit may include a pixel circuit located in the display area and a peripheral circuit located in the peripheral area. On the one hand, the peripheral circuit may be connected to the light-emitting device LD through the pixel circuit, and apply the first power signal VDD to the first electrode ANO of the light-emitting device LD. On the other hand, the peripheral circuit may also be connected to the second electrode CAT of the light-emitting device LD, and apply the second power signal VSS to the second electrode CAT. Thus, the current through the light-emitting device LD may be controlled by controlling the pixel circuit, thereby controlling the brightness of the light-emitting device LD.
As shown in
As shown in
There may be multiple pixel circuits PC, and they are arranged in an array in the pixel area AA, thereby obtaining multiple rows and multiple columns of pixel circuits PC. One pixel circuit PC may be connected to at least one light-emitting device to drive the light-emitting device to emit light.
There may be multiple gate lines GAL, and at least some of them are located in the pixel area AA. Each gate line GAL extends along the row direction X, and is arranged along the column direction Y. The pixel circuits PC in one row are connected to at least one gate line GAL.
The gate drive circuit GGOA may be disposed in the control area WA, and includes a plurality of gate shift register units GGOAs cascaded along the column direction Y. There are multiple gate connection lines GCL. One gate shift register unit GGOA may be connected to one gate connection line GCL, so that signals can be input to the pixel circuit PC through the gate connection line GCL and the gate line GAL. At the same time, at least part of a gate connection line GCL is in a different layer from the gate line GAL, and is connected to at least one gate line GAL through a contact hole.
The bus lines L are provided in the bus area LA, and at least some of them are located between the gate drive circuit GGOA and the pixel area AA. The bus line L is insulated from the gate connection line GCL.
In the drive backplane BP in an embodiment of the present disclosure, at least some of the gate connection lines GCL connecting the gate line GAL and the gate shift register unit GGOA may be located on a different layer from the gate line GAL, and thus the connection needs to be realized through a contact hole. The existence of the contact hole helps to increase the overall impedance of the gate connection line GCL, improve the ability to block static electricity, play a certain protective role for other circuits, ensure the stable transmission of electrical signals, and avoid abnormal display phenomena such as black screens and flickers. Especially for the gate line GAL that transmits high-frequency pulse signals, this helps to reduce the interference of static electricity on the signal.
The following is a detailed description of the pixel circuit PC and drive circuit.
The pixel circuit PC may include multiple transistors and may also include capacitors. For example, it may be 3T1C, 7T1C, and another pixel circuit PC. nTmC indicates that a pixel circuit PC includes n transistors (indicated by the letter “T”) and m capacitors (indicated by the letter “C”).
As shown in
The first reset transistor T1 has a gate used to receive the first reset control signal RE1, a first terminal used to receive the reset signal VI, and a second terminal connected to the gate of the drive transistor T3. The first plate of the storage capacitor Cst is connected at the N1 node, and the second plate of the storage capacitor Cst is used to receive the first power signal VDD. The compensation transistor T2 has a gate used to receive the scan signal GA, a first terminal connected to the N2 node along with the second terminal of the drive transistor T3, and a second terminal connected to the N1 node along with the gate of the drive transistor T3. The write transistor T4 has a gate used to receive the scan signal GA, a first terminal used to receive the data signal DA, and a second terminal connected to the N3 node along with the first terminal of the drive transistor T3. The first light emission control transistor T5 has a gate used to receive the light emission control signal EM, a first terminal used to receive the first power signal VDD, and a second terminal connected to the first terminal of the drive transistor T3. The second light emission control transistor T6 has a gate used to receive the light emission control signal EM, a first terminal connected to the N2 node along with the second terminal of the drive transistor T3, and a second terminal connected to the N4 node along with the first terminal of the light-emitting device. The second reset transistor T7 has a gate used to receive the reset control signal REL, a first terminal used to receive the reset signal VI, and a second terminal connected to the N4 node along with the second terminal of the second light emission control transistor T6.
The following explains the operation principle of the pixel circuit PC.
Each transistor of the pixel circuit PC may be a P-type low-temperature polysilicon transistor. Because the P-type low-temperature polysilicon transistors have high carrier mobility, they are conducive to achieving a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The P-type low-temperature polysilicon transistor may be turned off when a high-level signal is input to its gate, and turned on when a low-level signal is input thereto. It is noted that the transistor may also be an N-type low-temperature polysilicon transistor, which is turned on at a high-level signal. The present description only takes the P-type low-temperature polysilicon transistor as an example.
During the reset phase, the first reset control signal RE1 is a low-level signal, the first reset transistor T1 is turned on, and the reset signal VI is written to the gate of the drive transistor T3 and the first plate of the storage capacitor Cst. As a result, the N1 node is reset to implement initialization, thereby eliminating the influence of the data of the previous image frame.
During the write stage, the scan signal GA can turn on the write transistor T4 and the compensation transistor T2, and the data signal DA is written to the gate of the drive transistor T3 and the first plate Cst1 of the storage capacitor Cst. That is, through the N3 node and the N2 node, the data signal DA is written to the N1 node, until the potential reaches Vdata+vth. Vdata is the voltage of the data signal Da, and Vth is the threshold voltage of the drive transistor T3. The scan signal GA of the write transistor T4 and the compensation transistor T2 may be the same signal. At the same time, the second reset control signal RE2 is a low-level signal, causing the second reset transistor T7 to be turned on. The second reset signal VIN2 is written to the first electrode of the light-emitting device LD and the second terminal of the second light emission control transistor T6. Thus, the N4 node is reset to implement initialization, and further eliminate the influence of the data of the previous image frame.
During the light-emitting phase, the light emission control signal EM is a low-level signal, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the drive transistor T3 is turned on under the effect of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power signal VDD. At this time, the light-emitting device LD emits light.
Further, as shown in
The power lines VDL may extend along the column direction Y and be arranged along the row direction X. The power lines VDL may be connected to the first light emission control transistor T5 and the second plate Cst2 of the storage capacitor Cst for transmitting the first power signal VDD. The data lines DAL may also extend along the column direction Y and be arranged along the row direction X. The data lines DAL may be connected to the first terminal of the write transistor T4 for transmitting the data signal DA.
The first reset signal line VIL1 and the second reset signal line VIL2 both extend along the row direction X and are arranged along the column direction Y. The first reset signal line VIL1 may be connected to the first terminal of the first reset transistor T1 for transmitting the reset signal VI. The second reset signal line VIL2 may be connected to the first terminal of the second reset transistor T7 for transmitting the reset signal VI. The two reset signals VI may be the same or different.
In order to simplify the structure, in some embodiments, the same reset signal line may be used to simultaneously input the reset signal to the second reset transistor T7 of the pixel circuit PC in the n-th row and the first reset transistor T1 of the pixel circuit PC in the (n+1)-th row. That is to say, the second reset signal line VIL2 connected to the pixel circuit PC in the n-th row may be multiplexed as the first reset signal line VIL1 connected to the pixel circuit PC in the (n+1)-th row. To this end, the first terminal of the second reset transistor T7 of the pixel circuit PC in the n-th row may be connected to the first terminal of the first reset transistor T1 of the pixel circuit PC in the (n+1)-th row, and is further connected to the same reset signal line (the first reset signal line VIL1 and the second reset signal line VIL2). In this way, the number of reset signal lines can be reduced.
There may be multiple gate lines GAL, and they all extend along the row direction X and are arranged along the column direction Y. The gate line GAL may be used to transmit the scan signal GA, the first reset control signal RE1, the second reset control signal RE2, and the light emission control signal EM, thereby controlling the on or off state of other transistors except the drive transistor T3. For example, the gate line GAL may include a first gate line GAL1, a second gate line GAL2, a third gate line GAL3, and a fourth gate line GAL4.
The first gate line GAL1 may be connected to the gates of the write transistor T4 and the compensation transistor T2 at the same time, and simultaneously transmit the scan signal GA to the write transistor T4 and the compensation transistor T2. The second gate line GAL2 may be connected to the gate of the first reset transistor T1 for transmitting the first reset control signal RE1. The third gate line GAL3 may be connected to the gates of the first light emission control transistor T5 and the second light emission control transistor T6 at the same time for transmitting the light emission control signal EM. The fourth gate line GAL4 may be connected to the gate of the second reset transistor T7 for transmitting the second reset control signal RE2.
Since the write transistor T4, the compensation transistor T2, and the second reset transistor T2 are all turned on during the light-emitting phase, the first gate line GAL1 and the fourth gate line GAL4 connected to the same pixel circuit PC can receive a signal at the same time, and the signal may serve as the scan signal GA and the second reset control signal RE2 simultaneously. At the same time, the first gate line GAL1 connected to the pixel circuit PC in the n-row may be connected with the second gate line GAL2 connected to the first reset transistor T1 of the pixel circuit PC in the (n+1)-row. Thus, while the pixel circuit PC in the n-th row is in the write stage, the pixel circuit PC in the (n+1)-th row may be in the reset stage.
In view of above, the fourth gate line GAL4 connected to the second reset transistor T7 of the pixel circuit PC in the n-th row, and the second gate line GAL2 connected to the first reset transistor T7 of the pixel circuit PC in the (n+1)-th row may be the same gate line GAL. That is to say, the fourth gate line GAL4 connected to the pixel circuit PC in the n-th row is multiplexed as the second gate line GAL2 of the pixel circuit PC in the (n+1)-th row, which is beneficial to simplifying the structure and shortening the refresh time.
Based on the above pixel circuit PC, in some embodiments, as shown in
As shown in
The first gate insulation layer GI1 may cover the semiconductor layer SEL, and the material thereof may be insulation materials such as silicon nitride and silicon oxide.
As shown in
The second gate insulation layer GI2 may cover the first gate layer GAT1, and the material thereof may be silicon nitride, silicon oxide, or other insulation materials. The material of the second gate insulation layer GI2 may be the same as that of the first gate insulation layer GI1.
As shown in
If the second reset signal line VIL2 connected to the pixel circuit PC in the n-th row is multiplexed as the first reset signal line VIL1 connected to the pixel circuit PC in the (n+1)-th row, then the semiconductor layer SEL between the channel of the second reset transistor T7 of the pixel circuit PC in the n-th row and the channel of the first reset transistor T1 of the pixel circuit PC in the (n+1)-th row may be connected to the first reset signal line VIL1.
In some embodiments of the present disclosure, the compensation transistor T2 may be a dual-gate transistor with two channels. The second gate layer GAT2 may also include a shielding part SL, which may be provided between the first reset signal line VIL1 and the second plate Cst2, and overlap with the area between the two channels of the compensation transistor T2, reducing the the electrical leakage of the compensation transistor T2.
The dielectric layer ILD may cover the second gate layer GAT2, and the dielectric layer ILD may also be made of insulation materials such as silicon nitride and silicon oxide.
As shown in
As shown in
The number of the gate drive circuit GGOA may be one, and it is located on one side of the pixel area AA. The gate shift register unit GGOA may drive at least one row of pixel circuits PC. Alternatively, the number of the gate drive circuits GGOAs may be two, and they are located on both sides of the pixel area AA. The gate shift register units GGOAs of the two gate drive circuits GOA may be set in one-to-one correspondence. The pixel circuits PC in the same row may simultaneously receive signals provided by the corresponding gate shift register units GGOAs on both sides.
As shown in
The gate shift register units GGOAs are cascaded. The first terminal of the input transistor T21 in the first-stage gate shift register unit GGOA is connected to the input terminal IN. The input terminal IN is used to connect to the trigger signal line GSTV for receiving the trigger signal STV as an input signal. The first terminal of the input transistor T1 in the gate shift register unit GGOA of other stages is electrically connected to the output terminal of the gate shift register unit GGOA in the previous stage, so as to receive the output signal output by the output terminal GOUT of the gate shift register unit GGOA in the previous stage as an input signal, thereby realizing the shift output for scanning the pixel circuits PC in the display area row by row.
As shown in
The gate of the first control transistor T2 is connected to the first node N1. The second terminal of the first control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal. The first terminal of the first control transistor T2 and the second node N2 are connected to the gate of the second control transistor T3 and the first clock signal terminal CK to receive the first clock signal. The second terminal of the second control transistor is connected to the second drive power line VGL to receive the second voltage. The first terminal of the second control transistor T3 is connected to the second node N2.
The gate of the output control transistor T4 is connected to the second node N2. The first terminal of the output control transistor T4 is connected to the first drive power line VGH to receive the first voltage. The second terminal of the output control transistor T4 is connected to the output terminal GOUT.
The first terminal of the first capacitor is connected to the second node N2. The second terminal of the first capacitor C1 is connected to the first drive power line VGH.
The gate of the output transistor T5 is connected to the third node N3. The first terminal of the output transistor T5 is connected to the second clock signal terminal CB. The second terminal of the output transistor T5 is connected to the output terminal GOUT.
The first terminal of the second capacitor C2 is connected to the third node N3. The second terminal of the second capacitor C2 is connected to the output terminal GOUT.
The gate of the first noise reduction transistor T6 is connected to the second node N2. The first terminal of the first noise reduction transistor T6 is connected to the first drive power line VGH to receive the first voltage. The second terminal of the first noise reduction transistor T6 is connected to the second terminal of the second noise reduction transistor T7.
The gate of the second noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second sub-clock signal line GCB) to receive the second clock signal. The first terminal of the second noise reduction transistor T7 is connected to the first node N1.
The gate of the voltage stabilizing transistor T8 is connected to the second drive power line VGL to receive the second voltage. The second terminal of the voltage stabilizing transistor T8 is connected to the first node N1. The first terminal of the voltage stabilizing transistor T8 is connected to the third node N3.
The transistors in the gate shift register unit GGOAs in
For the operation principle of the gate-scanning gate shift register unit, references may be made to the introduction in the art, and will not be described in detail here.
It should be noted that markings (T1-T8) for the transistor and the capacitor in the circuit of the gate shift register unit GGOA are the same as the markings (T1-T4) for the transistor in the pixel circuit PC above. But, the same marking is merely used for different circuits, and the same marking on a transistor does not indicate the same transistor.
For the above-mentioned gate drive circuit GGOA, the channel of each transistor may be located on the semiconductor layer SEL, the gate of each transistor and one plate of the capacitor may be located on the first gate layer GAT1, and the other plate of the capacitor may be located on the second gate layer GAT2. The first drive power line VGH, the second drive power line VGL, the trigger signal line GSTV, the first sub-clock signal line GCK, and the second sub-clock signal line GCB are located on the source and drain layer SD. The first drive power line VGH, the second drive power line VGL, the trigger signal line GSTV, the first sub-clock signal line GCK, and the second sub-clock signal line GCB are all located on the side of the gate drive circuit GGOA away from the display area.
As shown in
The space occupied by the power bus line LVD may be reduced by shortening the length thereof, so that the range of the peripheral area can be narrowed. The following is an example.
In some embodiments of the present disclosure, as shown in
Further, as shown in
In other embodiments of the present disclosure, as shown in
As shown in
For example, based on the multiplexing of the gate line GAL in the above embodiment of the pixel circuit PC, the first gate line GAL1 connected to the pixel circuit PC in the n-row and the second gate line GAL2 connected to the first reset transistor T1 of the pixel circuit PC in the (n+1)-row may be connected to the same gate shift register unit GGOA through the same gate connection line GCL. This kind of connection allows the first gate line GAL1 and the fourth gate line GAL4 connected to the same pixel circuit PC to be connected through the same gate connection line GCL with the same gate shift register unit GGOA. In the following, based on this kind of connection, the specific implementation method of the gate connection line GCL is exemplified.
As shown in
In the first type of implementation of the present disclosure, as shown in
In a first embodiment of the first type, as shown in
The second connection part GCL2 is located on the source and drain layer SD, and extends along the column direction Y. The second connection part GCL2 may be connected to the first connection part GCL1 through the contact hole, and is connected to the first gate line GAL1 through the contact hole. The second connection part GCL2 may be located in the display area, and located between the reset bus line LV1 and the column of pixel circuits PC closest to the bus area LA. That is, the second connection part GCL2 is located on the side of the reset bus line LV1 away from the test bus line.
Furthermore, the first connection part GCL1 passes through the bus area LA along the row direction X, and overlaps with each bus line L. The second connection part GCL2 is arranged adjacent to the reset bus line LV1. That is, there is no other wiring between the reset bus line LV1 and the second connection part GCL2. The distance between the second connection part GCL2 and the reset bus line LV1 along the row direction X may be 3 μm-10 μm. For example, the distance may be 4.5 μm. On the one hand, it helps to prevent the second connection part GCL2 from being too close to the reset bus line LV1 and causing the parasitic capacitance to increase too much, which is beneficial to reducing power consumption. On the other hand, it helps to prevent the distance from being too far and causing the width of the peripheral area to increase too much, which would be not conducive to reducing the frame width.
The width of the second connection part GCL2 is 20%-40% of the width of the reset bus line. For example, the width of the second connection part GCL2 is 3.5 μm, and the width of the reset bus line is 10 μm.
In a second embodiment of the first type, as shown in
In a third embodiment of the first type, as shown in
In the third embodiment of the first type, as shown in
In a fourth embodiment of the first type, as shown in
In a fifth embodiment of the first type, the circuit layer CL may also include a light-shielding layer, which may be disposed on one side of the substrate SU and covered by an insulation layer. The semiconductor layer SEL may be disposed on one side of the insulation layer away from the substrate SU. The light-shielding layer may have a light-shielding part that overlaps with the channel of the driving transistor to block light from irradiating the drive transistor. The second connection part GCL2 may be located on the light-shielding layer.
In other embodiments of the first type, the gate connection line GCL may not be limited to the structures of the first connection part GCL1 and the second connection part GCL2 described above, and may include more line segments. At least some of these line segments are located on the first gate layer GAT1, and the others thereof may be located on at least one of the second gate layer GAT2 and the source and drain layer SD, as long as the connection between the gate shift register unit GGOA and the first gate line GAL1 and the second gate line GAL2 can be realized, without any direct contact with the bus line. Thus, no repeated description is provided herein.
In the second type of implementation of the present disclosure, the gate connection line GCL is located on the same layer. For example, the first connection part GCL1 and the second connection part GCL2 of the gate connection line GCL are provided on the same layer, but are on a different layer from the gate line and the bus line, so that contact holes are needed for them to connect with the gate line.
In a first embodiment of the second type, as shown in
In a second embodiment of the second type, the circuit layer CL may also include a light-shielding layer, which may be disposed on one side of the substrate and covered by an insulation layer. The semiconductor layer SEL may be disposed on a side of the insulation layer away from the substrate SU. The light-shielding layer may have a light-shielding part that overlaps with the channel of the drive transistor to block light from irradiating the drive transistor. The gate connection line GCL may be located on the light-shielding layer, and for its specific structure and connection way, references may be made to the first embodiment of the second type, which will not be described in detail here.
Further, as shown in
For example, in some embodiments, as shown in
In some embodiments, as shown in
In order to realize the connection between the light emission shift register unit EGOA and the third gate line GAL3, the circuit layer CL may also include a plurality of light emission connection lines ECL. One light emission shift register unit EGOA is connected to one light emission connection line ECL. At least par of one light emission connection line ECL is located on a different layer from the third gate line GAL3, and is connected to a third gate line GAL3 through a contact hole.
The inventor(s) has found that although the light-emitting time of the light-emitting device LD is longer than the reset and write time, and as a pulse signal, the frequency of the light emission control signal EM is lower than the frequencies of the scan signal GA and the reset control signals RE1 and RE2, but the light emission control signal EM may still be affected by static electricity. Therefore, contact holes may also be introduced between the light emission shift register unit EGOA and the third gate line GAL3 to increase the impedance, thereby improving the anti-static capability.
Similar to the structure of the above-mentioned gate connection line GCL, at most some of the light emission connection lines ECL are on the same layer as the gate line GAL, and thus a contact hole is required for connecting to the third gate line GAL3. Therefore, the resistance can be increased by introducing a contact hole, thereby improving the ability to block static electricity.
As shown in
In addition, the light emission connection line ECL may be located on the second gate layer GAT2, and connected to the light emission shift register unit EGOA and the third gate line GAL3 through the contact hole.
The structure and the connection way of the light emission connection line ECL may refer to the gate connection line GCL mentioned above, the third connection part ECL1 may refer to the first connection part GCL1, and the fourth connection part ECL2 may refer to GCL2, as long as the resistance can be increased through the contact hole. Detailed examples will not be given here. However, it should be noted that the light emission connection line ECL cannot be in direct contact with the bus line L and the gate connection line GCL to avoid short circuits.
Further, for the second type of implementation described above, the reset signal lines (the second reset signal line VIL2 connected to the pixel circuit PC in the n-th row and the first reset signal line VIL1 connected to the pixel circuit PC in the (n+1)-th row) extend along the row direction X, and are connected to the reset bus line LV1 through the reset connection line RCL. In order to avoid the fourth connection part CGL2 and the second connection part GCL2 from intersecting with the reset connection line RCL, the reset connection line RCL thereof may be located on the first gate layer GAT1, and the reset connection line RCL may be connected with the reset bus line LV1. The reset connection line may be located on the second gate layer GAT2, and is connected to the reset connection line RCL through the contact hole. The reset connection line RCL overlaps with the fourth connection part CGL2 and the second connection part GCL2, but can maintain insulation therefrom.
It is noted that the connection between the reset signal line and the reset bus line LV1 can also be achieved by using the reset connection line RCL of other film layers, as long as the short circuit with the fourth connection part CGL2 and the second connection part GCL2 can be avoided.
As shown in
The drive backplane BP may be the drive backplane BP in any of the above embodiments, and the structure thereof will not be described in detail here.
The light-emitting device LD may be disposed on a side of the circuit layer CL away from the substrate SU, and connected to the pixel circuit PC. There may be multiple light-emitting devices LD, and each light-emitting device LD may be connected to a pixel circuit PC. The same pixel circuit PC may be connected to one or more light-emitting devices LD. The light-emitting device LD may be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a Micro LED, or a Mini LED, etc., and may include a first electrode ANO, a second electrode CAT, and a light-emitting layer located between the first electrode ANO and the second electrode CAT.
Taking OLED as an example, the first electrode ANO may be disposed on the surface of the circuit layer CL away from the substrate SU, for example, on the surface of the second planarization layer PLN2 away from the substrate SU. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the drive backplane BP. Each light-emitting device LD may share the second electrode CAT. That is to say, the second electrode CAT may be a continuous whole-layer structure. The second electrode CAT may extend to the peripheral area, and may receive the second power signal VSS. The first electrodes ANOs are arranged in an array to ensure that each light-emitting device LD can emit light independently. In addition, in order to limit the light-emitting range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL may be provided on the surface where the first electrode ANO is provided, and the pixel definition layer PDL may have openings exposing various first electrodes ANO. The light-emitting layer EL is stacked with the first electrode ANO in the opening.
Each light-emitting device LD may at least share the light-emitting material layer, so that the light emission color of each light-emitting device LD is the same. At this time, in order to achieve color display, a color film layer may be provided on the side of the light-emitting device LD away from the substrate SU. Through the filter part corresponding to each light-emitting device LD in the color film layer, color display is realized. It is noted that the light-emitting material layer of each light-emitting device LD may also be made independent, so that the light-emitting device LD can directly emit monochromatic light, and the light emission colors of different light-emitting devices LD can be different, thereby achieving color display.
In addition, the display panel may also include an encapsulation layer covering each light-emitting device LD, and may also include other film layers such as a touch layer and a transparent cover plate disposed on a side of the encapsulation layer away from the substrate SU, which will not be described in detail here.
The present disclosure also provides a display apparatus, which may include the display panel described in any of the above embodiments. The display panel is a display panel according to any of the above embodiments. For its specific structure and beneficial effects, reference may be made to the above embodiments of the display panel and will not be described again here. The display apparatus of the present disclosure may be an electronic device with a display function such as a mobile phone, a tablet computer, a television, etc., which will not be listed here.
Other embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the content disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the present disclosure.
The present disclosure is a 35 U.S.C. 371 national phase application of PCT International Application No. PCT/CN2022/096167 filed on May 31, 2022, the entire content of which is incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/096167 | 5/31/2022 | WO |
