Patent Application
20240265858
The present disclosure relates to the field of integrated circuits, and in particular to a drive circuit, a display drive chip, a display apparatus, and an electronic apparatus.
An operational amplifier is a circuit unit with a very high magnification. It is widely used in the field of integrated circuits, so problems that may arise in different application scenarios have to be taken into consideration when designing an operational amplifier. A common problem is that the load capacitance of an operational amplifier is uncertain. For example, when an operational amplifier is used in a drive circuit to drive LED display, many LEDs can be driven, and the number of the LEDs is determined by the user. Therefore, when designing an operational amplifier, it should be considered that the load capacitance of the operational amplifier may be approximately any value. Moreover, in some application scenarios, an operational amplifier may be used as a gain amplifier. The gain amplifier requires that the output has a certain magnification with respect to the input, so another problem is that the transient response of the operational amplifier (a process in which the output changes to a steady state when the input changes) should be smooth, that is, the value of the output voltage has no overshoot, which usually requires a phase margin greater than 60. This is very difficult for Miller-compensated operational amplifiers.
Therefore, it has become a research hotspot in this field to design a Miller-compensated drive circuit that can meet the above requirements.
In view of the foregoing, the present disclosure provides a drive circuit, a display drive chip, a display apparatus, and an electronic apparatus. The drive circuit, as a Miller-compensated drive circuit, can meet the needs of connecting to an arbitrary load capacitance and having a smooth transient response.
According to one aspect of the present disclosure, a drive circuit is provided, including a first stage circuit, a second stage circuit, and an auxiliary circuit, where the first stage circuit is configured to receive a first input signal and a second input signal and amplify the first input signal and the second input signal to acquire a first output signal and a second output signal and output the first output signal and the second output signal to the second stage circuit, the second stage circuit is configured to output a third output signal based on the first output signal and the second output signal to drive a load, and the second stage circuit is connected to the first stage circuit via a Miller capacitor, and the auxiliary circuit is connected to the first stage circuit and the second stage circuit for reducing an output impedance of the first stage circuit.
In one possible implementation, the auxiliary circuit includes a first resistor and a second resistor, the first output signal is output by a first end of the first stage circuit, and the second output signal is output by a second end of the first stage circuit, the first resistor is connected between a power supply voltage and the first end of the first stage circuit, and the second resistor is connected between the second end of the first stage circuit and a ground.
In one possible implementation, the auxiliary circuit further includes a first transistor and a second transistor, the first transistor and the first resistor are connected in series between the power supply voltage and the first end of the first stage circuit, a current flowing through the first resistor also flows through a first electrode and a second electrode of the first transistor, a gate of the first transistor is connected to a farther one of the first and second electrodes of the first transistor from the power supply voltage, and the first transistor is configured to reduce the current flowing through the first resistor, and the second transistor and the second resistor are connected in series between the second end of the first stage circuit and the ground, a current flowing through the second resistor also flows through a first electrode and a second electrode of the second transistor, a gate of the second transistor is connected to a farther one of the first and second electrodes of the second transistor from the ground, and the second transistor is configured to reduce the current flowing through the second resistor.
In one possible implementation, the auxiliary circuit further includes a third transistor and a fourth transistor, the third transistor, the first transistor, and the first resistor are connected in series between the power supply voltage and the first end of the first stage circuit, the current flowing through the first resistor also flows through a first electrode and a second electrode of the third transistor, a gate of the third transistor receives a first bias signal, and the third transistor is configured to control a maximum value of the current flowing through the first resistor to be smaller than a current value of a tail current of the first stage circuit, and the fourth transistor, the second transistor, and the second resistor are connected in series between the second end of the first stage circuit and the ground, the current flowing through the second resistor also flows through a first electrode and a second electrode of the fourth transistor, a gate of the fourth transistor receives a second bias signal, and the fourth transistor is configured to control a maximum value of the current flowing through the second resistor to be smaller than the current value of the tail current of the first stage circuit.
In one possible implementation, when the first bias signal causes the third transistor to operate in a linear region, the first output signal decreases and the current flowing through the first resistor increases; when the first output signal decreases such that the third transistor operates in a saturation region, the current flowing through the first resistor reaches the maximum value; when the second bias signal causes the fourth transistor to operate in the linear region, the second output signal increases and the current flowing through the second resistor increases; and when the second output signal increases such that the fourth transistor operates in the saturation region, the current flowing through the second resistor reaches the maximum value.
In one possible implementation, the second stage circuit includes a fifth transistor and a sixth transistor, where a first electrode of the fifth transistor is connected to the power supply voltage, a second electrode of the fifth transistor serves as a first end of the second stage circuit to output the third output signal, and a gate of the fifth transistor serves as a second end of the second stage circuit to receive the first output signal, and a first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected to the ground, and a gate of the sixth transistor serves as a third end of the second stage circuit to receive the second output signal, where the fifth transistor and the sixth transistor have different polarities, the fifth transistor and the first transistor have same polarity, and the sixth transistor and the second transistor have same polarity.
According to another aspect of the present disclosure, a display drive chip is provided, including a plurality of display units and at least one drive circuit as described above, where the plurality of display units are connected to the third end of the second stage circuit of the drive circuit.
According to another aspect of the present disclosure, a display apparatus is provided, including the above display drive chip.
In one possible implementation, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small pitch display panel.
According to another aspect of the present disclosure, an electronic apparatus is provided, including the above display apparatus.
In a drive circuit according to an embodiment of the present disclosure, the first stage circuit receives and amplify a first input signal and a second input signal to acquire a first output signal and a second output signal and output the first output signal and the second output signal to a second stage circuit, thereby realizing the amplification function and providing a bias for the second stage circuit; the second stage circuit outputs a third output signal based on the first output signal and the second output signal, thereby driving a load; and the second stage circuit is further configured to be connected to the first stage circuit via a Miller capacitor. Therefore, the drive circuit according to the embodiment of the present disclosure is a Miller-compensated drive circuit. An auxiliary circuit is connected to the first stage circuit and the second stage circuit so as to reduce an output impedance of the first stage circuit, such that a minimum value of a phase margin of the drive circuit increases during variation of the load capacitance and a smooth transient response is achieved, that is, the Miller-compensated drive circuit can meet the needs of connecting to an arbitrary load capacitance and having a smooth transient response.
Other features and aspects of the present disclosure will become evident from the detailed description of exemplary embodiments below with reference to the drawings.
The drawings included in and forming part of the description, together with the description, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.
Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the drawings. The same reference signs in the drawings are used to designate elements that are functionally identical or similar. Although various aspects of the embodiments are shown in the drawings, unless otherwise specified, the drawings are not necessarily drawn to scale.
The word “exemplary” used here means “serving as an example, embodiment or illustration”. Any embodiment described here as “exemplary” is not necessarily to be interpreted as superior to or better than other embodiments.
In addition, to better explain the present disclosure, numerous details are given in the following embodiments. It is appreciated by those skilled in the art that the present disclosure can still be implemented without some specific details. In some embodiments, methods, means, elements and circuits well known to those skilled in the art are not described in detail in order to highlight the gist of the present disclosure.
As shown in
When designing an operational amplifier, the specific value of the load capacitance CL in the practical application of the operational amplifier cannot be determined in advance. Therefore, the design of the operational amplifier should consider the fact that the load capacitance may be approximately any value. In some scenarios, the operational amplifier is used as a gain amplifier, so the design of the operational amplifier also needs to take smooth transient response into consideration, i.e., the output signal has no overshoot (which usually requires a phase margin greater than 60°). This is very difficult for operational amplifiers compensated by Miller capacitors in the prior art.
In order to solve the above technical problem, the present disclosure provides a drive circuit, a display drive chip, a display apparatus, and an electronic apparatus. The drive circuit, as a Miller-compensated drive circuit, can satisfy the needs of connecting to an arbitrary load capacitance and having a smooth transient response.
As shown in
The first stage circuit 210 is configured to receive a first input signal Vin1 and a second input signal Vin2 and amplify the first input signal Vin1 and the second input signal Vin2 to acquire a first output signal Vout1 and a second output signal Vout2 and output the first output signal Vout1 and the second output signal Vout2 to the second stage circuit 220.
The first stage circuit 210 according to the embodiment of the present application may be a voltage gain amplification circuit implemented based on the prior art.
It should be appreciated by those skilled in the art that the structure shown in
The second stage circuit 220 is configured to output a third output signal Vout3 based on the first output signal Vout1 and the second output signal Vout2 to drive the load CL. The second stage Circuit 220 is further connected to the first stage circuit 210 via Miller Capacitors C1 and C2.
The second stage circuit 220 may be implemented based on the prior art.
The auxiliary circuit 230 (including 230a and 230b) is connected to the first stage circuit 210 and the second stage circuit 220 to reduce the output impedance of the first stage circuit 210.
The output impedance of the first stage circuit 210 is associated with the phase margin of the drive circuit in such a manner that the smaller the output impedance of the first stage circuit 210, the greater the minimum value of the phase margin of the drive circuit during the variation of the load capacitance CL. When the phase margin is greater than 60%, it can be considered that the transient response of the drive circuit is smooth. Therefore, by reducing the output impedance of the first stage circuit 210 through the auxiliary circuit 230, the transient response of the drive circuit can be optimized.
In a drive circuit according to an embodiment of the present disclosure, the first stage circuit receives and amplify a first input signal and a second input signal to acquire a first output signal and a second output signal and output the first output signal and the second output signal to a second stage circuit, thereby realizing the amplification function and providing a bias for the second stage circuit; the second stage circuit outputs a third output signal based on the first output signal and the second output signal, thereby driving a load; and the second stage circuit is further configured to be connected to the first stage circuit via a Miller capacitor. Therefore, the drive circuit according to the embodiment of the present disclosure is a Miller-compensated drive circuit. An auxiliary circuit is connected to the first stage circuit and the second stage circuit so as to reduce an output impedance of the first stage circuit, such that a minimum value of a phase margin of the drive circuit increases during variation of the load capacitance and a smooth transient response is achieved, that is, the Miller-compensated drive circuit can satisfy the needs of connecting to an arbitrary load capacitance and having a smooth transient response.
The auxiliary circuit 230 in the embodiments of the present disclosure has a variety of structures. Several exemplary structures of the auxiliary circuit 230 and their advantages are described below with reference to
As shown in
By way of example, as is clear from
However, in the circuit shown in
Therefore, the present disclosure provides another design of the auxiliary circuit 230.
As shown in
The first transistor M1 and the first resistor R1 are connected in series between the power supply voltage VDD and the first end a1 of the first stage circuit 210, and the current I1 flowing through the first resistor also flows through a first electrode m11 and a second electrode m12 of the first transistor M1; a gate m13 of the first transistor M1 is connected to one of the first electrode m11 and the second electrode m12 of the first transistor M1 which is far away from the power supply voltage VDD; and the first transistor M1 is configured to reduce the current I1 flowing through the first resistor.
The second transistor M2 and the second resistor R2 are connected in series between the second end a2 of the first stage circuit 210 and the ground, and the current I2 flowing through the second resistor R2 also flows through a first electrode m21 and a second electrode m22 of the second transistor M2; a gate m13 of the second transistor M2 is connected to one of the first electrode m21 and the second electrode m22 of the second transistor M2 which is far from the ground; and the second transistor M2 is configured to reduce the current I2 flowing through the second resistor R2.
In the example shown in
It is appreciated that, in addition to the connection mode shown in
The principle of reducing the current flowing through the first resistor and the current flowing through the second resistor by the auxiliary circuit shown in
In one possible implementation, the second stage circuit includes the fifth transistor T5 and the sixth transistor T6.
The first electrode of the fifth transistor T5 is connected to the power supply voltage VDD, the second electrode of the fifth transistor T5 serves as a first end b1 of the second stage circuit 220 to output the third output signal, and the gate of the fifth transistor T5 serves as a second end b2 of the second stage circuit 220 to receive the first output signal Vout1.
The first electrode of the sixth transistor T6 is connected to the second electrode a2 of the fifth transistor T5, the second electrode of the sixth transistor T6 is connected to the ground, and the gate of the sixth transistor T6 serves as the third end of the second stage circuit to receive the second output signal Vout2.
The fifth transistor T5 and the sixth transistor T6 have different polarities, the fifth transistor T5 and the first transistor M1 have the same polarity, and the sixth transistor T6 and the second transistor M2 have the same polarity.
By way of example, the fifth transistor is the above transistor T5, the sixth transistor is the above transistor T6, the fifth transistor T5 and the sixth transistor T6 are transistors of different polarities, the fifth transistor T5 and the first transistor M1 may be of the same polarity, and the sixth transistor T6 and the second transistor M2 may be of the same polarity. For example, in the embodiment of the present disclosure, the fifth transistor T5 and the first transistor M1 may be P-type transistors, and the sixth transistor T6 and the second transistor M2 may be N-type transistors.
The first transistor M1 may be regarded as a diode when connected in the manner shown in
However, the circuit shown in
Therefore, the present disclosure provides another design of the auxiliary circuit.
As shown in
The third transistor M3, the first transistor M1, and the first resistor R1 are connected in series between the power supply voltage VDD and the first end a1 of the first stage circuit 210, and the current flowing through the first resistor R1 also flows through a first electrode m31 and a second electrode m32 of the third transistor M3; a gate m33 of the third transistor M3 receives a first bias signal VBP; and the third transistor M3 is configured to control the maximum value of the current I1 flowing through the first resistor R1 to be smaller than the current value of the tail current I3 of the first stage circuit 210.
The fourth transistor M4, the second transistor, and the second resistor R2 are connected in series between the second end a2 of the first stage circuit 210 and the ground, and the current I2 flowing through the second resistor R2 also flows through a first electrode m41 and a second electrode m42 of the fourth transistor M4; a gate of the fourth transistor M4 receives a second bias signal VBN; and the fourth transistor M4 is configured to control the maximum value of the current I2 flowing through the second resistor R2 to be smaller than the current value of the tail current I3 of the first stage circuit 210.
In the example shown in
It is appreciated that in addition to the connection mode shown in
An exemplary method in which the third transistor M3 and the fourth transistor M4 control the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 will be described below with reference to
In one possible implementation, when the first bias signal VBP causes the third transistor M3 to operate in the linear region, the first output signal Vout1 decreases and the current I1 flowing through the first resistor R1 increases.
When the first output signal Vout1 decreases such that the third transistor M3 operates in the saturation region, the current I1 flowing through the first resistor R1 reaches a maximum value.
When the second bias signal VBN causes the fourth transistor M4 to operate in the linear region, the second output signal Vout2 increases and the current I2 flowing through the second resistor R2 increases.
When the second output signal Vout2 increases such that the fourth transistor M4 operates in the saturation region, the current I2 flowing through the second resistor R2 reaches a maximum value.
By way of example, the first bias signal VBP and the second bias signal VBN may be set to fixed values, which are generated by a bias circuit (not shown) capable of stably outputting the bias voltage in the prior art and provided to the auxiliary circuit 230 (including 230a and 230b). In a normal state, the third transistor M3 and the fourth transistor M4 are pressed into a depth linear region by the first bias signal VBP and the second bias signal VBN, respectively. At this time, the current I1 flowing through the first resistor R1 and the current I2 flowing through the second resistor R2 are very low, which will not cause the drive circuit to introduce the offset voltage. When voltage conversion is required in the drive circuit, taking the first output signal Vout1 as an example, the voltage value of the first output signal Vout1 decreases and the current I1 flowing through the first resistor R1 increases. However, when the voltage value of the first output signal Vout1 drops to a certain value, the third transistor M3 enters the saturation region, and at this time the current I1 flowing through the first resistor R1 will no longer increase, that is, the current I1 flowing through the first resistor R1 reaches the maximum value at this time. As long as the maximum value is smaller than the tail current I3 of the first stage circuit 210, the voltage value of the first output signal Vout1 may continue to decrease without causing the problem that the voltage conversion rate of the drive circuit decreases.
Similarly, taking the second output signal Vout2 as an example, when the voltage value of the second output signal Vout2 increases, the current I2 flowing through the second resistor R2 increases. However, when the voltage value of the second output signal Vout2 increases to a certain value, the fourth transistor M4 enters the saturation region, and at this time the current I2 flowing through the second resistor R2 will no longer increase, that is, the current I2 flowing through the second resistor R2 reaches the maximum value at this time. As long as the maximum value is smaller than the tail current I3 of the first stage circuit 210, the voltage value of the second output signal Vout2 may continue to decrease without causing the problem that the voltage conversion rate of the drive circuit decreases.
It should be appreciated by those skilled in the art that the structures shown in
The present disclosure further provides a display drive chip, including a plurality of display units and at least one drive circuit as described above, where the plurality of display units are connected to a third end of a second stage circuit 220 of the drive circuit. The third end of the second stage circuit 220 may be an end of the second stage circuit 220 which is connected to the load, namely, an end which outputs the third output signal Vout3. The plurality of display units are the load mentioned above, and the capacitance values of the plurality of display units are the load capacitance of the drive circuit.
The present disclosure further provides a display apparatus, including the above display drive chip. The display drive chip according to the embodiment of the present disclosure may be formed as a universal drive chip and may be applied to display panels with different sub-pixel arrays, thereby reducing the design cost and the manufacturing cost.
In one possible implementation, the display unit includes a display panel, where the display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small pitch display panel.
The present disclosure further provides an electronic apparatus, including the above display apparatus.
By way of example, the electronic apparatus in the embodiment includes, but is not limited to, a desktop computer, a television, a mobile device with a large-size screen such as a mobile phone and a tablet computer, and other common electronic apparatuses that require multiple chips to be connected in cascade to realize the drive.
By way of example, the electronic apparatus may also be a User Equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, a vehicle-mounted device, or the like. By way of example, some examples of terminals include a monitor, a smartphone or portable device, a mobile phone, a tablet computer, a laptop computer, a palmtop computer, a Mobile Internet device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in Industrial Control, a wireless terminal in self-driving, a wireless terminal in remote medical surgeries, a wireless terminal in Smart Grid, a wireless terminal in Transportation Safety, a wireless terminal in Smart City, a wireless terminal in Smart Home, a wireless terminal in Internet of Vehicles, and the like. For example, the server may be a local server or a cloud server.
Although the embodiments of the present disclosure have been described above, it will be appreciated that the above descriptions are merely exemplary, but not exhaustive, and is not limited to the disclosed embodiments. A number of variations and modifications may occur to one skilled in the art without departing from the scopes and spirits of the described embodiments. The terms used herein are selected to best explain the principles, practical applications, or improvements to techniques in the market of the embodiments, or to make the embodiments disclosed herein understandable to those skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210821620.6 | Jul 2022 | CN | national |
The present application is a continuation of International Application PCT/CN2023/106798, filed Jul. 11, 2023, which claims the benefit of a priority of Chinese patent application No. 202210821620.6, filed with the China National Intellectual Property Administration on Jul. 12, 2022, the entire contents of all of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/106798 | Jul 2023 | WO |
| Child | 18637164 | US |
