Patent Application
20210350758
The present application claims priority to the Chinese Patent Application No. CN201811282987.5, filed to the Chinese Patent Office on Oct. 31, 2018, and entitled “DRIVE CIRCUIT, DISPLAY MODULE DRIVING METHOD AND DISPLAY MODULE” which is incorporated herein by reference in its entirety.
The present application relates to the technical field of display, and in particular to a drive circuit, a display module driving method and a display module,
The statements in this section merely provide background information related to the present application and may not constitute prior art.
Along with the development and progress of science and technology, a Liquid Crystal Display (LCD) has become a mainstream display product and is widely applied because of hot points such as a thin body power saving and low radiation. It is known by an inventor that most LCDs are backlight type LCDs and each LCD includes a liquid crystal panel and a backlight module. A working principle of the liquid crystal panel is to place liquid crystal molecules into two parallel glass substrates and apply a drive voltage onto the two glass substrates to control rotation directions of the liquid crystal molecules, thereby refracting light rays of the backlight module to generate a picture.
When the liquid crystal panel is just started, a Timing Controller Integrated Circuit (TCON IC) takes a certain time to read an external code and complete initial configuration settings of a register inside the IC, and as a matter of fact, an output of the TCON IC is in an unstable state during this period of time, so a condition of an abnormal startup screen is occurred easily. This is mainly solved by pushing a turn-on time of a backlight module back to some extent during just starting, i.e., when the TCON IC is unstable, the backlight module is not turned on first and then after the output of the TCON IC is stable, the backlight module is turned on. However, such a manner prolongs the starting time, resulting in a complaint of a user.
An object of the present application provides a drive circuit, a display module driving method and a display module to solve an abnormal startup screen of a display panel.
The present invention provides a drive circuit, which includes:
Optionally the control circuit includes a third resistor, a third Metal Oxide Semiconductor (MOS) tube and a fourth MOS tube; the fourth MOS tube is an N-type MOS tube; the third MOS tube is a P-type MOS tube;
Optionally, the control circuit further includes a first resistor, a second resistor, a first MOS tube and a second MOS tube; the first MOS tube is an N-type MOS tube; the second MOS tube is a P-type MOS tube;
The present application further discloses a display module driving method, which includes:
Optionally, after the display panel is started, a step of turning on a backlight module of a display module and the step of performing, by a timing control chip, initial configurations are performed simultaneously, so that the time is further saved.
Optionally, the timing control chip outputs the state signal to a gate drive circuit of the display screen of the display panel, thereby controlling whether the display screen of the display panel displays the picture or not.
Optionally the display panel further includes a control circuit; the control circuit detects a state of the timing control chip, and outputs a ready signal to the display screen;
Optionally, the step of outputting, by the timing control chip, the state signal to the control circuit according to an initial configuration state includes:
The present application further discloses a display module using the above-mentioned driving method, which includes:
Optionally, the backlight module includes a backlight source and a light source drive circuit; and when the display panel is started. While the digit source drive circuit is turned on, the timing control chip performs initial configurations.
Optionally, the display screen includes a gate drive circuit; the control circuit outputs the state signal to the gate drive circuit of the display screen to control picture display of the display panel; and
Compared with a solution in which a turn-on time of a backlight module is pushed back to some extent during just starting, i.e., when the TCON IC is unstable, the backlight module is not turned on first, and then after an output of the TCON IC is stable, the backlight module is turned on, in the present application, when the display panel is started, the timing control chip performs the initial configurations; and meanwhile, the backlight module is turned on, one state signal is output in the timing control chip, and the picture display of the display panel is controlled according to the state signal; therefore, the effect that the picture display of the display panel may be controlled when the timing control chip performs initialization is implemented, and a condition of the abnormal screen due to the fact that a picture is already opened when the timing control chip hasn't finished all configurations is prevented.
The drawings are included to provide further understanding of embodiments of the present application, which constitute a part of the specification and illustrate the embodiments of the present application, and describe the principles of the present application together with the text description. Apparently, the accompanying drawings in the following description show merely some embodiments of the present application, and a person of ordinary skill in the art may still derive other accompanying drawings from these accompanying drawings without creative efforts. In the accompanying drawings:
The specific structure and function details disclosed herein are merely representative, and are intended to describe exemplary embodiments of the present application. However, the present application can be specifically embodied in many alternative forms, and should not be interpreted to be limited to the embodiments described herein.
In the description of the present application, it should be understood that, orientation or position relationships indicated by the terms “center”, “transversal”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, etc. are based on the orientation or position relationships as shown in the drawings, for ease of the description of the present application and simplifying the description only, rather than indicating or implying that the indicated device or element must have a particular orientation or be constructed and operated in a particular orientation. Therefore, these terms should not be understood as a limitation to the present application. In addition, the terms such as “first” and “second” are merely for a descriptive purpose, and cannot be understood as indicating or implying a relative importance, or implicitly indicating the number of the indicated technical features. Hence, the features defined by “first” and “second” can explicitly or implicitly include one or more features. In the description of the present application, “a plurality of” means two or more, unless otherwise stated. In addition, the term “include” and any variations thereof are intended to cover a non-exclusive inclusion.
In the description of the present application, it should be understood that, unless otherwise specified and defined, the terms “install”, “connected with”, “connected to” should be comprehended in a broad sense. For example, these terms may be comprehended as being fixedly connected, detachably connected or integrally connected; mechanically connected or coupled; or directly connected or indirectly connected through an intermediate medium, or in an internal communication between two elements. The specific meanings about the foregoing terms in the present application may be understood by those skilled in the art according to specific circumstances.
The terms used herein are merely for the purpose of describing the specific embodiments, and are not intended to limit the exemplary embodiments. As used herein, the singular forms “a”, “an” are intended to include the plural forms as well, unless otherwise indicated in the context clearly. It will be further understood that the terms “comprise” and/or “include” used herein specify the presence of the stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or combinations thereof.
The present application will be further described below in combination with the accompanying drawings and optional embodiments.
As shown in
In this solution, when the display panel 11 is started, the timing control chip 210 performs the initial configurations; meanwhile, the backlight module 120 is turned on, one state signal is output in the timing control chip 210, and the picture display of the display panel 110 is controlled according to the state signal; therefore, the effect that the picture display of the display panel 110 may be controlled when the timing control chip 210 performs initialization is implemented, and a condition of an abnormal screen due to the fact that a picture is already opened when the timing control chip 210 hasn't finished all configurations is prevented.
In one embodiment, the control circuit 230 includes a third resistor 231, a third MOS tube 232 and a fourth MOS tube 233; the fourth MOS tube 233 is an N-type MOS tube; the third MOS tube 232 is a P-type MOS tube; the control circuit 230 further includes a first level signal 238, a second level signal 239 and a logic level signal 240; a gate terminal of the third MOS tube is connected to the state signal, a source terminal of the third MOS tube is connected to the logic level voltage signal, and a drain terminal of the third MOS tube is connected to the first level signal via the third resistor; a gate terminal of the fourth MOS tube is connected between the drain terminal of the third MOS tube and the third resistor 231, a source terminal of the fourth MOS tube is connected to the first level signal 238, and a drain terminal of the fourth MOS tube is connected to a display panel 110; when the state signal is the first level signal 238, the third MOS tube 232 is connected; the gate terminal of the fourth MOS tube 233 is pulled up by the logic level signal 240 to the second level signal 239 and is connected; and the ready signal outputs the first level signal 238 to take as an output signal of the control circuit 230 to output to the display panel 110.
In this solution, the fourth MOS tube 233 is the N-type MOS tube. the third MOS tube 232 is the P-type MOS tube, the N-type MOS tube is disconnected upon the reception of the first level signal 238 and the P-type MOS tube is connected upon the reception of the first level signal 238; the third MOS tube 232 receives the state signal first in the control circuit 230; when the timing control chip 210 sends out the state signal of the first level signal 238, the grid terminal of the third MOS tube 232 is connected upon the reception of the state signal of the first level signal 238, so that the logic level signal 240 is transmitted to the grid terminal of the fourth MOS tube 233; and moreover, since the logic level signal 240 is the second level signal 239, the fourth MOS tube 233 is connected. Therefore, the first level signal 238 connected to the source terminal of the fourth MOS tube 233 is transmitted to the gate drive circuit 220, and the gate drive circuit 220 controls the display panel 10 not to display
In one embodiment, the control circuit 230 further includes a first resistor 234, a second resistor 235, a first MOS tube 236 and a second MOS tube 237; the first MOS tube 236 is an N-type MOS tube; the second MOS tube 237 is a P-type MOS tube; a gate terminal of the first MOS tube 236 is connected to the state signal and the gate terminal of the third MOS tube 232, a source terminal of the first MOS tube 236 is connected to a ground terminal, and a drain terminal of the first MOS tube 236 is connected to the second level signal 239 sequentially via the second resistor 235 and the first resistor 234; a gate terminal of the second MOS tube 237 is connected to the drain terminal of the first MOS tube 236 via the second resistor 235, a source terminal of the second MOS tube 237 is connected to the second level signal 239, and a drain terminal of the second MOS tube 237 is connected to the display panel 110; and when the state signal outputs the second level signal 239, the third MOS tube 232 is disconnected; meanwhile, the first MOS tube 236 is connected; the gate terminal of the second MOS tube 237 is pulled down by the ground terminal and is connected; and the ready signal outputs the second level signal 239 to take as an output signal of the control circuit 230 to output to the gate drive circuit 220.
In this solution, the first MOS tube 236 is the N-type MOS tube, the second MOS tube 237 is the P-type MOS tube, the N-type MOS tube is connected upon the reception of the second level signal 239 and the P-type MOS tube is disconnected upon the reception of the second level signal 239; the first MOS tube 236 and the third MOS tube 232 receive the state signal first in the control circuit 230; when the timing control chip 210 sends out the state signal of the second level signal 239, the grid terminal of the first MOS tube 236 is connected upon the reception of the state signal of the second level signal 239, so that a signal of the ground terminal is transmitted to the grid terminal of the second MOS tube 237; and moreover, since the signal of the ground terminal is the first level signal 238, the second MOS tube 237 is connected, Therefore, the second level signal 239 connected to the source terminal of the second MOS tube 237 is transmitted to the gate drive circuit 220, and the gate drive circuit 220 controls the display panel 10 to display upon the reception of the first level signal 238.
As another embodiment of the present application, referring to
When the display panel 110 is started, the timing control chip 210 performs the initial configurations; meanwhile, the backlight module 120 is turned on, one state signal is output in the timing control chip 210, and the picture display of the display panel 110 is controlled according to the state signal; therefore, the effect that the picture display of the display panel 110 may be controlled when the timing control chip 210 performs initialization is implemented, and a condition of an abnormal screen due to the fact that a picture is already opened when the timing control chip 210 hasn't finished all configurations is prevented.
In one embodiment, after the display panel 110 is started, the step that the backlight module 120 of the display module 100 is turned on and the step that the timing control chip 210 performs the initial configurations are performed simultaneously, so that the time is further saved.
In this solution, when the display panel 110 is started, the step that the backlight module 120 of the display module 100 is turned on and the step that the timing control chip 210 performs the initial configurations are performed simultaneously. Since the two steps may be performed simultaneously, the operation of other programs is not interfered, and the time of turning on the display screen may further be reduced, thereby facilitating the use of a user and saving the time that the user waits for startup.
In one embodiment, the timing control chip 210 outputs the state signal to a gate drive circuit of the display screen of the display panel 110, thereby controlling whether the display screen of the display panel 110 displays the picture or not. In this solution, the timing control chip 210 outputs the state signal to the gate drive circuit 200 of the display screen of the display panel 110, and may control, according to the state signal, whether the display screen of the display panel 110 displays the picture or not, so the condition of the abnormal picture display of the display screen due to the fact that the configurations of the timing control chip 210 haven't been finished and the timing control chip 210 is unstable when the display panel 110 is started is prevented.
In one embodiment, the display panel 110 further includes a control circuit 230. The control circuit 230 detects a state of the timing control chip 210, and outputs a ready signal to the gate drive circuit The step that the timing control chip 210 outputs a state signal includes: when the timing control chip 210 is in a code reading and configuration process, the timing control chip 210 controls to output a state signal of a first level signal 238 to the control circuit 230; and after the timing control chip 210 finishes all code configurations, the timing control chip 210 outputs a state signal of a second level signal 239 to the control circuit 230.
In this solution, the timing control chip 210 may output the state signal of the first level signal 238 according to an own configuration condition after the display panel is started and before the configurations are finished, and may further output the state signal of the second level signal 239 after all configurations are finished. Through a state of the state signal, the control circuit 230 is notified of a configuration condition of the timing control chip 210. Therefore, the display panel 11 may be controlled to perform different displays according to different states, and a condition that the backlight module is turned on in advance to see the abnormal startup screen and the like is prevented.
In one embodiment, the step that whether a display screen of a display panel displays a picture or not is controlled includes: when it is detected that the state signal output by the timing control chip 210 is the first level signal 238, the ready signal of the first level signal 238 is output to the display screen; and when the state signal received by the control circuit 230 is the second level signal 239, the control circuit 230 outputs the state signal of the second level signal. In this solution, the first level signal is a high level, the second level signal is a low level, the first level signal of the state signal is a high level RH, the second level signal of the state signal is an RL, the first level signal of the ready signal is a VGH and the second level signal of the ready signal is a VGL.
In this solution, when the state signal received by the control circuit 230 is the first level signal 238, the control circuit 230 outputs the ready signal of the first level signal 238; and when the state signal received by the control circuit 230 is the second level signal 239, the control circuit 230 outputs the ready signal of the second level signal 239. In this way, the control circuit 230 may know a configuration state of the timing control chip 210 according to the state of the state signal; if the timing control chip 210 is in the configuration state and does not finish all configurations, the work of a data drive chip is disconnected; since a voltage difference between two ends of the liquid crystal panel is zero, the penetration of the light cannot be controlled and a black screen appears. As a result, even though the backlight module is turned on in advance, there is no phenomenon that the user sees the abnormal startup screen; and moreover, when the timing control chip 210 finishes the configurations, since the backlight module 120 is turned on early and completes the preparation, the picture display may be performed immediately as long as an output port of the data drive chip is restored by the control circuit 230, and thus the starting time is saved.
In one embodiment, the step that the timing control chip 210 outputs the state signal to the control circuit 230 according to an initial configuration state includes: when the timing control chip 210 does not finish the configurations, the timing control chip 210 outputs the first level signal 238 to take as the state signal to send to the control circuit 230.
In this solution, when the display panel 110 is started, the timing control chip 210 does not finish the initial configurations; and meanwhile, the timing control chip 210 correspondingly outputs the first level signal 238 according to a state that the initial configurations are unfinished to take as the state signal and then sends the state signal to the control circuit 230; with the judgment of MOS tubes in the control circuit 230, the first level signal 238 is output to the display panel 110; and after the display panel 110 receives the first level signal 238, the liquid crystal panel cannot be charged and the display panel 110 maintains the black screen display.
In one embodiment, the step that the timing control chip 210 outputs the state signal to the control circuit according to an initial configuration state includes: when the timing control chip 210 finishes all configurations, the timing control chip 210 outputs the second level signal 239 to take as the state signal to send to the control circuit 230.
In this solution, when the timing control chip 210 detects that the configurations of the initial code are finished, the timing control chip 210 correspondingly outputs the second level signal 239 according to a state that the initial configurations are finished to take as the state signal and then sends the state signal to the control circuit 230; with the judgment of MOS tubes in the control circuit 230, the second level signal 239 is output to the display panel 110; and after the gate drive circuit 220 receives the second level signal 239, the liquid crystal panel is charged and the display panel starts to normally display the picture.
As another embodiment of the present application, referring to
S51: A display panel 110 is started, and a timing control chip 210 reads an initial node with an external memory and configures the initial code.
S52-1: The timing control chip 210 detects that a configuration state of the initial code is unfinished, and the timing control chip 210 outputs a state signal of a first level signal 238 to the control circuit 230.
S53-1: A gate terminal of a third MOS tube 232 is connected to the state signal, a source terminal of the third MOS tube 232 is connected to a logic level signal 240, and a drain terminal of the third MOS tube 232 is connected to the first level signal 238 via a third resistor 141.
S54-1: A gate terminal of a fourth MOS tube 233 is connected between the drain terminal of the third MOS tube 232 and the third resistor 141, a source terminal of the fourth MOS tube 233 is connected to the first level signal 238, and a drain terminal of the fourth MOS tube 233 is connected to the display panel 110.
S55-1: When the state signal is the first level signal 238, the third MOS tube 232 is connected; the gate terminal of the fourth MOS tube is pulled up by the logic voltage level signal 240 to a second level signal 239 and is connected; and the state signal outputs the first level signal 238 to take as a ready signal of the control circuit 230 to output to a gate drive circuit 220.
S56-1: The gate drive circuit 220 receives the ready signal of the first level signal, and the gate drive circuit 220 controls the display panel 110 to display a black screen.
S52-2: The timing control chip 210 detects that the configuration state of the initial code is finished, and the timing control chip 210 outputs a state signal of the second level signal 239 to the control circuit 230.
S53-2: A gate terminal of a first MOS tube 236 is connected to the state signal and the gate terminal of the third MOS tube 232, a source terminal of the first MOS tube 236 is connected to a ground terminal, and a drain terminal of the first MOS tube 236 is connected to the second level signal 239 sequentially via a second resistor 145 and a first resistor 144.
S54-2: A gate terminal of a second MOS tube 237 is connected to the drain terminal of the first MOS tube 236 via the second resistor 145, a source terminal of the second MOS tube 237 is connected to the second level signal 239, and a drain terminal of the second MOS tube 237 is connected to the gate drive circuit 220.
S55-2: When the state signal outputs the second level signal 239, the third MOS tube 232 is disconnected; meanwhile, the first MOS tube 236 is connected; the gate terminal of the second MOS tube 237 is pulled down by the ground terminal and is connected; and the ready signal outputs the second level signal 239 to take as a control signal of the control circuit 230 to output to the gate drive circuit 220 to control the display panel.
S56-2: The gate drive circuit 220 receives a ready signal of the second level signal, and the gate drive circuit 220 controls the display panel 110 to restore the display.
In this solution, the first MOS tube 236 and the fourth MOS tube 233 are the N-type MOS tubes, the second MOS tube 237 and the third MOS tube 232 are the P-type MOS tubes, the N-type MOS tubes are disconnected upon the reception of the first level signal 238, and the P-type MOS tubes are connected upon the reception of the first level signal 238. The third MOS tube 232 receives the state signal first in the control circuit 230. When the display panel 110 is started, the timing control chip 210 reads the initial code with the external memory via a protocol and performs the initial configurations; when the timing control chip 210 detects that the configuration state of the initial code is unfinished, the state signal of the first level signal 238 is sent out, and the grid terminal of the third MOS tube 232 is connected upon the reception of the state signal of the first level signal 238, so that the logic level signal 240 is transmitted to the grid terminal of the fourth MOS tube 233; and moreover, the logic level signal 240 is the second level signal 239, the fourth MOS tube 233 is connected. Therefore, the first level signal 238 connected to the source terminal of the fourth MOS tube 233 is transmitted to the gate drive circuit 220, and after the gate drive circuit 220 receives the first level signal 238, the display panel does not display. The first MOS tube 236 and the third MOS tube 232 receive the state signal first in the control circuit 230. When the display panel 110 is started, the timing control chip 210 reads the initial code with the external memory via the protocol and performs the initial configurations; when the timing control chip 210 detects that the configuration state of the initial code is finished, the state signal of the second level signal 239 is sent out, and the grid terminal of the first MOS tube is connected upon the reception of the state signal of the second level signal 239, so that a signal of the ground terminal is transmitted to the grid terminal of the second MOS tube 237; and moreover, the signal of the ground signal is the first level signal 238, the second MOS tube 237 is connected. Therefore, the second level signal 239 connected to the source terminal of the second MOS tube 237 is transmitted to the gate drive circuit 220, and after the gate drive circuit 220 receives the level signal 238, the display panel starts to display
As another embodiment of the present application, referring to
In this solution, when the display panel 110 is started, the timing control circuit 210 performs the initial configurations; meanwhile, a state signal is output in the timing control circuit 210 and is transmitted to the control circuit 230; and the control circuit 230 outputs the ready signal to a gate drive circuit of a display screen via internal control, thereby controlling the picture display of the display panel 110. In one embodiment, the backlight module 120 includes a backlight source and a light source drive circuit; and when the display panel 110 is started, while the light source drive circuit is turned on, the timing control chip 210 performs the initial configurations.
In this solution, when the display panel 110 is started, the step that the backlight source of the display module 100 is turned on and the step that the timing control chip 210 performs the initial configurations are performed simultaneously. Since the two steps may be performed simultaneously, the operation of other programs is not interfered, and the time of turning on the display screen may further be reduced, thereby facilitating the use of a user and saving the time that the user waits for starting up.
In one embodiment, the display screen includes a gate drive circuit; the control circuit 230 outputs the ready signal to the gate drive circuit of the display screen to control picture display of the display panel 110; and
In this solution, the display screen is provided with the gate drive circuit to receive the ready signal output by the control circuit 230. The gate drive circuit controls the picture display of the display panel 110 upon the reception of the ready signal, and thus the abnormal screen due to the fact that the timing control chip 210 performs the initial configurations when the display panel 110 is started may be controlled.
It is to be noted that, the limit on each step related in this solution is not considered as a limit to a sequential order of the steps on the premise of not affecting implementation of a specific solution. A step written in front may be executed ahead and may also be executed later, or even may also be executed simultaneously; and as long as this solution can be implemented, all should be considered as a scope of protection of the present application.
In the present application, the panel may be a Twisted Nematic (TN) panel, an In-Plane Switching (IPS) panel, a Multi-domain Vertical Alignment (VA) panel, and of source, may also be other types of appropriate panels.
The above are further detailed descriptions of the present application in combination with specific optional implementation manners and should not be deemed as that the specific implementation of the present application is only limited to these descriptions. A person of ordinary skill in the art to which the present application belongs may further make a plurality of simple deviations or replacements without departing from the concept of the present application and all should be considered as the scope of protection of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201811282987.5 | Oct 2018 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/115210 | 11/13/2018 | WO | 00 |
