Patent Grant
9424778
The present disclosure relates to a drive circuit that drives a light emitting device such as an organic EL, to a driving method, to a display unit that includes such a drive circuit, and to an electronic apparatus.
In recent years, in a field of display units that perform image display, there has been developed and commercialized a display unit (an organic EL display unit) that uses, as a light emitting device, a current-driven optical device in which light emission luminance varies in accordance with a value of a current passing therethrough, for example, an organic EL (Electro Luminescence) device. Unlike a device such as a liquid crystal device, the organic EL device is a self-emitting device, and it is not necessary to provide a light source (a backlight) therefor. Therefore, the organic EL display unit has characteristics such as high visibility of an image, low power consumption, and high response speed of device, compared to the liquid crystal display unit in which the light source is necessary.
As a driving scheme of the organic EL display unit, there are a simple (passive) matrix scheme and an active matrix scheme as with the liquid crystal display unit. The former has a simple structure; however, has an issue such as difficulty in achieving large and high-definition display unit. Therefore, currently, the latter active matrix scheme has been actively developed (for example, Patent Literature 1, etc.). In this scheme, a current that passes through an organic EL device arranged for each pixel is controlled by a transistor in a pixel circuit provided for each organic EL device.
By the way, in the display unit, defects such as a point defect (a dot defect) and a line defect may occur in some cases in manufacturing. Such defects such as the point defect and the line defect may be often noticeable for a user. A user who has purchased a display unit that has many defects as described above feels unfairness. Therefore, reduction in such defects is desired.
Accordingly, it is desirable to provide a drive circuit, a driving method, a display unit, and an electronic apparatus that are capable of reducing defects in display.
A drive circuit of an embodiment of the present technology includes a drive section driving a plurality of pixel circuits by line-sequential scanning. On a plurality of the pixel circuits belonging to one horizontal line, the above-described drive section performs a first preparation drive based on a first voltage in a first preparation period, then performs a second preparation drive based on the first voltage in a second preparation period, and performs writing of luminance information in a subsequent writing period. The second preparation period ends at a timing out of the first preparation periods of other horizontal lines.
A driving method of an embodiment of the present disclosure includes: at a time of driving a plurality of pixel circuits by line-sequential driving, on a plurality of the pixel circuits belonging to one horizontal line, performing a first preparation drive based on a first voltage in a first preparation period; then performing a second preparation drive based on the first voltage in a second preparation period, the second preparation period ending at a timing out of the first preparation periods of other horizontal lines; and performing writing of luminance information in a subsequent writing period.
A display unit of an embodiment of the present disclosure includes a plurality of pixel circuits, and a drive section driving the plurality of pixel circuits by line-sequential scanning. On a plurality of the pixel circuits belonging to one horizontal line, the above-described drive section performs a first preparation drive based on a first voltage in a first preparation period, then performs a second preparation drive based on the first voltage in a second preparation period, and performs writing of luminance information in a subsequent writing period. The second preparation period ends at a timing out of the first preparation periods of other horizontal lines.
An electronic apparatus of an embodiment of the present disclosure includes the above-described display unit. Examples thereof may include a television apparatus, a digital camera, a personal computer, a video camcorder, and a mobile terminal apparatus such as a mobile phone.
In the drive circuit, the driving method, the display unit, and the electronic apparatus according to some embodiments of the present disclosure, at the time of driving the plurality of pixel circuits, on the plurality of pixel circuits belonging to one horizontal line, the first preparation drive is performed based on the first voltage in the first preparation period, the second preparation drive is performed based on the first voltage in the subsequent second preparation period, and the writing of the luminance information is performed in the subsequent writing period. At that time, the second preparation period ends at the timing out of the first preparation periods of other horizontal lines.
According to the drive circuit, the driving method, the display unit, and the electronic apparatus according to some embodiments of the present disclosure, the second preparation period of one horizontal line ends at the timing out of the first preparation period of other horizontal lines. Therefore, it is possible to reduce defects in display.
Some embodiments of the present disclosure will be described below in detail referring to the drawings. It is to be noted that the description will be given in the following order.
1. First Embodiment
2. Second Embodiment
3. Application Examples
The display panel 10 includes a pixel array section 13, and performs pixel display by active matrix drive. In the pixel array section 13, a plurality of pixels 11 are arranged in a matrix. Here, each pixel 11 is configured of a pixel 11R for red, a pixel 11G for green, and a pixel 11B for blue. It is to be noted that, hereinafter, “pixel 11” is appropriately used collectively referring to the pixel 11R, the pixel 11G, and the pixel 11B.
The pixel array section 13 includes a plurality of scanning lines WSL, a plurality of power lines DSL, and a plurality of data lines DTL. The plurality of scanning lines WSL and the plurality of power lines DSL extend in a row direction. The plurality of data lines DTL extend in a column direction. One end of each of these scanning lines WSL, power lines DSL, and data lines DTL is connected to the drive circuit 20. Each of the above-described pixels 11 is arranged at an intersection of the scanning line WSL and the data line DTL.
The writing transistor Tr1 and the driving transistor Tr2 may each be configured, for example, of a TFT (Thin Film Transistor) of an n-channel MOS (Metal Oxide Semiconductor) type. A gate of the writing transistor Tr1 is connected to the scanning line WSL, a source thereof is connected to the data line DTL, and a drain thereof is connected to a gate of the driving transistor Tr2 and one end of the capacitor Cs. The gate of the driving transistor Tr2 is connected to the drain of the writing transistor Tr1 and the one end of the capacitor Cs, a drain thereof is connected to the power line DSL, and a source thereof is connected to the other end of the capacitor Cs and an anode of the organic EL device 12. It is to be noted that a type of TFT is not particularly limited, and may be, for example, an inverse-staggered structure (a so-called bottom-gate type) or a staggered structure (a so-called top-gate type).
The one end of the capacitor Cs is connected to the gate of the driving transistor Tr2, and the other end thereof is connected to the source of the driving transistor Tr2. The organic EL device 12 is a light emitting device that emits light of a color corresponding to each of the pixels 11R, 11G, and 11B. The anode of the organic EL device 12 is connected to the source of the driving transistor Tr2 and the other end of the capacitor Cs, and a cathode thereof is grounded. One end of the capacitor Csub is connected to the anode of the organic EL device 12, and the other end thereof is grounded.
The drive circuit 20 drives the display panel 10 based on an image signal Sdisp and a synchronization signal Ssync that are supplied from outside. As shown in
The image signal processing circuit 21 performs predetermined correction on the digital image signal Sdisp supplied from the outside, and outputs a corrected image signal Sdisp2 to the data line drive circuit 24. Examples of this predetermined correction may include gamma correction and overdrive correction.
The timing generation circuit 22 is a circuit that supplies a control signal to each of the control signal scanning line drive circuit 23, the data line drive circuit 24, and the power line drive circuit 25, based on the synchronization signal Ssync inputted from the outside, and that performs control to allow these circuits to operate in synchronization with one another.
The scanning line drive circuit 23 sequentially applies scanning line signals WS to the plurality of scanning lines WSL in accordance with the control signal supplied from the timing generation circuit 22, and thereby, sequentially selects the plurality of pixels 11. Specifically, the scanning line drive circuit 23 selectively outputs a voltage Von and a voltage Voff, and thereby, generates the above-described scanning line signals WS. The voltage Von is to be applied when the writing transistor Tr1 is set to an ON state. The voltage Voff is to be applied when the writing transistor Tr1 is set to an OFF state.
The data line drive circuit 24 generates a data line signal Sig that includes an analog image signal (a luminance signal) in accordance with the control signal supplied from the timing generation circuit 22, and to apply the generated data line signal Sig to each data line DTL.
The D-A conversion circuit 31 performs D-A conversion on a digital signal based on the image signal Sdisp2, and thereby, generates a pixel voltage Vpix to be supplied to the pixel 11. The offset voltage generation circuit 32 generates an offset voltage Vofs (which will be described later).
The switch section 33 time-divisionally selects the pixel voltage Vpix supplied from the D-A conversion circuit 31 and the offset voltage Vofs supplied from the offset voltage generation circuit 32, based on an instruction from the switch control circuit 34, and supplies the selected voltage to the data line DTL.
The switch section 33 includes an inverter IV and switches SW1 and SW2. The inverter IV inverts an SW control signal supplied from the switch control circuit 34, and outputs the inverted signal. The switch SW1 is turned on or off based on the SW control signal supplied from the switch control circuit 34. To one end of the switch SW1, the pixel voltage Vpix is supplied from the D-A conversion circuit 31. The other end of the switch SW1 is connected to the other end of the switch SW2, and is connected to the data line DTL. The switch SW2 is turned on or off based on the output signal from the inverter IV. To one end of the switch SW2, the offset voltage Vofs is supplied from the offset voltage generation circuit 32. The other end of the switch SW2 is connected to the other end of the switch SW1, and is connected to the data line DTL.
The switch control circuit 34 generates the SW control signals for controlling ON and OFF of the switches SW1 and SW2 in the switch section 33, and supplies the generated SW control signals to the switch section 33.
Due to this configuration, the data line drive circuit 24 time-divisionally applies the offset voltage Vofs and the pixel voltage Vpix to each data line DTL, and thereby, drives each pixel 11 in the display panel 10. Specifically, as will be described later, the data line drive circuit 24 applies the offset voltage Vofs to the data line DTL in initialization periods P1 and P2 (which will be described later) and Vth correction periods P3 and P4 (which will be described later), and applies the pixel voltage Vpix to the data line DTL in a signal writing period P5 (which will be described later).
Here, as will be described later, the initialization periods P1 and P2 are each a period in which the pixel 11 is initialized by increasing a gate-source voltage Vgs of the driving transistor Tr2 in the pixel 11 to be larger than a threshold voltage Vth of the driving transistor Tr2 based on the offset voltage Vofs. Further, as will be described later, the Vth correction periods P3 and P4 are each a period in which the threshold voltage Vth of the driving transistor Tr2 is corrected based on the offset voltage Vofs. Further, the signal writing period P5 is a period in which a predetermined voltage in accordance with the pixel voltage Vpix is set between the gate and the source of the driving transistor Tr2. As will be described later, the initialization periods P1 and P2 (which will be described later) are shorter than the Vth correction periods P3 and P4 (which will be described later) in the display unit 1.
The power line drive circuit 25 sequentially applies power line signals DS to the plurality of power lines DSL in accordance with the control signal supplied from the timing generation circuit 22, and thereby controls a light emission operation and a light extinction operation of each organic EL device 12. Specifically, as will be described later, the power line drive circuit 25 applies a voltage Vini that is lower than the offset voltage Vofs to each power line DSL in the initialization periods P1 and P2 (which will be described later), and applies a voltage Vccp that is higher than the offset voltage Vofs thereto in the Vth correction periods P3 and P4 (which will be described later) and the signal writing period (P5) (which will be described later).
Here, the drive circuit 20 corresponds to a specific example of “drive section” in the present disclosure. The initialization periods P1 and P2 correspond to specific examples of “first preparation period” in the present disclosure. The Vth correction periods P3 and P4 correspond to specific examples of “second preparation period” in the present disclosure. The signal writing period P5 corresponds to a specific example of “writing period” in the present disclosure. The offset voltage Vofs corresponds to a specific example of “first voltage” in the present disclosure. The voltage Vini corresponds to a specific example of “second voltage” in the present disclosure. The voltage Vccp corresponds to a specific example of “third voltage” in the present disclosure.
[Operations and Functions]
Subsequently, description will be given on operations and functions of the display unit 1 of the present embodiment.
[Outline of General Operation]
First, outline of a general operation of the display unit 1 will be described referring to
[Detailed Operation]
Next, a detailed operation of the display unit 1 will be described.
Each pixel 11 in the display unit 1 performs the display operation by alternately repeating light emission (a light emission period P0) and light extinction (a light extinction period P10). Specifically, in the light extinction period P10, each pixel 11 first performs initialization in each of a plurality of (two, in this example) horizontal period (1H)s (the initialization periods P1 and P2), and performs Vth correction of the driving transistor Tr2 in each of a plurality of (two, in this example) horizontal periods subsequent thereto (the Vth correction periods P3 and P4). Further, the pixel voltage Vpix is written in the pixel 11 in the signal writing period P5 subsequent to the Vth correction period P4. Thereafter, the pixel 11 emits light in a light emission period P9. In other words, in this example, the display unit 1 performs the initialization, the Vth correction, and writing of a signal on each pixel 11 in a period corresponding to four horizontal periods. Hereinafter, details thereof will be described.
First, at a timing t0, the power line drive circuit 25 decreases a voltage of the power line signal DS from the voltage Vccp to the voltage Vini ((B) of
Next, in a period (the initialization period P1) from a timing t1 to a timing t2, the drive circuit 20 performs first initialization on the pixel 11. Specifically, at the timing t1, the scanning line drive circuit 23 first increases the voltage of the scanning line signal WS from the voltage Voff to the voltage Von ((A) of
Next, at the timing t2, the scanning line drive circuit 23 decreases the voltage of the scanning line signal WS from the voltage Von to the voltage Voff ((A) of
Next, in a period (the initialization period P2) from the timing t3 to a timing t4, the drive circuit 20 performs second initialization on the pixel 11. An operation thereof is similar to that in the above-described case of the initialization period P1. Specifically, at the timing t3, the scanning line drive circuit 23 first increases the voltage of the scanning line signal WS from the voltage Voff to the voltage Von ((A) of
Next, at the timing t4, the scanning line drive circuit 23 decreases the voltage of the scanning line signal WS from the voltage Von to the voltage Voff ((A) of
Next, in a period (the Vth correction period P3) from a timing t6 to a timing t7, the drive circuit 20 performs first Vth correction on the pixel 11. Specifically, prior to this Vth correction, at the timing t5, the scanning line drive circuit 23 first increases the voltage of the scanning line signal WS from the voltage Voff to the voltage Von ((A) of
This operation is a so-called negative feedback operation. Specifically, as described above, when the current Id flows between the drain and the source of the driving transistor Tr2 and the gate-source voltage Vgs decreases, the current Id between the drain and the source decreases. In other words, the current Id between the drain and the source of the driving transistor Tr2 converges toward 0 (zero) due to this negative feedback operation. In other words, the gate-source voltage Vgs of the driving transistor Tr2 converses so as to be equal to the threshold voltage Vth of the driving transistor Tr2 (Vgs=Vth) due to this negative feedback operation.
Next, at the timing t7, the scanning line drive circuit 23 decreases the voltage of the scanning line signal WS from the voltage Von to the voltage Voff ((A) of
Next, in a period (the Vth correction period P4) from the timing t8 to a timing t9, the drive circuit 20 performs second Vth correction on the pixel 11. An operation thereof is similar to that in the above-described case of the Vth correction period P3. Specifically, at the timing t8, the scanning line drive circuit 23 increases the voltage of the scanning line signal WS from the voltage Voff to the voltage Von ((A) of
Next, at the timing t9, the scanning line drive circuit 23 decreases the voltage of the scanning line signal WS from the voltage Von to the voltage Voff ((A) of
Next, in a period (the signal writing period P5) from a timing t10 to a timing t11, the drive circuit 20 performs writing of the pixel voltage Vpix on the pixel 11. Specifically, prior to this writing of the pixel voltage Vpix, the data line drive circuit 24 first increases the voltage of the data line signal Sig from the offset voltage Vofs to the pixel voltage Vpix ((E) of
Next, at the timing t11, the scanning line drive circuit 23 decreases the voltage of the scanning line signal WS from the voltage Von to the voltage Voff ((A) of
Thereafter, after a predetermined period elapses, the display unit 1 moves from the light emission period P9 (P0) to the light extinction period P10. Further, the drive circuit 20 performs drive so as to repeat this series of operations.
As shown in
The display unit 1 performs this series of operations for the respective pixels 11 on a row basis so as to allow the operations to be shifted by one horizontal period. Specifically, for example, in the display unit 1, when the pixel 11(n) in the n-th row performs the first initialization operation in the initialization period P1, the pixel 11(n−1) in the (n−1)th row may perform the second initialization operation in the initialization period P2. Similarly, for example, when the pixel 11(n) in the n-th row performs the second initialization operation in the initialization period P2, the pixel 11(n−1) in the (n−1)th row performs the first Vth correction operation in the Vth correction period P3.
As shown in
[Concerning Display Defect]
Next, description will be given on a defect of the pixel in the display unit.
Also, the defective pixel 11S is not allowed to normally perform operations such as the initialization operation and the Vth correction operation. Specifically, as shown in
Further, in the initialization periods P1 and P2, the offset voltage Vofs that has decreased as described above is supplied also to other pixels 11 via the data lines DTL as will be described below.
As shown in
Next, description will be given on an operation of the pixel 11(n−3).
As shown in
The drive circuit 20 drives the pixel 11(n−3) in a manner similar to that in the timing diagram shown in
Next, in a period (the Vth correction period P4) from a timing t38 to a timing t40, the drive circuit 20 performs the second Vth correction. Specifically, the scanning line drive circuit 23 first increases a voltage of the scanning line signal WS(n−3) from the voltage Voff to the voltage Von ((A) of
Subsequently, in a period (the signal writing period P5) from a timing t41 to a timing t42, the drive circuit 20 performs the writing of the pixel voltage Vpix in the pixel 11(n−3) in a manner similar to that in the timing diagram shown in
In such a manner, in the display unit 1, even when the point defect occurs in part (for example, the pixel 11(n)) of the pixels, it is possible to suppress the influence on the display operation in another pixel (for example, the pixel 11(n−3)), unlike in a display unit according to a comparative example which will be described later.
Next, description will be given on a display unit 1R according to the comparative example. End timings of the initialization periods P1 and P2 in the horizontal period (1H) is different from those in the case of the present embodiment. Specifically, in the present embodiment, the initialization periods P1 and P2 end earlier than the Vth correction periods P3 and P4 in another row in the horizontal period (1H). However, in the present comparative example, the initialization periods P1 and P2 end at the same time with the Vth correction periods P3 and P4 in another row in the horizontal period (1H).
As shown in
In the initialization periods P1 and P2 of the pixel 11(n) (the defective pixel 11S), because the both terminals of the capacitor Cs are short-circuited, the offset voltage Vofs of the data line signal Sig decreases by the voltage ΔV toward the voltage Vini ((E) of
A drive circuit 20R according to the display unit 1R performs drive so as to perform the first initialization on the pixel 11(n−3) in a period (the initialization period P1) from a timing r31 to a timing r32, to perform the second initialization operation on the pixel 11(n−3) in a period (the initialization period P2) from a timing r33 to a timing r34, and to perform the first Vth correction operation on the pixel 11(n−3) in a period (the Vth correction period P3) from a timing r36 to a timing r37. These operations are almost similar to those in the case of the present embodiment. It is to be noted that, in the display unit 1R, time periods of the initialization periods P1 and P2 are longer than those in the case of the present embodiment; however, the operations themselves in the initialization periods P1 and P2 are almost similar to those in the case of the present embodiment.
Next, in a period (the Vth correction period P4) from a timing r38 to a timing r40, the drive circuit 20R performs the second Vth correction. Specifically, the scanning line drive circuit 23 first increases a voltage of the scanning line signal WS(n−3) from the voltage Voff to the voltage Von ((A) of
Next, at the timing r40, the scanning line drive circuit 23 decreases the voltage of the scanning line signal WS(n−3) from the voltage Von to the voltage Voff ((A) of
Subsequently, in a period (the signal writing period P5) from a timing r41 to a timing r42, the drive circuit 20R performs the writing of the pixel voltage Vpix in the pixel 11(n−3) in a manner similar to that in the timing diagram shown in
As described above, in the display unit 1R according to the present comparative example, for example, when part of the pixels 11 includes the point defect, the display operation in other pixels may be influenced. Specifically, in the display unit 1R, as shown in
In this example, description has been given that the pixel 11(n) (the defective pixel 11S) in the n-th row influences the display operation of the pixel 11(n−3) in the (n−3)th row. However, similarly, the pixel 11(n) (the defective pixel 11S) in the n-th row also influences the display operation of the pixel 11(n−2) in the (n−2)th row. Specifically, as shown in
Moreover, this offset voltage Vofs is supplied also to the pixels 11 in another row in the display panel 10. Specifically, as shown in
Moreover, two initialization periods P1 and P2 are provided in this example. However, when more initialization periods are provided, defects in display may increase further.
On the other hand, in the display unit 1 according to the present embodiment, as shown in
In such a manner, in the display unit 1, even when part (for example, 11(n)) of the pixels 11 includes the point defect, it is possible to suppress its influence on the display operation in another pixel (for example, 11(n−3)).
[Effects]
As described above, in the present embodiment, the initialization period ends earlier than the Vth correction period in another row. Therefore, even when the pixel includes the point defect, it is possible to suppress its influence on the display operation in another pixel.
[Modification 1-1]
In the above-described embodiment, two initialization periods are provided. However, this is not limitative. For example, three or more initialization periods may be provided, or only one initialization period may be provided. Similarly, in the above-described embodiment, two Vth correction periods are provided. However, this is not limitative. For example, three or more Vth correction periods may be provided, or only one Vth correction period may be provided. An example of the present modification will be described below.
Next, description will be given on the display unit 2 according to the second embodiment. In the present embodiment, the initialization period and the Vth correction period in another row are provided in horizontal periods different from each other. It is to be noted that the same symbols are attached to components substantially the same as those in the display 2 according to the above-described first embodiment, and description thereof will be appropriately omitted.
Each of the pixels 11 in the display unit 2 performs the initialization in first and third horizontal periods out of a period corresponding to six adjacent horizontal period (1H)s (the initialization periods P1 and P2), and performs the Vth correction in fourth and sixth horizontal periods (the Vth correction periods P3 and P4). In this example, a length of each of the initialization periods P1 and P2 is almost the same as a length of each of the Vth correction periods P3 and P4. Further, the pixel signal Vpix is written in each pixel 11 in the horizontal period in which the Vth correction period P4 is provided, or in a horizontal period subsequent to the horizontal period in which the Vth correction period P4 is provided (the signal writing period P5). Thereafter, each pixel 11 emits light based on that pixel signal Vpix. Specifically, as shown in
The display unit 2 performs this series of operations on a two-row basis so as to allow the operations to be shifted by two horizontal periods. Specifically, for example, as shown in
Accordingly, in the display unit 2, as shown in
As described above, in the present embodiment, the initialization period is provided in a horizontal period different from that of the Vth correction period in another row. Therefore, even when the pixel includes the point defect, it is possible to suppress its influence on the display operation in another pixel.
[Modification 2-1]
In the above-described embodiment, the signal writing period P5 is provided in the horizontal period in which the Vth correction period P4 is provided, or in the horizontal period subsequent to the horizontal period in which the Vth correction period P4 is provided. However, at that time, the horizontal period in which this signal writing period P5 is provided may be changed for each frame. Details thereof will be described below.
In such a manner, in the present modification, the horizontal period in which the signal writing period P5 is provided is changed for each frame. As a result, in the display unit according to the present modification, for example, even when the time from performing the Vth correction in the Vth correction period P4 to writing of the pixel signal Vpix in the signal writing period influences light emission luminance of that pixel, the light emission luminance is averaged by displaying a plurality of frames, and therefore, it is possible to suppress degradation in image quality.
[Modification 2-2]
In the above-described embodiment, two initialization periods are provided. However, this is not limitative. For example, three or more initialization periods may be provided, or only one initialization period may be provided. Similarly, in the above-described embodiment, two Vth correction periods are provided. However, this is not limitative. For example, three or more Vth correction periods may be provided, or only one Vth correction period may be provided. An example of the present modification will be described below.
The display unit according to the present modification performs this series of operations on a two-row basis so as to allow the operations to be shifted by two horizontal periods. Specifically, for example, as shown in
Also in these cases, the initialization period Q1 is provided in a horizontal period different from that of the Vth correction period Q2 of another row. Therefore, as in the above-described embodiment, the Vth correction operation is allowed to be performed normally. Therefore, even when the pixel includes the point defect, it is possible to suppress its influence on the display operation in another pixel.
[Modification 2-3]
In the above-described embodiment, the initialization periods P1 and P2 are arranged in the first and third horizontal periods in the period corresponding to six adjacent horizontal period (1H)s, and the Vth correction periods P3 and P4 are arranged in the fourth and sixth horizontal periods therein. However, this is not limitative. Also, in the above-described embodiment, the length of each of the initialization periods P1 and P2 is almost the same as the length of each of the Vth correction periods P3 and P4. However, this is not limitative. For example, as shown in
Next, description will be given on application examples of the display units described in the above embodiments and modifications.
The display units according to the above-described embodiments and the like are applicable to electronic apparatuses in any field such as a digital camera, a notebook personal computer, a mobile terminal apparatus such as a mobile phone, a mobile game machine, and a video camcorder, other than the television apparatus as described above. In other words, the display units according to the above-described embodiments and the like are applicable to electronic apparatuses in any field that display an image.
The present technology has been described above referring to some modifications. However, the present technology is not limited to these embodiments and the like, and various modifications may be made.
For example, in each of the above-described embodiments, the pixel 11 has the configuration of a so-called “2Tr1C” configured using the writing transistor Tr1, the driving transistor Tr2, and the capacitor Cs. However, this is not limitative. Alternatively, for example, as shown in
For example, the organic EL device is used as the display device in each of the above-described embodiments. However, this is not limitative. Alternatively, for example, an inorganic EL device may be used.
It is to be noted that the present technology may have configurations as described below.
(1) A drive circuit including
a drive section driving a plurality of pixel circuits by line-sequential scanning,
on a plurality of the pixel circuits belonging to one horizontal line, the drive section performing a first preparation drive based on a first voltage in a first preparation period, then performing a second preparation drive based on the first voltage in a second preparation period, and performing writing of luminance information in a subsequent writing period, and the second preparation period ending at a timing out of the first preparation periods of other horizontal lines.
(2) The drive circuit according to the above-described (1), wherein the first preparation period and the second preparation period in each of the pixel circuits belong to horizontal periods different from each other.
(3) The drive circuit according to the above-described (2), wherein
the second preparation period of the one horizontal line and the first preparation period of one of the other horizontal lines belong to same horizontal period, and,
in each horizontal period, the first preparation period of one of the other horizontal lines ends earlier than the second preparation period of the one horizontal line.
(4) The drive circuit according to the above-described (3), wherein the first preparation period of one of the other horizontal lines is shorter than the second preparation period of the one horizontal line.
(5) The drive circuit according to the above-described (2), wherein the first preparation period of the one horizontal line and the second preparation period of each of the other horizontal lines belong to horizontal periods different from each other.
(6) The drive circuit according to the above-described (5), wherein the first preparation period has a length same as a length of the second preparation period.
(7) The drive circuit according to any one of the above-described (1) to (6), wherein
a plurality of the second preparation periods are provided for each of the pixel circuits,
the plurality of second preparation periods belong to horizontal periods different from one another, and
a last period of the plurality of second preparation periods ends at a timing out of the first preparation periods of the other horizontal lines.
(8) The drive circuit according to any one of the above-described (1) to (7), wherein a plurality of the first preparation periods are provided for each of the pixel circuits.
(9) The drive circuit according to any one of the above-described (1) to (8), wherein
the pixel circuits each includes a light emitting device, a transistor, and a capacitor, the transistor having a source that is connected to the light emitting device, and the capacitor being inserted between a gate and the source of the transistor,
the drive section applies the first voltage to the gate of the transistor and applies a second voltage to a drain of the transistor in the first preparation period, the second voltage being lower than the first voltage, and
the drive section applies the first voltage to the gate of the transistor and applies a third voltage to the drain of the transistor in the second preparation period, the third voltage being higher than the first voltage.
(10) The drive circuit according to the above-described (9), wherein the light emitting device is an electroluminescence device.
(11) A driving method including:
at a time of driving a plurality of pixel circuits by line-sequential driving,
on a plurality of the pixel circuits belonging to one horizontal line,
performing a first preparation drive based on a first voltage in a first preparation period;
then performing a second preparation drive based on the first voltage in a second preparation period, the second preparation period ending at a timing out of the first preparation periods of other horizontal lines; and
performing writing of luminance information in a subsequent writing period.
(12) A display unit including:
a plurality of pixel circuits; and
a drive section driving the plurality of pixel circuits by line-sequential scanning,
on a plurality of the pixel circuits belonging to one horizontal line, the drive section performing a first preparation drive based on a first voltage in a first preparation period, then performing a second preparation drive based on the first voltage in a second preparation period, and performing writing of luminance information in a subsequent writing period, and the second preparation period ending at a timing out of the first preparation periods of other horizontal lines.
(13) An electronic apparatus including:
a display unit; and
a control circuit performing operation control utilizing the display unit,
the display unit including
a plurality of pixel circuits, and
a drive section driving the plurality of pixel circuits by line-sequential scanning,
on a plurality of the pixel circuits belonging to one horizontal line, the drive section performing a first preparation drive based on a first voltage in a first preparation period, then performing a second preparation drive based on the first voltage in a second preparation period, and performing writing of luminance information in a subsequent writing period, and the second preparation period ending at a timing out of the first preparation periods of other horizontal lines.
This application claims priority on the basis of Japanese Patent Application JP 2011-235045 filed Oct. 26, 2011 in Japan Patent Office, the entire contents of each which are incorporated herein by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
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